Re: [PEDA] Power supply pins
Hello and thank you for your extensive response.
I do apologise for not getting back to you earlier but have been fairly busy.
I think it is generally good practise to always have EVERY pin exposed even power
supply pins but I do feel that putting the power pins off to one side is a neater way
than having as part of a main component symbol. The only problem I have found so far,
and I can't explain why, is that putting the power parts on to a separate page
resulted in Protel wanting to add a complete extra chip to the pcb when I did an
update.
I will study your other comments but am often amazed at how much extra work one has to
do sometimes to achieve a basic feature - not bad for ASU$9000!
Best Regards
Laurie Biddulph
http://www.elby-designs.com
- Original Message -
From: Abd ul-Rahman Lomax
To: Protel EDA Forum
Sent: Friday, December 12, 2003 5:07 AM
Subject: Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital supply. This,
by the way, is a very common error in designs we receive as a service
bureau, and we do try to notice it and query the engineer.)
Problem is Protel 99 doesn't like annotating these as it treats the
power part as a real part and really gets messed up. I believe Protel DXP
lets you assign the power supply pins to Part 0 and so, presumably, gets
round the problem.
I haven't looked into that aspect of DXP yet. The problem in P99 (and
earlier) is only with automatic annotation. I think one could get around
the problem by having two libraries: one would be the components with no
power pins (or with them as part of the main symbols), the other would have
the same parts with power pins removed. The schematic would be drawn, at
first, with the parts from the first library, and annotated. Then the
symbols would all be updated from the second library, and then the power
page would be added to the schematic. There are some caveats with updating
symbols, but I'm a bit rusty on that topic
Beyond that, manually assigning parts is normally not such a huge task. If
there is a way in DXP to exclude a symbol part from the autoannotation
task, this would indeed be an improvement.
But there is usually manual attention needed to annotation, to cluster
logic functions, for example, on the same device so that signals remain
local instead of running across the board and back just to run through an
inverter. I'll often allow a few sections to be unused, more than the
absolute minimum, just to keep signals together. Logic functions are
generally cheap.
Hiding power pins is bad news especially if you use different power rails
from, say, VCC and GND which are the common defaults for logic chips and
so if you forget to unhide them you end up with a power net not going
anywhere near your real power supply.
Protel does not handle this probem as well as DOS Tango did. Tango allowed
sheet-wise net
Re: [PEDA] Protel 99SE ERC
Yes, it would flag that too. It would be considered a warning of a net without a drive source. However, it flags lots of those in a design, so you might ignore it. (another reason not to ignore warnings.) Tony -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED] Sent: Friday, December 19, 2003 6:43 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel 99SE ERC ok, point taken, thanks for the encouragement, keep 'em coming how about this one: i once had a power port symbol +12V2 connected to one end of a resistor the rest of the board was all +12V for that power and i didn't notice it good 'ol cut and paste - it wasn't my fault! :) anyway the resistor didn't go anywhere on one end and in the usual mad proto rush it was shipped because the DRC was happy does DXP catch this ? BTW, this is not a 'single pin net' since the netlist shows 2 items: +12V2 R112-2 the 'isolated' power port counts kind of like a 'pin' i poked around a bit in 99SE and couldn't find a way to flag it yes manually inspecting the netlist would have caught it and truthfully isn't very hard to scan through even a big net list for this sort of thing and for the record ... at one time i may have been in the DXP-basher camp (some time ago) at this point since i have not used DXP much i don't think it would be objective or fair for me to bash i hope i have not lately presented such an attitude i would prefer to be categorized as simply a non-DXP user who is very reluctant to 'move on' based on what i saw during a few brief forays when 2004 ships i intend to give it another go Dennis Saputelli Tony Karavidas wrote: There are so many reasons voiced as to why to not move to DXP. Here is one reason TO MOVE to DXP. It now checks for that error. Tony -Original Message- From: Website Visitor [mailto:[EMAIL PROTECTED] Sent: Friday, December 19, 2003 6:29 AM To: proteledaforum Subject: [PEDA] Protel 99SE ERC This is a little hard to explain, but here goes... I am running the ERC on a schematic in Protel 99SE. It's interesting that there isn't a rule for determining whether a port has a mating counterpart. The Orcad ERC has a place where it will verify that all off-page connectors have mating counterparts. The only thing Protel 99 verifies is that the port is connected to something electrical. If you had a port that was supposed to match a port on another page, but you mispelled one of them, had a space in one of them, etc. you wouldn't know it by using the ERC. That seems really strange to me! Posted from Association web site by: Travis -- __ _ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power supply pins
are you referring to DXP ?
i don't see this prob in 99SE
the topic of power pins being hidden or not and separate parts for
containing power pins only has been hashed over quite a bit here
my 2 cents FWIW
keep the power pins right on logic BLOCK type symbols
with the rest of the pins
these days with so many different core voltages and possibly
separate isolated voltages of the same magnitude it's just plain
easier to control and see what is going on
rather than having to hunt around for a separate section and
then match up the designator, etc.
as to clutter it hardly matters to me since these chips are becoming
porcupines anyway
the messy exception i make to the above statement is for op amps
and maybe something like a QUAD NAND package which from this perspective
is about like an op amp
it's just so annoying to have the power pins jump around and have to
clear the
space, exp. for the byp caps
i think in this case the argument for a power section (aka 'part') makes
sense
BTW
in my practice i am finding that producing a nice looking
and pretty schematic to be less and less important
i.e., once the whole thing is debugged and in production
i seem to have ever decreasing need to look at the schematic
things are so fast moving that the bd is obsolete or junk
before you need to fix it (or so reliable it never comes up)
if it doesn't work on test get another assembler or
fix the process, there just isn't enough time or margin
to debug troubleshoot at the schematic level
remember when they used to repair carburetors?
now they just bolt a new one on
likewise i seem to be seeing less and less published
schematics which would remove another reason for making
a pretty schematic
obviously others will have different needs and perspectives
and i would like to make perfect looking and clear schematic as
much as the next designer but sometimes a bag of net
labels is enough to get the job done
Dennis Saputelli
Laurie Biddulph wrote:
Hello and thank you for your extensive response.
I do apologise for not getting back to you earlier but have been fairly busy.
I think it is generally good practise to always have EVERY pin exposed even power
supply pins but I do feel that putting the power pins off to one side is a neater
way than having as part of a main component symbol. The only problem I have found so
far, and I can't explain why, is that putting the power parts on to a separate page
resulted in Protel wanting to add a complete extra chip to the pcb when I did an
update.
I will study your other comments but am often amazed at how much extra work one has
to do sometimes to achieve a basic feature - not bad for ASU$9000!
Best Regards
Laurie Biddulph
http://www.elby-designs.com
- Original Message -
From: Abd ul-Rahman Lomax
To: Protel EDA Forum
Sent: Friday, December 12, 2003 5:07 AM
Subject: Re: [PEDA] Power supply pins
{this message bounced first time, outgoing mail server couldn't find
techservinc.com)
At 06:10 AM 12/10/2003, Laurie Biddulph wrote:
I hate having power supply pins as part of schematic component symbols
(especially opamps and logic gate chips). I prefer to create an additional
`component part' in the chip purely for the power supply pins. This makes
it easier to assign decoupling components to the chip as well as reduce
clutter in the main part of the schematic.
This is a very legitimate way of dealing with the problem, as is having the
power pins be part of the symbol. Hidden pins have restricted application,
some say that they should never be used, but that goes too far. If you have
a digital design with standard logic, hiding the power pins may be acceptable.
However, if a technician is going to have any difficulty later figuring out
which pin on a part is, for example, ground, it is better to be explicit.
Making symbols with power pins as a separate part of the symbol, while it
is a little more complex -- in creating the symbols -- is really the best
of both worlds. All the power parts can be placed on a page -- or part of a
schematic page -- which shows power nets and bypass cap allocations. This
leaves the rest of the schematic for signal flow and logic, and not having
to deal with power connections and bypass on those pages saves both time
and space, and results in a schematic that is easier to read. The only
negative I can think of is that in a split-supply design the power
assignments are not necessarily on the same page so an error in assignment
might be less obvious.
I consider the improvement in general readability to outweight that; it
just requires a little more caution, since, so far, there is no ERC for this.
(If component classes could be set up in schematic and assigned power
supply classes, ERC would be possible, where a component was assigned the
incorrect power supply, i.e., an analog part gets a digital
