It's a bug. I've been having the same problem for quite a while. I think
it may happen when the grid is changed from mils to mm and then back, but
I'm not sure.
- Original Message -
From: Sean James [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, March 12, 2002
Yes. In Design Rules go to Other tab and select Short Circuit Constraint.
When you pull it up, change both of the Objects Filtered boxes to say Net
Class rather than Whole Board and select All Nets. That will get rid of the
error. However, I would wait until the rest of the DRC is clean,
18-21.
-Original Message-
From: Dan Beaudoin [mailto:[EMAIL PROTECTED]]
Sent: Thursday, April 25, 2002 4:09 PM
To: Protel EDA Forum
Subject: Re: [PEDA] FBGA fan outs with no net name
Yes. In Design Rules go to Other tab and select Short
Circuit Constraint.
When you pull
