Yes.  In Design Rules go to Other tab and select Short Circuit Constraint.
When you pull it up, change both of the Objects Filtered boxes to say Net
Class rather than Whole Board and select All Nets.  That will get rid of the
error.  However, I would wait until the rest of the DRC is clean, because if
some net gets tied to a free primative (tooling hole or such) that has no
net, it will not report it as an error, and you could end up with an open on
the final project.  Of course, if everything on the board is a component, it
should not be a problem.

Dan B.

----- Original Message -----
From: "Michael Biggs" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Sent: Thursday, April 25, 2002 3:47 PM
Subject: [PEDA] FBGA fan outs with no net name


> I am working with a design that has a large FBGA and each pad on this part
> has a via fanout from it. Not all the pads are assigned a net name on this
> FBGA. The pins that are not used have no net name and therefore the pad
has
> no net name but I am still giving it a fan out with a small connection to
> it, incase I ever need to use it. The problem is the design rules flags
all
> these. My question is there any way around this or a design rule I can set
> up that will not show these no net name fanouts/connections as a
violation?
> Thanks for anyones comments,
> Michael Biggs

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