[PEDA] vias and multilayerboards

2001-11-30 Thread Matthias . Trebeck

Hi,

I have a problem with vias on a 6 layer board with a stack up like:

T
--P--
1   
--C--
2
--P--
3
--C--
4
--P--
B

Among others a via type, from layer 1 to layer 4, witch is depending on the layer 
stack, were used. But some of the vias were only connected on layer 1 and layer 3. Our 
board manufacturer had problems with these ones, because these vias appeared without 
the pad on layer 4 in the Gerber files. In other words, there was just a metallized 
hole in the board. During the etching process these vias were destroyed. All vias and 
tracks were manually placed and routed.
In DRC runs with Minimal Anular Ring Rule set 0 no violation were found. 

Does anyone out there know, how to fix this trouble or how to check the vias. Any help 
would be welcome.
Thanks in advance.  

  
Regards,

Matthias Trebeck

Infineon Technologies AG
Automotive Industrial
AI MC AC EMC

fon: +49 89 636 83244
fax: +49 89 234 723831

mailto:[EMAIL PROTECTED]

 VISIT US AT: http://www.infineon.com 

Mit freundlichen Grüßen

Matthias Trebeck

Infineon Technologies AG
Automotive Industrial
AI MC AC EMC

fon: +49 89 636 83244
fax: +49 89 234 723831

mailto:[EMAIL PROTECTED]

 VISIT US AT: http://www.infineon.com 
 

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Re: [PEDA] vias and multilayerboards

2001-11-30 Thread Abd ul-Rahman Lomax

At 10:47 AM 11/30/01 +0100, [EMAIL PROTECTED] wrote:
I have a problem with vias on a 6 layer board with a stack up like:

[ T p 1 c 2 p 3 c 4 p B ]

Among others a via type, from layer 1 to layer 4, witch is depending on 
the layer stack, were used. But some of the vias were only connected on 
layer 1 and layer 3. Our board manufacturer had problems with these ones, 
because these vias appeared without the pad on layer 4 in the Gerber 
files. In other words, there was just a metallized hole in the board. 
During the etching process these vias were destroyed.

This may be due to dead pad removal. If I had time, I'd investigate it now, 
I'd verify that dead pad removal (a gerber output option which removes 
unconnected pads on inner layers to improve manufacturability by decreasing 
the number of close clearances) will remove the outermost layer of a 
blind/buried via stack. I would not be at all surprised if it does.

Dead pad removal is a fairly old tool and may not have been modified to 
deal with blind/buried vias.

I'm a bit surprised that the removal of that pad would cause a problem with 
the vias, but it does make sense. I'm not up to speed with blind/buried via 
technology -- I have managed to avoid their use until very recently -- but 
I would imagine that the problem occurs when layer 4 is etched. Because the 
pad has been removed, there is no resist tent over the hole, and so the 
etchant could eat the hole wall down past layer 3, thus breaking the 
connection.

An obvious workaround is to turn off dead pad removal.

A possible manual workaround that would preserve the removal of 
non-functional pads would be to place a short length of track across the 
vias that one wants to retain, on the outer via layers; I suspect that this 
track need not even be visible outside the via. The track might even be 
zero length, I forget whether such track will plot (it should plot as if it 
were a flash). It is also possible that a pad would do it, i.e., a pad with 
0 hole on the layer in question. If so, placing such pads could be 
automated by selecting the vias with layer 4 as the stop layer, copying 
them to the clipboard, unselecting them, then pasting them over the 
originals, then using Tools/Convert/Convert Selected Vias to Free Pads. If 
that doesn't work there would be other techniques

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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