Bruce,
What you've described is a cap constructed 6 layer board. An
alternative (and from my understanding, the usual default) is
foil construction, in which the layers are stacked:
Cu
prepreg
Cu
core
Cu
prepreg
Cu
core
Cu
prepreg
Cu
The difference is only significant if you've got blind or buried
vias, since these can only be made through a core (e.g. between
layers 2 and 3 for the foil construction above).
Most important, though, is the fact that you don't have to live with
the board shop's "standard" stackup. In my opinion, every design should
explicitly specify the stackup, even if it's only to specify what would
have been made by default anyway. This way, if a board is refabbed
months or even years later, the stackup will be the same and you won't
hit sudden performance problems caused by a sudden absence of an
interplane capacitor (that perhaps was never there by design but which
just happened to be necessary for the board to work!).
Taking an example from one of my recent boards, I supplied a text file
with the PCB database (my board shop has Protel, so I let them generate
the gerbers they need) that looks like:
==================================================================
Printed Circuit Board Specification #001
========================================
PCB DATABASE:
The board was designed in Protel 99SE, SP5
GENERAL:
Six layers, cap construction, 0.5oz copper
1.1 mm finished thickness
Blind vias between layers 1-2 and 5-6
Min. finished hole size = 0.2mm
Min. annular ring = 0.175mm
Min. track width = 0.15mm (0.006")
Min. track separation = 0.14mm (0.0055")
Mi. solder mask expansion = 0.05mm
Min. router size = 1.0mm
MATERIAL:
Tetra/Multi functional FR-4: Tg >= 180C
STACKUP:
Top Overlay: White Legend Marking
Soldermask (Green LPI, sprayed)
SIG1
1 x 0.3mm core
SIG2
1 x 1080 prepreg
VDD
1 x 0.1mm core
GND
1 x 1080 prepreg
SIG3
1 x 0.3mm core
SIG4
Soldermask (Green LPI, sprayed)
Bottom Overlay: White Legend Marking
BOARD FINISH:
Silver
TESTING:
100% Flying probe tested
OTHER:
Fabricator's logo is not to be placed within the board
proper - within the assembly panel frame is OK
CAM MODIFICATIONS:
NO CHANGES are to be made in CAM (other than for etch
allowance) without EXPLICIT approval.
================================================================
Admittedly, this is a non-standard PCB (note the 0.1mm central
core that increases my interplane capacitance). But I'd still
provide a specification file even if the build was for a stock
standard 1.6mm PCB.
On inductance issues, from a course by Lee Ritchey:
"In general, vias are not visible to signals with edge rates
slower than 300psec"
While, from "High Speed Digital Design" (Howard W Johnson &
Martin Graham):
a via with length 0.063in (1.6mm) and diameter 0.016in (0.4mm)
has an inductance of 1.2nH
Assuming that we're making connection to a plane located
approximately in the centre of the board, the effective via
length may be taken to be approximately half the above value,
so L = 490pH (using the formula on p.259).
In comparison, (from Kemet data), a 100pF 0603 NPO ceramic
cap has a series inductance of 904pH (with a self resonant
frequency of 502MHz i.e. no good for 900MHz).
Placing multiple vias in parallel allows reduction in the
inductance getting to the plane, while nothing much can save
the discrete capacitor problem other than an increase in
BOM costs (more caps in parallel).
Cheers,
John Haddy
> -----Original Message-----
> From: TSListServer [mailto:[EMAIL PROTECTED]]On
> Behalf Of Bruce Walter
> Sent: Friday, 23 February 2001 12:20 PM
> To: Multiple recipients of list proteledausers
> Subject: [PROTEL EDA USERS]: power/ground planes
>
>
> I'm no expert, but here are my 2cents:
>
> I'm not sure, but I recall that for a six layer board, the center
> two layers
> are on either side of the 'core' material, which is the thickest
> part of the
> sandwich (~=30mil?). This is the most popular (and most
> appropriate) place
> for the power and ground plane, but causes the least inter-plane
> capacitance
> due to this thickness. There may not be much. (calculations anyone?)
>
> Moving to the next layer pair out is worse - more distance apart, with
> signal layers in-between. Moving the planes to one side or the other
> produces problems (bananas).
>
> The next step is an 8-layer board with two power-ground plane pairs - that
> way the pairs only have the thin laminate layer between greatly increasing
> the capacitance between the planes. At one time I think there was an
> enhanced dielectric laminate material available to increase this effect
> further.
>
> Regardless, I think that a feedthrough has much greater
> inductance that the
> lead inductance of an 0805 (or smaller) capacitor. When you get into
> extremely high frequencies, you just have to pay more attention to part
> selection - chose a part value that has self-inductance (self-resonance)
> appropriate for the intended use. (i.e. 27-100pF for 900MHz)
>
> Always select the path of least inductance. If the power and ground pins
> are adjacent, use the shortest traces to an APPROPRIATE cap, then sink
> feedthroughs to the power/ground plane (on the far side of the cap). I'm
> sure that the combined trace/lead inductance will be less than that of a
> feedthrough. Then, ABSOLUTELY let the parasitic effect of inter-plane
> capacitance provide additional (not replacement) decoupling.
>
> If the power and ground pins are far apart, then a feedthrough might have
> less inductance (as well as reducing routing problems) than running traces
> to a cap.
>
> There are no absolutes. Use the most appropriate method for each need!
>
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