On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
j...@tribudubois.net wrote:
Tested by booting a minimal linux system on the emulated plateform
Linux platform
Note: Qdev construction helper functions are removed with this patch.
So is the goal of the inline header movements to
On Mon, 07/06 10:27, Max Filippov wrote:
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng f...@redhat.com wrote:
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with TAP network and after the commit
0a2df857a703 Merge remote-tracking branch
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
j...@tribudubois.net wrote:
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
---
Changes since v1:
* Added a ds1338 I2C device for qtest purpose.
Changes since v2:
* none
Changes since v3:
* Rework GPL header
On Mon, Jul 06, 2015 at 09:46:14AM +0200, Paolo Bonzini wrote:
On 04/07/2015 23:19, Michael S. Tsirkin wrote:
The fact that address_space_write/_read actually does a byteswap if
host!=target endian should probably be documented.
FWIW, it's not if host != target endian. It's if memory
Hi.
If a base qcow2 image snapshot chain like this:
base.qcow2: [A] - [B] - [C]
[C] is the current image where guest read/write to,usually we create a new
image base on the base.qcow2 like this
qemu-img create -f qcow2 -o backing_file=/path/base.qcow2 new.qcow2
so the data of new.qcow2 is
On 2015-07-05 16:25, Serge Vakulenko wrote:
On Wed, Jul 1, 2015 at 3:02 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
@@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
*/
if (!kvm_enabled()) {
env-timer =
On 06/07/2015 10:33, Michael S. Tsirkin wrote:
Also, by luck, some values work the same whatever the endian-ness.
E.g. dma_memory_set fills the buffer with a given pattern, so
nothing changes if you byte-swap it.
Here's an example that's wrong: dp8393x. Typically it's accessing
memory for
On Mon, Jul 6, 2015 at 1:43 AM, Paolo Bonzini pbonz...@redhat.com wrote:
On 05/07/2015 23:08, Peter Crosthwaite wrote:
There was a complicated subtractive arithmetic for determining the
padding on the CPUTLBEntry structure. Simplify this with a union.
Signed-off-by: Peter Crosthwaite
From: Johannes Schlatow schla...@ida.ing.tu-bs.de
The interval interrupt is not set if the timer is in decrement mode.
This is because x =0 and x interval after leaving the while-loop.
Signed-off-by: Johannes Schlatow schla...@ida.ing.tu-bs.de
Message-id:
On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
On 6 July 2015 at 10:06, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
Why host endian and not device (in this case little) endian?
It's the endian of the originator
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current
translation
block. Implementation of the exceptions handling does not correctly
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
This patch introduces several helpers to pass return address
which points to the TB. Correct return address allows correct
restoring of the guest PC and icount. These functions should be used when
helpers embedded into TB invoke memory operations.
On 2015-07-06 11:25, Pavel Dovgalyuk wrote:
This patch introduces loop exit function, which also
restores guest CPU state according to the value of host
program counter.
Reviewed-by: Richard Henderson r...@twiddle.net
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Pavel
://github.com/OSLL/qemu-xtensa.git tags/20150706-xtensa
for you to fetch changes up to 1479073b7e849fa03e5892eea0e0b5dadde1a98a:
target-xtensa: fix gdb register map construction (2015-07-06 13:25:12 +0300)
Xtensa fixes:
- add 64-bit
On 06/07/2015 11:59, zhanghailiang wrote:
Besides, the follow is the cpus message got from host.
80FF72F5-FF6D-E411-A8C8-00821800:/home/fsp/hrg # virsh
qemu-monitor-command instance-000
* CPU #0: pc=0x7f64160c683d thread_id=68570
CPU #1: pc=0x810301f1 (halted)
On 04/07/2015 03:12, Alexey Kardashevskiy wrote:
One step back :) Whole dance is what here? There are:
1) del+set_size(0)
2) set_size(not zero)+add
Then no need for begin/commit. :)
I got a new problem here - set_size(0) + set_size(not 0) do not invoke
region_del/region_add which does
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as yield this CPU back to the top level loop so
another CPU has a chance to run. However it's rather confusing
that YIELD ends up calling HELPER(wfe), and
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
From: Dmitry Osipenko dig...@gmail.com
The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
On Mon, Jul 06, 2015 at 11:04:24AM +0100, Peter Maydell wrote:
On 6 July 2015 at 11:03, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
But address_space_rw() is just the memcpy bytes to the
target's memory operation -- if you have a
On 3 July 2015 at 09:22, Mark Cave-Ayland mark.cave-ayl...@ilande.co.uk wrote:
On 19/05/15 21:29, Richard Henderson wrote:
And do not issue an error_report in that case.
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/virtio/virtio-pci.c | 15 ++-
1 file changed, 10
Am 06.07.2015 um 11:44 schrieb Chun Yan Liu:
While testing with a 1GB VHD file created on win7, found that the VHD file
size reported on Windows is different from that is reported by qemu-img
info or within a Linux KVM guest.
Created a dynamic VHD file on win7, on Windows, it is reported 1024MB
On Mon, Jul 06, 2015 at 10:06:50AM +0800, Hong Bo Li wrote:
On 7/5/2015 2:25, Michael S. Tsirkin wrote:
On Fri, Jul 03, 2015 at 07:09:59PM +0800, Hong Bo Li wrote:
But I would like to note that pci device drivers require driver handshake
before device goes away.
IIUC s390 hotplug is
On Sun, 5 Jul 2015 23:14:56 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
This file implements a platform for Microchip PIC32MX7 microcontroller,
with three boards (machine types) supported:
pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-16 board
While testing with a 1GB VHD file created on win7, found that the VHD file
size reported on Windows is different from that is reported by qemu-img
info or within a Linux KVM guest.
Created a dynamic VHD file on win7, on Windows, it is reported 1024MB
(2097152 sectors). But with qemu-img info or
From: Sergey Fedorov serge.f...@gmail.com
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.
Signed-off-by: Sergey Fedorov serge.f...@gmail.com
Message-id:
repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150706
for you to fetch changes up to 257621a9566054472d1d55a819880d0f9da02bda:
arm_mptimer: Respect IT bit state (2015-07-06 10:26:35 +0100
On 2015/7/6 16:45, Paolo Bonzini wrote:
On 06/07/2015 09:54, zhanghailiang wrote:
From host, we found that QEMU vcpu1 thread and vcpu7 thread were not
consuming any cpu (Should be in idle state),
All of VCPUs' stacks in host is like bellow:
[a07089b5] kvm_vcpu_block+0x65/0xa0 [kvm]
The arm_gic_common reset function was missing reset code for
several of the GIC's state fields:
* bpr[]
* abpr[]
* priority1[]
* priority2[]
* sgi_pending[]
* irq_target[] (SMP configurations only)
These probably went unnoticed because most guests will either
never touch them, or will write
From: Dmitry Osipenko dig...@gmail.com
The running timer can't be stopped because timer control code just
doesn't handle disabling the timer. Fix it by deleting the timer if
the enable bit is cleared.
The timer won't start periodic ticking if a ONE-SHOT - PERIODIC mode
change happens after a
On 6 July 2015 at 11:03, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
But address_space_rw() is just the memcpy bytes to the
target's memory operation -- if you have a pile of bytes
then there are no endianness concerns. If you don't
On 07/06/2015 05:42 PM, Dr. David Alan Gilbert wrote:
* Wen Congyang (ghost...@gmail.com) wrote:
At 2015/7/3 23:30, Dr. David Alan Gilbert Wrote:
* Wen Congyang (we...@cn.fujitsu.com) wrote:
Block replication is a very important feature which is used for
continuous checkpoints(for example:
Works fine here,
Thanks !
- Mail original -
De: Fam Zheng f...@redhat.com
À: qemu-devel qemu-devel@nongnu.org
Cc: Kevin Wolf kw...@redhat.com, Jeff Cody jc...@redhat.com,
qemu-bl...@nongnu.org, mre...@redhat.com, js...@redhat.com, aderumier
aderum...@odiso.com, stefanha
On Mon, Jul 06, 2015 at 12:11:10PM +1000, Alexey Kardashevskiy wrote:
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO devices. As all TCE root regions
are mapped
On Mon, Jul 06, 2015 at 12:11:01PM +1000, Alexey Kardashevskiy wrote:
Currently TCE tables are created once at start and their size never
changes. We are going to change that by introducing a Dynamic DMA windows
support where DMA configuration may change during the guest execution.
This
On Mon, Jul 6, 2015 at 10:36 AM, Fam Zheng f...@redhat.com wrote:
On Mon, 07/06 10:27, Max Filippov wrote:
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng f...@redhat.com wrote:
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with TAP network and after the commit
0a2df857a703
On 04/07/2015 23:19, Michael S. Tsirkin wrote:
The fact that address_space_write/_read actually does a byteswap if
host!=target endian should probably be documented.
FWIW, it's not if host != target endian. It's if memory region
endianness != target endianness. See
This patch introduces several helpers to pass return address
which points to the TB. Correct return address allows correct
restoring of the guest PC and icount. These functions should be used when
helpers embedded into TB invoke memory operations.
Reviewed-by: Richard Henderson r...@twiddle.net
This patch fixes exception handling for other helper functions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/cc_helper.c |2 +-
target-i386/misc_helper.c | 10 +-
target-i386/ops_sse.h |2 +-
target-i386/svm_helper.c |4 ++--
4 files
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
We can know if VM in destination should go into COLO mode by refer to
the info that has been migrated from PVM.
Signed-off-by:
This patch fixes exception handling for memory helpers.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/mem_helper.c | 39 ++-
1 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/target-i386/mem_helper.c
On 2015-07-05 20:48, Serge Vakulenko wrote:
On Wed, Jul 1, 2015 at 6:37 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
target-mips/cpu.h| 2 ++
On 2015/7/6 16:29, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
We can know if VM in destination should go into COLO mode by refer to
the info that
On 06/07/2015 10:51, Alexander Graf wrote:
On 07/04/15 01:00, Laurent Vivier wrote:
On 04/07/2015 00:42, Paolo Bonzini wrote:
Loading the BIOS in the mac99 machine is interesting, because there is a
PROM in the middle of the BIOS region (from 16K to 32K). Before memory
region accesses
On 2015-07-05 23:14, Serge Vakulenko wrote:
Data definitions and function declarations for simulation
of pic32 microcontrollers.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/pic32_peripherals.h | 210
1 file changed,
On 6 July 2015 at 02:27, Dmitry Osipenko dig...@gmail.com wrote:
The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
If
On 07/02/2015 09:09 PM, Zavadovsky Yan wrote:
I tested this patch on my 4-cores cpu.
Debug and release builds both.
Win32 and Win64 binaries both. (I used old Fedora 17-18 with SJLJ mingw-w64
to crossbuild for Win64.)
With default Qemu BIOS and with myself-builded OVMF(also debug and
On 2015-07-05 20:31, Serge Vakulenko wrote:
On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
diff --git a/target-mips/cpu.h
On 2015-07-05 23:14, Serge Vakulenko wrote:
EIC is required for pic32 microcontroller.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c | 17 +++--
hw/mips/mips_int.c | 8 +++-
target-mips/cpu.h| 8 +++-
target-mips/helper.c |
On 2015/7/4 2:03, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
We can know if VM in destination should go into COLO mode by refer to
the info that has been migrated from PVM.
Signed-off-by: zhanghailiang zhang.zhanghaili...@huawei.com
Signed-off-by:
On Sun, 5 Jul 2015 21:18:11 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
On Wed, Jul 1, 2015 at 6:41 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/Makefile.objs
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng f...@redhat.com wrote:
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with TAP network and after the commit
0a2df857a703 Merge remote-tracking branch
'remotes/stefanha/tags/net-pull-request' into staging
I've noticed that activation
On Sun, 5 Jul 2015 21:27:04 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
On Wed, Jul 1, 2015 at 10:56 PM, Antony Pavlov antonynpav...@gmail.com
wrote:
On Tue, 30 Jun 2015 21:12:34 -0700
Serge Vakulenko serge.vakule...@gmail.com wrote:
Signed-off-by: Serge Vakulenko
- Le 6 Juil 15, à 8:40, Peter Crosthwaite peter.crosthwa...@xilinx.com a
écrit :
On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
j...@tribudubois.net wrote:
Move constructor to DeviceClass methods
* imx_serial_init
* imx_serial_realize
imx32_serial_properties is renamed to
On Sun, Jul 5, 2015 at 11:14 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
Data definitions and function declarations for simulation
of pic32 microcontrollers.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/pic32_peripherals.h | 210
On 2015-07-05 17:03, Serge Vakulenko wrote:
On Wed, Jul 1, 2015 at 3:11 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On 2015-06-30 21:12, Serge Vakulenko wrote:
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c | 18 +-
1 file changed, 5
On 2015-07-05 23:14, Serge Vakulenko wrote:
Currently the clock rate for all MIPS platforms is fixed at 100MHz.
Need to make it 40MHz for pic32mx7.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/cputimer.c| 15 +++
hw/mips/mips_fulong2e.c | 2
On 06/07/2015 09:54, zhanghailiang wrote:
From host, we found that QEMU vcpu1 thread and vcpu7 thread were not
consuming any cpu (Should be in idle state),
All of VCPUs' stacks in host is like bellow:
[a07089b5] kvm_vcpu_block+0x65/0xa0 [kvm]
[a071c7c1]
On 2015-07-05 20:05, Serge Vakulenko wrote:
} else {
/* A MIPS configured with compatibility or VInt (Vectored
Interrupts)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8e3204a..7e25998 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@
Many of the same comments I had before for IMX31 apply.
Liviu, CCd is actually working on a simlar problem for multiple SoCs
of the same family using a mostly the same definition. I think the
same applies to the i.MXxx families.
How I suggest this can one can be done to avoid the code dup is:
On Mon, 07/06 15:36, Fam Zheng wrote:
On Mon, 07/06 10:27, Max Filippov wrote:
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng f...@redhat.com wrote:
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with TAP network and after the commit
0a2df857a703 Merge remote-tracking
Hi,
Recently we encountered a problem in our project: 2 CPUs in VM are not brought
up normally after reboot.
Our host is using KVM kmod 3.6 and QEMU 2.1.
A SLES 11 sp3 VM configured with 8 vcpus,
cpu model is configured with 'host-passthrough'.
After VM's first time started up, everything
This patch fixes exception handling for FPU instructions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/fpu_helper.c | 146 +-
1 files changed, 80 insertions(+), 66 deletions(-)
diff --git a/target-i386/fpu_helper.c
This patch fixes exception handling for div instructions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/int_helper.c | 32
1 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-i386/int_helper.c
This patch removes useless PC updates before executing instructions.
PC can be recovered with correct exception handling by using TB return address.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/translate.c | 25 -
1 files changed, 0
This patch fixes exception handling in PowerPC.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling does not correctly
restore icount for the instruction which caused the
On Mon, Jul 6, 2015 at 1:01 AM, j...@tribudubois.net wrote:
- Le 6 Juil 15, à 8:40, Peter Crosthwaite peter.crosthwa...@xilinx.com
a écrit :
On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
j...@tribudubois.net wrote:
Move constructor to DeviceClass methods
* imx_serial_init
On 05/07/2015 23:08, Peter Crosthwaite wrote:
There was a complicated subtractive arithmetic for determining the
padding on the CPUTLBEntry structure. Simplify this with a union.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
include/exec/cpu-defs.h | 23
On Sun, Jul 5, 2015 at 11:15 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
Implement pic32 SPI peripheral interface.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/pic32_spi.c | 121
SPI controllers go in
On Mon, 07/06 10:45, Max Filippov wrote:
On Mon, Jul 6, 2015 at 10:36 AM, Fam Zheng f...@redhat.com wrote:
On Mon, 07/06 10:27, Max Filippov wrote:
On Mon, Jul 6, 2015 at 4:55 AM, Fam Zheng f...@redhat.com wrote:
On Sat, 07/04 10:47, Max Filippov wrote:
Hello,
I'm using QEMU with
On Sun, Jul 5, 2015 at 11:15 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
Implement access to SD card, attached to pic32 SPI port.
Can you use sd.c SD card definition?
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/pic32_sdcard.c | 428
On Sun, Jul 5, 2015 at 11:14 PM, Serge Vakulenko
serge.vakule...@gmail.com wrote:
Implement pic32 UART peripheral interface.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
hw/mips/pic32_uart.c | 228
+++
1 file changed, 228
This patch introduces loop exit function, which also
restores guest CPU state according to the value of host
program counter.
Reviewed-by: Richard Henderson r...@twiddle.net
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
cpu-exec.c
This patch introduces new versions of raise_exception functions
that receive TB return address as an argument.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/cpu.h |4
target-i386/excp_helper.c | 26 +++---
2 files changed, 23
QEMU targets ISAs contain instruction that can break the execution
flow with exceptions. When exception breaks the execution of the translation
block it may corrupt PC and icount values.
This set of patches fixes exception handling for MIPS, PowerPC, and i386
targets.
Incorrect execution for
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current translation
block. Implementation of the exceptions handling does not correctly
restore icount for the instruction which caused the
This patch fixes exception handling for seg_helper functions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/seg_helper.c | 646 +++---
1 files changed, 330 insertions(+), 316 deletions(-)
diff --git a/target-i386/seg_helper.c
On 2015-07-05 23:14, Serge Vakulenko wrote:
The LFSR algorithm, used for generating random TLB indexes for TLBWR
instruction,
was inclined to produce a degenerate sequence in some cases.
For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7,
On 07/04/15 01:00, Laurent Vivier wrote:
On 04/07/2015 00:42, Paolo Bonzini wrote:
Loading the BIOS in the mac99 machine is interesting, because there is a
PROM in the middle of the BIOS region (from 16K to 32K). Before memory
region accesses were clamped, when QEMU was asked to load a BIOS
On 07/03/15 09:18, David Gibson wrote:
On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
Current PPC code relies on -mem-path being used in order for
hugepage support to be detected. With the introduction of
MemoryBackendFile we can now handle this via:
-object
On 06/07/2015 10:58, Peter Crosthwaite wrote:
Which compiler version started implementing anonymous structs?
ISO C11 standardises it apparently. But various parts of the tree use
them now. target-arm/cpu.h, target-i386/kvm.c,
linux-user/syscall_defs.h and linux-headers/linux/kvm.h have
On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
On 06/07/2015 10:33, Michael S. Tsirkin wrote:
Also, by luck, some values work the same whatever the endian-ness.
E.g. dma_memory_set fills the buffer with a given pattern, so
nothing changes if you byte-swap it.
Here's
On 6 July 2015 at 10:06, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 10:46:31AM +0200, Paolo Bonzini wrote:
Why host endian and not device (in this case little) endian?
It's the endian of the originator of the transaction.
And emulated device code is all compiled in host
On 2015-07-05 23:14, Serge Vakulenko wrote:
Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation.
Signed-off-by: Serge Vakulenko serge.vakule...@gmail.com
---
target-mips/translate_init.c | 46
1 file changed, 46 insertions(+)
* Wen Congyang (ghost...@gmail.com) wrote:
At 2015/7/3 23:30, Dr. David Alan Gilbert Wrote:
* Wen Congyang (we...@cn.fujitsu.com) wrote:
Block replication is a very important feature which is used for
continuous checkpoints(for example: COLO).
Usage:
Please refer to
On Mon, Jul 06, 2015 at 10:53:47AM +0200, Alexander Graf wrote:
On 07/03/15 09:18, David Gibson wrote:
On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
Current PPC code relies on -mem-path being used in order for
hugepage support to be detected. With the introduction of
On Mon, Jul 06, 2015 at 12:10:56PM +1000, Alexey Kardashevskiy wrote:
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA
On Mon, Jul 06, 2015 at 12:11:08PM +1000, Alexey Kardashevskiy wrote:
On systems with guest visible IOMMU, adding a new memory region onto
PCI bus calls vfio_listener_region_add() for every DMA window. This
installs a notifier for IOMMU memory regions. The notifier is supposed
to be removed by
On Mon, Jul 06, 2015 at 12:11:06PM +1000, Alexey Kardashevskiy wrote:
sPAPR IOMMU is managing two copies of an TCE table:
1) a guest view of the table - this is what emulated devices use and
this is where H_GET_TCE reads from;
2) a hardware TCE table - only present if there is at least one
On 07/06/2015 09:06 PM, David Gibson wrote:
On Mon, Jul 06, 2015 at 12:11:10PM +1000, Alexey Kardashevskiy wrote:
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO
On 07/06/15 13:09, David Gibson wrote:
On Mon, Jul 06, 2015 at 10:53:47AM +0200, Alexander Graf wrote:
On 07/03/15 09:18, David Gibson wrote:
On Thu, Jul 02, 2015 at 03:46:14PM -0500, Michael Roth wrote:
Current PPC code relies on -mem-path being used in order for
hugepage support to be
On 6 July 2015 at 11:31, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 11:04:24AM +0100, Peter Maydell wrote:
On 6 July 2015 at 11:03, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 10:11:18AM +0100, Peter Maydell wrote:
But address_space_rw() is just
On 06/07/2015 13:54, Pavel Dovgaluk wrote:
Paolo,
Are there any chances for upstreaming these patches?
I'm sorry. It looks like no one really feels competent enough. What
about committing them at the beginning of 2.5? I'll do another round of
locking review before then.
Paolo
Pavel
On 07/06/2015 09:26 AM, Pavel Dovgalyuk wrote:
@@ -1117,33 +1131,33 @@ void helper_fxsave(CPUX86State *env, target_ulong ptr,
int data64)
for (i = 0; i 8; i++) {
fptag |= (env-fptags[i] i);
}
-cpu_stw_data(env, ptr, env-fpuc);
-cpu_stw_data(env, ptr + 2, fpus);
-
On 07/06/2015 09:26 AM, Pavel Dovgalyuk wrote:
This patch fixes exception handling for div instructions.
Signed-off-by: Pavel Dovgalyukpavel.dovga...@ispras.ru
---
target-i386/int_helper.c | 32
1 files changed, 16 insertions(+), 16 deletions(-)
On 07/06/2015 09:26 AM, Pavel Dovgalyuk wrote:
This patch fixes exception handling for seg_helper functions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
No, you don't want to discriminately change every call. That was my original
point about not needing to change seg_helper.c
On 2015-07-06 11:26, Pavel Dovgalyuk wrote:
This patch fixes exception handling for FPU instructions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
---
target-i386/fpu_helper.c | 146
+-
1 files changed, 80 insertions(+), 66
On Mon, Jul 06, 2015 at 02:04:12PM +0200, Paolo Bonzini wrote:
On 06/07/2015 13:50, Peter Maydell wrote:
On 6 July 2015 at 11:31, Michael S. Tsirkin m...@redhat.com wrote:
On Mon, Jul 06, 2015 at 11:04:24AM +0100, Peter Maydell wrote:
On 6 July 2015 at 11:03, Michael S. Tsirkin
From: Richard Henderson [mailto:rth7...@gmail.com] On Behalf Of Richard
Henderson
On 07/06/2015 09:26 AM, Pavel Dovgalyuk wrote:
This patch fixes exception handling for seg_helper functions.
Signed-off-by: Pavel Dovgalyuk pavel.dovga...@ispras.ru
No, you don't want to discriminately
From: Artyom Tarasenko atar4q...@gmail.com
Intel C Compiler version 15.0.3.187 Build 20150407 doesn't support
'|' function for non floating-point simd operands.
Define VEC_OR macro which uses _mm_or_si128 supported
both in icc and gcc on x86 platform.
Signed-off-by: Artyom Tarasenko
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