[Qemu-devel] [PULL 01/14] ppc: Fix xsrdpi, xvrdpi and xvrspi rounding

From: Anton Blanchard xsrdpi, xvrdpi and xvrspi use the round ties away method, not round nearest even. Signed-off-by: Anton Blanchard Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 6 +++--- 1 file changed, 3

[Qemu-devel] [PULL 06/14] vfio: Add host side DMA window capabilities

From: Alexey Kardashevskiy There are going to be multiple IOMMUs per a container. This moves the single host IOMMU parameter set to a list of VFIOHostDMAWindow. This should cause no behavioral change and will be used later by the SPAPR TCE IOMMU v2 which will also add a

[Qemu-devel] [PULL 00/14] ppc-for-2.7 queue 20160705 (v2)

The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa: Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3' into staging (2016-07-04 17:27:54 +0100) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.7

Re: [Qemu-devel] [PULL 00/14] ppc-for-2.7 queue 20160705

On Tue, Jul 05, 2016 at 03:10:34PM +1000, David Gibson wrote: > The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa: > > Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3' > into staging (2016-07-04 17:27:54 +0100) > > are av

[Qemu-devel] [PULL 04/14] spapr_iommu: Realloc guest visible TCE table when starting/stopping listening

From: Alexey Kardashevskiy The sPAPR TCE tables manage 2 copies when VFIO is using an IOMMU - a guest view of the table and a hardware TCE table. If there is no VFIO presense in the address space, then just the guest view is used, if this is the case, it is allocated in the KVM.

Re: [Qemu-devel] [RFC PATCH v0 1/5] cpu: Factor out cpu vmstate_[un]register into separate routines

On Tue, 5 Jul 2016 10:46:07 +0530 Bharata B Rao wrote: > On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote: > > On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote: > > > Consolidates cpu vmstate_[un]register calls into separate > > > routines. No

[Qemu-devel] [PATCH 2/3] Add KVM_CAP_PPC_HTM to linux/kvm.h

Signed-off-by: Sam Bobroff --- linux-headers/linux/kvm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index e60e21b..37cb3e8 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -866,6

[Qemu-devel] [PULL 08/14] spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)

From: Alexey Kardashevskiy This adds support for Dynamic DMA Windows (DDW) option defined by the SPAPR specification which allows to have additional DMA window(s) The "ddw" property is enabled by default on a PHB but for compatibility the pseries-2.6 machine and older disable

[Qemu-devel] [PATCH 3/3] spapr: Set ibm, pa-features HTM from KVM_CAP_PPC_HTM

Advertise HTM support in ibm, pa-features if KVM indicates support when queried via a new capability (KVM_CAP_PPC_HTM). If KVM returns false for the capability (which may indicate that the host kernel doesn't support the capability itself) attempt to determine availability using a fallback method

[Qemu-devel] [PULL 14/14] ppc/hash64: Fix support for LPCR:ISL

From: Benjamin Herrenschmidt We need to ignore the segment page size and essentially treat all pages as coming from a 4K segment. Signed-off-by: Benjamin Herrenschmidt [dwg: Adjusted for differences in my version of the prereq patches]

[Qemu-devel] [PULL 05/14] vfio: spapr: Add DMA memory preregistering (SPAPR IOMMU v2)

From: Alexey Kardashevskiy This makes use of the new "memory registering" feature. The idea is to provide the userspace ability to notify the host kernel about pages which are going to be used for DMA. Having this information, the host kernel can pin them all once per user

Re: [Qemu-devel] [PULL 00/14] ppc-for-2.7 queue 20160705

On Tue, 2016-07-05 at 15:32 +1000, David Gibson wrote: > On Tue, Jul 05, 2016 at 03:10:34PM +1000, David Gibson wrote: > > The following changes since commit > > 11659423113d2fbcf055085b5e8285d590addfaa: > > > >   Merge remote-tracking branch 'remotes/kraxel/tags/p

Re: [Qemu-devel] [PULL 14/14] ppc/hash64: Fix support for LPCR:ISL

On Tue, 2016-07-05 at 15:10 +1000, David Gibson wrote: > From: Benjamin Herrenschmidt > > We need to ignore the segment page size and essentially treat > all pages as coming from a 4K segment. NAK The arguments are still wrong to ppc_hash64_pteg_search >

[Qemu-devel] [PULL 10/14] target-ppc: Correct page size decoding in ppc_hash64_pteg_search()

The architecture specifies that when searching a PTEG for PTEs, entries with a page size encoding that's not valid for the current segment should be ignored, continuing the search. The current implementation does this with ppc_hash64_pte_size_decode() which is a very incomplete implementation of

[Qemu-devel] [PULL 07/14] vfio/spapr: Create DMA window dynamically (SPAPR IOMMU v2)

From: Alexey Kardashevskiy New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management. This adds ability to VFIO common code to dynamically allocate/remove DMA windows in the host kernel when new VFIO container is added/removed. This adds a helper to

[Qemu-devel] [PULL 13/14] ppc/hash64: Add proper real mode translation support

From: Benjamin Herrenschmidt This adds proper support for translating real mode addresses based on the combination of HV and LPCR bits. This handles HRMOR offset for hypervisor real mode, and both RMA and VRMA modes for guest real mode. PAPR mode adjusts the offsets

[Qemu-devel] [PULL 08/14] spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)

From: Alexey Kardashevskiy This adds support for Dynamic DMA Windows (DDW) option defined by the SPAPR specification which allows to have additional DMA window(s) The "ddw" property is enabled by default on a PHB but for compatibility the pseries-2.6 machine and older disable

[Qemu-devel] [PULL 09/14] ppc: simplify ppc_hash64_hpte_page_shift_noslb()

From: Cédric Le Goater The segment page shift parameter is never used. Let's remove it. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c| 4 ++-- target-ppc/mmu-hash64.c | 6 +-

Re: [Qemu-devel] [RFC PATCH v0 2/5] cpu: Optionally use arch_id instead of cpu_index in cpu vmstate_register()

On Tue, Jul 05, 2016 at 02:56:53PM +1000, David Gibson wrote: > On Tue, Jul 05, 2016 at 10:12:49AM +0530, Bharata B Rao wrote: > > Introduce CPUState.prefer_arch_id_over_cpu_index and > > MachineClass.prefer_arch_id_over_cpu_index that allow target > > machines to optionally switch to using

Re: [Qemu-devel] [PATCH v2 09/18] pc: delay setting number of boot CPUs to machine_done time

On Mon, 4 Jul 2016 19:42:07 +0300 "Michael S. Tsirkin" wrote: > On Mon, Jul 04, 2016 at 06:15:42PM +0200, Igor Mammedov wrote: > > On Mon, 4 Jul 2016 17:17:51 +0300 > > "Michael S. Tsirkin" wrote: > > > > > On Fri, Jun 24, 2016 at 06:05:57PM +0200, Igor

[Qemu-devel] [PULL 13/14] ppc/hash64: Add proper real mode translation support

From: Benjamin Herrenschmidt This adds proper support for translating real mode addresses based on the combination of HV and LPCR bits. This handles HRMOR offset for hypervisor real mode, and both RMA and VRMA modes for guest real mode. PAPR mode adjusts the offsets

[Qemu-devel] [PULL 03/14] ppc: simplify max_smt initialization in ppc_cpu_realizefn()

From: Greg Kurz kvmppc_smt_threads() returns 1 if KVM is not enabled. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- target-ppc/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Qemu-devel] [PATCH v10 02/26] x86-iommu: provide x86_iommu_get_default

On Mon, Jul 04, 2016 at 06:17:47PM +0300, Michael S. Tsirkin wrote: > On Tue, Jun 21, 2016 at 03:47:30PM +0800, Peter Xu wrote: > > Instead of searching the device tree every time, one static variable is > > declared for the default system x86 IOMMU device. Also, some VT-d > > macros are replaced

Re: [Qemu-devel] [PULL 14/14] ppc/hash64: Fix support for LPCR:ISL

On Tue, Jul 05, 2016 at 03:12:15PM +1000, Benjamin Herrenschmidt wrote: > On Tue, 2016-07-05 at 15:10 +1000, David Gibson wrote: > > From: Benjamin Herrenschmidt > > > > We need to ignore the segment page size and essentially treat > > all pages as coming from a 4K

Re: [Qemu-devel] [PATCH v10 02/26] x86-iommu: provide x86_iommu_get_default

On Mon, Jul 04, 2016 at 06:16:08PM +0300, Michael S. Tsirkin wrote: > On Tue, Jun 21, 2016 at 03:47:30PM +0800, Peter Xu wrote: > > Instead of searching the device tree every time, one static variable is > > declared for the default system x86 IOMMU device. Also, some VT-d > > macros are replaced

[Qemu-devel] [PATCH 0/3] Rework spapr: Better handling of ibm, pa-features TM bit

Hi David, Anton asked me to have a look at this, so here is an attempt at a re-implementation of his: "spapr: Better handling of ibm, pa-features TM bit" addressing your comments and those from Paul Mackerras. I've broken the patch into one to unconditionally disable the HTM bit in pa-features

[Qemu-devel] [PULL 14/14] ppc/hash64: Fix support for LPCR:ISL

From: Benjamin Herrenschmidt We need to ignore the segment page size and essentially treat all pages as coming from a 4K segment. Signed-off-by: Benjamin Herrenschmidt [dwg: Adjusted for differencesin my version of the prereq patches]

[Qemu-devel] [PATCH 1/3] spapr: Disable ibm, pa-features HTM bit

There are a few issues with our handling of the ibm,pa-features HTM bit: - We don't support transactional memory in PR KVM, so don't tell the OS that we do. - In full emulation we have a minimal implementation of HTM that always fails, so for performance reasons lets not tell the OS that we

Re: [Qemu-devel] [RFC PATCH v0 1/5] cpu: Factor out cpu vmstate_[un]register into separate routines

On Tue, Jul 05, 2016 at 02:56:13PM +1000, David Gibson wrote: > On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote: > > Consolidates cpu vmstate_[un]register calls into separate routines. > > No functionality change except that vmstate_unregister calls are > > now done under

[Qemu-devel] [PULL 12/14] target-ppc: Return page shift from PTEG search

ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it didn't previously do. This means we're now double decoding the page size because we check it int he fault path after ppc64_hash64_htab_lookup() returns. To avoid this duplication have ppc_hash64_pteg_search() and

[Qemu-devel] [PULL 00/14] ppc-for-2.7 queue 20160705

The following changes since commit 11659423113d2fbcf055085b5e8285d590addfaa: Merge remote-tracking branch 'remotes/kraxel/tags/pull-seabios-20160704-3' into staging (2016-07-04 17:27:54 +0100) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.7

[Qemu-devel] [PULL 07/14] vfio/spapr: Create DMA window dynamically (SPAPR IOMMU v2)

From: Alexey Kardashevskiy New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management. This adds ability to VFIO common code to dynamically allocate/remove DMA windows in the host kernel when new VFIO container is added/removed. This adds a helper to

[Qemu-devel] [PULL 06/14] vfio: Add host side DMA window capabilities

From: Alexey Kardashevskiy There are going to be multiple IOMMUs per a container. This moves the single host IOMMU parameter set to a list of VFIOHostDMAWindow. This should cause no behavioral change and will be used later by the SPAPR TCE IOMMU v2 which will also add a

[Qemu-devel] [PULL 10/14] target-ppc: Correct page size decoding in ppc_hash64_pteg_search()

The architecture specifies that when searching a PTEG for PTEs, entries with a page size encoding that's not valid for the current segment should be ignored, continuing the search. The current implementation does this with ppc_hash64_pte_size_decode() which is a very incomplete implementation of

[Qemu-devel] [PULL 09/14] ppc: simplify ppc_hash64_hpte_page_shift_noslb()

From: Cédric Le Goater The segment page shift parameter is never used. Let's remove it. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c| 4 ++-- target-ppc/mmu-hash64.c | 6 +-

[Qemu-devel] [PULL 11/14] target-ppc: Simplify HPTE matching

ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check all of these bits at once with a suitable ptem value. So, consolidate all the

[Qemu-devel] [PULL 01/14] ppc: Fix xsrdpi, xvrdpi and xvrspi rounding

From: Anton Blanchard xsrdpi, xvrdpi and xvrspi use the round ties away method, not round nearest even. Signed-off-by: Anton Blanchard Signed-off-by: David Gibson --- target-ppc/fpu_helper.c | 6 +++--- 1 file changed, 3

[Qemu-devel] [PULL 02/14] spapr: Ensure thread0 of CPU core is always realized first

From: Bharata B Rao During CPU core realization, we create all the thread objects and parent them to the core object in a loop. However, the realization of thread objects is done separately by walking the threads of a core using object_child_foreach(). With this,

[Qemu-devel] [PULL 03/14] ppc: simplify max_smt initialization in ppc_cpu_realizefn()

From: Greg Kurz kvmppc_smt_threads() returns 1 if KVM is not enabled. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- target-ppc/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL 04/14] spapr_iommu: Realloc guest visible TCE table when starting/stopping listening

From: Alexey Kardashevskiy The sPAPR TCE tables manage 2 copies when VFIO is using an IOMMU - a guest view of the table and a hardware TCE table. If there is no VFIO presense in the address space, then just the guest view is used, if this is the case, it is allocated in the KVM.

Re: [Qemu-devel] [RFC PATCH v0 2/5] cpu: Optionally use arch_id instead of cpu_index in cpu vmstate_register()

On Tue, Jul 05, 2016 at 10:12:49AM +0530, Bharata B Rao wrote: > Introduce CPUState.prefer_arch_id_over_cpu_index and > MachineClass.prefer_arch_id_over_cpu_index that allow target > machines to optionally switch to using arch_id instead of cpu_index > as instance_id in vmstate_register(). This

Re: [Qemu-devel] [RFC PATCH v0 1/5] cpu: Factor out cpu vmstate_[un]register into separate routines

On Tue, Jul 05, 2016 at 10:12:48AM +0530, Bharata B Rao wrote: > Consolidates cpu vmstate_[un]register calls into separate routines. > No functionality change except that vmstate_unregister calls are > now done under !CONFIG_USER_ONLY to match with vmstate_register calls. > > Signed-off-by:

Re: [Qemu-devel] [RFC PATCH v0 4/5] xics: Use arch_id instead of cpu_index in XICS code

On Tue, Jul 05, 2016 at 10:12:51AM +0530, Bharata B Rao wrote: > xics maintains an array of ICPState structures which is indexed > by cpu_index. Change this to index the ICPState array by arch_id > for pseries-2.7 onwards. This allows migration of guest to suceed > when there are holes in

Re: [Qemu-devel] [RFC PATCH v0 3/5] spapr: Implement CPUClass.get_arch_id() for PowerPC CPUs

On Tue, Jul 05, 2016 at 10:12:50AM +0530, Bharata B Rao wrote: > Signed-off-by: Bharata B Rao Reviewed-by: David Gibson Longer term we should probably change the field name to arch_id. In theory we could have something like this on a

Re: [Qemu-devel] [PATCH qemu v19 0/5] spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)

On Mon, Jul 04, 2016 at 01:33:02PM +1000, Alexey Kardashevskiy wrote: > Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus > where devices are allowed to do DMA. These ranges are called DMA windows. > By default, there is a single DMA window, 1 or 2GB big, mapped at zero >

[Qemu-devel] [RFC PATCH v0 4/5] xics: Use arch_id instead of cpu_index in XICS code

xics maintains an array of ICPState structures which is indexed by cpu_index. Change this to index the ICPState array by arch_id for pseries-2.7 onwards. This allows migration of guest to suceed when there are holes in cpu_index range due to CPU hot removal. Signed-off-by: Bharata B Rao

[Qemu-devel] [RFC PATCH v0 3/5] spapr: Implement CPUClass.get_arch_id() for PowerPC CPUs

Signed-off-by: Bharata B Rao --- target-ppc/translate_init.c | 8 1 file changed, 8 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 8f257fb..b810624 100644 --- a/target-ppc/translate_init.c +++

[Qemu-devel] [RFC PATCH v0 2/5] cpu: Optionally use arch_id instead of cpu_index in cpu vmstate_register()

Introduce CPUState.prefer_arch_id_over_cpu_index and MachineClass.prefer_arch_id_over_cpu_index that allow target machines to optionally switch to using arch_id instead of cpu_index as instance_id in vmstate_register(). This will help allow successful migration in cases where holes are introduced

[Qemu-devel] [RFC PATCH v0 5/5] spapr: Prefer arch_id over cpu_index

Starting from pseries-2.7, prefer the use of arch_id (cpu_dt_id) over cpu_index for cpu vmstate registration and in XICS code. This allows migration to work when CPU cores are not necessarily unplugged in LIFO order. Signed-off-by: Bharata B Rao --- hw/ppc/spapr.c

[Qemu-devel] [RFC PATCH v0 0/5] sPAPR: Fix migration when CPUs are removed in random order

device_add/del based CPU hotplug and unplug support is upstream for sPAPR PowerPC and is under development for x86. Both of these will support CPU device removal in random order (and not necessarily in LIFO order). Random order removal will result in holes in cpu_index range which causes migration

[Qemu-devel] [RFC PATCH v0 1/5] cpu: Factor out cpu vmstate_[un]register into separate routines

Consolidates cpu vmstate_[un]register calls into separate routines. No functionality change except that vmstate_unregister calls are now done under !CONFIG_USER_ONLY to match with vmstate_register calls. Signed-off-by: Bharata B Rao --- exec.c | 47

Re: [Qemu-devel] [PATCH v10 27/26] intel_iommu: disallow kernel-irqchip=on with IR

On Mon, Jul 04, 2016 at 06:39:00PM +0300, Michael S. Tsirkin wrote: > On Fri, Jun 24, 2016 at 05:20:22PM +0800, Peter Xu wrote: > > On Fri, Jun 24, 2016 at 03:10:21PM +0800, Peter Xu wrote: > > > When user specify "kernel-irqchip=on", throw error and then quit. > > > > > > Signed-off-by: Peter Xu

Re: [Qemu-devel] [PATCH 0/3] Fixes and cleanups to HPTE lookup and page size decoding

On Tue, 2016-07-05 at 12:33 +1000, David Gibson wrote: > Here are 3 fixes and cleanups to the path to look up hashed PTEs and > decode their page size.  This series is functionally equivalent to > BenH's earlier posted "ppc/hash64: Various fixes in PTE search in the > hash" but split up for

[Qemu-devel] [PATCH 1/3] target-ppc: Correct page size decoding in ppc_hash64_pteg_search()

The architecture specifies that when searching a PTEG for PTEs, entries with a page size encoding that's not valid for the current segment should be ignored, continuing the search. The current implementation does this with ppc_hash64_pte_size_decode() which is a very incomplete implementation of

[Qemu-devel] [PATCH 2/3] target-ppc: Simplify HPTE matching

ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check all of these bits at once with a suitable ptem value. So, consolidate all the

[Qemu-devel] [PATCH 0/3] Fixes and cleanups to HPTE lookup and page size decoding

Here are 3 fixes and cleanups to the path to look up hashed PTEs and decode their page size. This series is functionally equivalent to BenH's earlier posted "ppc/hash64: Various fixes in PTE search in the hash" but split up for clarity and with some unnnecessary renames removed. David Gibson

[Qemu-devel] [PATCH 3/3] target-ppc: Return page shift from PTEG search

ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it didn't previously do. This means we're now double decoding the page size because we check it int he fault path after ppc64_hash64_htab_lookup() returns. To avoid this duplication have ppc_hash64_pteg_search() and

[Qemu-devel] [PATCH] hw/block/m25p80: fix resource leak

From: Shannon Zhao These two are spot by Coverity 1357232 and 1357233. Signed-off-by: Shannon Zhao --- hw/block/m25p80.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index

Re: [Qemu-devel] Regression: block: Add .bdrv_co_pwrite_zeroes()

On 07/04/2016 07:49 AM, Peter Lieven wrote: > Hi, > > the above commit: > > commit d05aa8bb4a8b6aa9a915ec5074fb12ae632d2323 > Author: Eric Blake > Date: Wed Jun 1 15:10:03 2016 -0600 > > block: Add .bdrv_co_pwrite_zeroes() > > introduces a regression (at least for

Re: [Qemu-devel] [RFC 00/13] Live memory snapshot based on userfaultfd

On 2016/7/4 20:22, Baptiste Reynal wrote: On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang wrote: For now, we still didn't support live memory snapshot, we have discussed a scheme which based on userfaultfd long time ago. You can find the discussion by the follow

Re: [Qemu-devel] [PATCH v8 7/7] trace: Add QAPI/QMP interfaces to query and control per-vCPU tracing state

On 07/04/2016 03:41 AM, Lluís Vilanova wrote: > Signed-off-by: Lluís Vilanova > Reviewed-by: Stefan Hajnoczi > --- > hmp-commands-info.hx |6 +- > hmp-commands.hx |7 +- > monitor.c| 17 +- > qapi/trace.json | 32

[Qemu-devel] Odp.: Odp.: [PATCH 2/7] m25p80: add mx25l25635f chip

W dniu 04.07.2016 o 17:48, Cédric Le Goater pisze: > On 07/04/2016 05:23 PM, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote: >> >> >> W dniu 04.07.2016 o 15:41, Cédric Le Goater pisze: >>> On 07/04/2016 02:57 PM, Krzeminski, Marcin (Nokia - PL/Wroclaw) wrote: > -Original

Re: [Qemu-devel] [PATCH v8 11/12] vfio: register aer resume notification handler for aer resume

ping On 2016/7/3 12:00, Zhou Jie wrote: Hi Alex, On 2016/6/30 9:45, Zhou Jie wrote: Hi Alex, On 2016/6/30 2:22, Alex Williamson wrote: On Wed, 29 Jun 2016 16:54:05 +0800 Zhou Jie wrote: Hi Alex, And yet we have struct pci_dev.broken_intx_masking and we test

Re: [Qemu-devel] failed kpartx on qemu-aarch64-static

Hi Peter, On Tuesday, July 5, 2016, Peter Maydell wrote: > On 2 July 2016 at 19:23, Peter Maydell > wrote: > > On 2 July 2016 at 17:25, Chanho Park > > wrote: > >> I've got a kpartx crash frin

Re: [Qemu-devel] [PATCH 0/2] linux-user: fix kpartx ioctl problems

Hi Peter, On Tuesday, July 5, 2016, Peter Maydell wrote: > This patchset fixes a couple of ioctl bugs which were > causing problems with running kpartx: > (1) add the missing ioctls for the loop-control device > (2) fix the BLKSSZGET ioctl not to trash memory on >

Re: [Qemu-devel] [PATCH v4 3/5] numa: reduce code duplication by adding helper numa_get_node_for_cpu()

On 2016/7/4 23:51, Igor Mammedov wrote: > Replace repeated pattern > > for (i = 0; i < nb_numa_nodes; i++) { > if (test_bit(idx, numa_info[i].node_cpu)) { >... >break; > > with a helper function to lookup numa node index for cpu. > > Suggested-by: Michael

Re: [Qemu-devel] [PATCH v2 2/6] x86: Mask mtrr mask based on CPU physical address limits

On Mon, Jul 04, 2016 at 05:05:36PM -0300, Eduardo Habkost wrote: > On Mon, Jul 04, 2016 at 11:02:00PM +0300, Michael S. Tsirkin wrote: > > On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) > > wrote: > > > From: "Dr. David Alan Gilbert" > > > > > > The

Re: [Qemu-devel] [PATCH 06/24] vhost-user: check vhost_user_write() return value

On Tue, Jul 05, 2016 at 12:01:49AM +0200, Marc-André Lureau wrote: > On Mon, Jul 4, 2016 at 5:46 PM, Michael S. Tsirkin wrote: > > Let's just work on handling it. If we need debug messages to help us > > reach that goal fine. But I don't see many reasons to propagate > > return

Re: [Qemu-devel] [PATCH 08/24] vhost-user: return a read error

On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote: > Hi > > On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote: > > Why does vhost_user_set_log_base need to return error? > > If backend is not there to handle this message, > > then it is not changing memory

Re: [Qemu-devel] [PATCH 1/2] tcg: Ensure safe tb_jmp_cache lookup out of 'tb_lock'

On Sat, Jul 02, 2016 at 08:09:35 +0100, Alex Bennée wrote: > > Emilio G. Cota writes: > > > On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote: > >> From: Sergey Fedorov > > (snip) > >> @@ -333,7 +338,7 @@ static inline TranslationBlock

Re: [Qemu-devel] [PATCH 1/2] tcg: Ensure safe tb_jmp_cache lookup out of 'tb_lock'

On Fri, Jul 01, 2016 at 17:32:01 -0700, Richard Henderson wrote: > On 07/01/2016 05:17 PM, Emilio G. Cota wrote: > >On Fri, Jul 01, 2016 at 17:16:09 +0100, Alex Bennée wrote: > >>From: Sergey Fedorov > >(snip) > >>@@ -333,7 +338,7 @@ static inline TranslationBlock

Re: [Qemu-devel] [PATCH 2/2] cpu-exec: remove tb_lock from the hot-path

On Mon, Jul 04, 2016 at 12:45:52 +0100, Alex Bennée wrote: > > Emilio G. Cota writes: > > > On Fri, Jul 01, 2016 at 17:16:10 +0100, Alex Bennée wrote: > >> Lock contention in the hot path of moving between existing patched > >> TranslationBlocks is the main drag in multithreaded

Re: [Qemu-devel] [PATCH 06/24] vhost-user: check vhost_user_write() return value

On Mon, Jul 4, 2016 at 5:46 PM, Michael S. Tsirkin wrote: > Let's just work on handling it. If we need debug messages to help us > reach that goal fine. But I don't see many reasons to propagate > return codes back and forth if caller just prints and ignores it. > Print it where

Re: [Qemu-devel] [PATCH 08/24] vhost-user: return a read error

Hi On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote: > Why does vhost_user_set_log_base need to return error? > If backend is not there to handle this message, > then it is not changing memory so it's ok to ignore the error. How do you know it's not changing the memory?

[Qemu-devel] [Bug 1593756] Re: qemu-ga won't start on Windows 8.1 guest

It turned out that this is not a bug but instead I overlooked to add a channel for qemu-ga via virt-manager. Don't know how it got lost on the working machine, but nvm, it works now. Anyone feel free to close this (didn't find an option to do so). ** Changed in: qemu Status: New =>

Re: [Qemu-devel] [PATCH v2 6/6] x86: Add sanity checks on phys_bits

On Mon, Jul 04, 2016 at 08:16:09PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Add some sanity checks on the phys-bits setting now that > the user can set it. >a) That it's in a sane range (52..32) >b) Warn if it mismatches the

[Qemu-devel] [PATCH 3/3] add serial console support

Signed-off-by: Gerd Hoffmann --- Makefile | 2 +- src/clock.c | 1 + src/misc.c | 2 + src/optionroms.c | 4 +- src/sercon.c | 545 +++ src/util.h | 3 + 6 files changed, 555

[Qemu-devel] [PATCH 1/3] std: add cp437 to unicode map

Signed-off-by: Gerd Hoffmann --- src/std/cp437.h | 258 1 file changed, 258 insertions(+) create mode 100644 src/std/cp437.h diff --git a/src/std/cp437.h b/src/std/cp437.h new file mode 100644 index 000..fafb864

[Qemu-devel] [PATCH 2/3] kbd: make enqueue_key public, add ascii_to_keycode

Signed-off-by: Gerd Hoffmann --- src/kbd.c | 17 - src/util.h | 2 ++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/kbd.c b/src/kbd.c index 61d9df0..7c43129 100644 --- a/src/kbd.c +++ b/src/kbd.c @@ -51,7 +51,7 @@ kbd_init(void)

[Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

Hi, Next round of patches. Changes: * Moved it all to a new sercon.c file. * Code maps cp437 to utf8 now, giving a much nicer display. Compare "Use the ↑ and ↓ keys to change the selection." (this series) with "Use the ^ and v keys to change the selection." (sgabios) ;-) *

Re: [Qemu-devel] [V12 4/4] hw/i386: AMD IOMMU IVRS table

On Wed, Jun 15, 2016 at 03:21:52PM +0300, David Kiarie wrote: > Add IVRS table for AMD IOMMU. Generate IVRS or DMAR > depending on emulated IOMMU. > > Signed-off-by: David Kiarie > --- > hw/acpi/aml-build.c | 2 +- > hw/i386/acpi-build.c| 95 >

Re: [Qemu-devel] [PATCH v2 4/6] x86: Set physical address bits based on host

On Mon, Jul 04, 2016 at 08:16:07PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > A special case based on the previous phys-bits property; if it's > the magic value 0 then use the hosts capabilities. > > This becomes the default on new

Re: [Qemu-devel] [RFC PATCH 1/2] serial console, output

Hi, > > void sercon_putchar(char *ptr) > > { > > char c = GET_GLOBAL(ptr[0]); > > [ ... ] > > > > ... work? > > Yes. See output.c:puts_cs() as an example. It only works if it's a > constant string (as opposed to a string built on the stack). After cleaning up the code only three

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > QEMU sets the guests physical address bits to 40; this is wrong > on most hardware, and can be detected by the guest. > It also stops you using really huge

Re: [Qemu-devel] [PATCH v2 3/6] x86: fill high bits of mtrr mask

On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote: [...] > @@ -2084,6 +2085,27 @@ static int kvm_get_msrs(X86CPU *cpu) > } > > assert(ret == cpu->kvm_msr_buf->nmsrs); > +/* > + * MTRR masks: Each mask consists of 5 parts > + * a 10..0: must be

Re: [Qemu-devel] [RFC PATCH 1/2] serial console, output

Hi, > I found what I was looking for though - it was in the sgabios > design.txt file instead of the revision history: > So, if I read the above correctly, it was lilo that inspired the > "feature". Anyway, something to keep in mind. Oh. lilo. Interesting. I didn't expect

Re: [Qemu-devel] [PATCH v2 3/6] x86: fill high bits of mtrr mask

On Mon, Jul 04, 2016 at 11:03:59PM +0300, Michael S. Tsirkin wrote: > On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > Fill the bits between 51..number-of-physical-address-bits in the > > MTRR_PHYSMASKn

Re: [Qemu-devel] [RFC PATCH 1/2] serial console, output

Hi, > > Unfortunately, the screen can be larger than 80x25. > > It can with SVGA BIOS, but Gerd here only supports mode 3, doesn't he? Current code yes, but that doesn't imply it'll stay that way forever. Supporting other sizes is just a matter of making sercon_1000() recognizing the mode

Re: [Qemu-devel] [PATCH v2 2/6] x86: Mask mtrr mask based on CPU physical address limits

On Mon, Jul 04, 2016 at 11:02:00PM +0300, Michael S. Tsirkin wrote: > On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > The CPU GPs if we try and set a bit in a variable MTRR mask above > > the limit of

Re: [Qemu-devel] [PATCH v2 3/6] x86: fill high bits of mtrr mask

On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Fill the bits between 51..number-of-physical-address-bits in the > MTRR_PHYSMASKn variable range mtrr masks so that they're consistent > in the migration stream

Re: [Qemu-devel] [PATCH v2 2/6] x86: Mask mtrr mask based on CPU physical address limits

On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > The CPU GPs if we try and set a bit in a variable MTRR mask above > the limit of physical address bits on the host. We hit this > when loading a migration from

Re: [Qemu-devel] [SeaBIOS] [RFC PATCH 2/2] serial console, input

Hi, > Does the original code flush the multi-byte sequence on a timeout? I > suspect it is important that one can hit ESC without having to type > another key. Also, I'd prefer to avoid backwards gotos if possible. Yes, sort of. If it didn't match an escape sequence and hasn't seen

Re: [Qemu-devel] [PATCH v2 2/6] x86: Mask mtrr mask based on CPU physical address limits

On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > The CPU GPs if we try and set a bit in a variable MTRR mask above > the limit of physical address bits on the host. We hit this > when loading a migration from

Re: [Qemu-devel] [PATCH v2 0/2]vhost-user: Extend protocol to seek response for any command.

On Mon, Jul 04, 2016 at 04:50:04PM +, Prerna Saxena wrote: > Hi Michael, > Thank you for taking a look. > > > > > > On 04/07/16 5:29 pm, "Michael S. Tsirkin" wrote: > > >On Fri, Jul 01, 2016 at 02:46:20AM -0700, Prerna Saxena wrote: > >> From: Prerna Saxena

Re: [Qemu-devel] [PATCH] char: do not use atexit cleanup handler

Hi, > > > What about graphics threads ? In particular I'd be thinking of spice > > > which uses threads and chardevs. > > > > I think it should be quiesced after pause_all_vcpus returns. Marc-André > > should know, but it's better to check with Gerd. > > In theory, spice_server_vm_stop()

Re: [Qemu-devel] Bug in virtio_net_load

Hey, So over the weekend we did a bunch of migrations with a bunch of different guest OSes and such and it all worked fine, so I would say the patch is working properly :) Regards, Robin Geuze On 7/1/2016 10:48, Cornelia Huck wrote: On Thu, 30 Jun 2016 20:23:08 +0300 "Michael S. Tsirkin"

Re: [Qemu-devel] [PATCH v2 1/6] x86: Allow physical address bits to be set

On Mon, Jul 04, 2016 at 08:16:04PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Currently QEMU sets the x86 number of physical address bits to the > magic number 40. This is only correct on some small AMD systems; > Intel systems tend to

[Qemu-devel] [PATCH v2 5/6] x86: fix up 32 bit phys_bits case

From: "Dr. David Alan Gilbert" On 32 bit systems fix up phys_bits to be consistent with what we tell the guest; don't ever bother with using the phys_bits property. Signed-off-by: Dr. David Alan Gilbert --- target-i386/cpu.c | 15 ++- 1

Re: [Qemu-devel] [PATCH v2 07/18] pc: set APIC ID based on socket/core/thread ids if it's not been set yet

On Fri, Jun 24, 2016 at 06:05:55PM +0200, Igor Mammedov wrote: > CPU added with device_add help won't have APIC ID set, > so set it according to socket/core/thread ids provided > with device_add command. > > Signed-off-by: Igor Mammedov > --- > v2: > - add validity checks

[Qemu-devel] [PATCH v2 4/6] x86: Set physical address bits based on host

From: "Dr. David Alan Gilbert" A special case based on the previous phys-bits property; if it's the magic value 0 then use the hosts capabilities. This becomes the default on new machine types. Signed-off-by: Dr. David Alan Gilbert ---

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