[Qemu-devel] [PATCH] block: all I/O should be completed before removing throttle timers.

From: Zhengui In blk_remove_bs, all I/O should be completed before removing throttle timers. If there has inflight I/O, removing throttle timers here will cause the inflight I/O never return. This patch add bdrv_drained_begin before throttle_timers_detach_aio_context to let

[Qemu-devel] Industrial Park Nanshan District

ZTE Corporation Hi-tech Road South,

[Qemu-devel] 答复: wurb test zt

wrong prefix 主 题 ：[Qemu-devel] wurb test zt It's a test mail for testing relative between topic and reply.

Re: [Qemu-devel] wurb test zt

reply with right prefix 主 题 ：[Qemu-devel] wurb test zt It's a test mail for testing relative between topic and reply.

[Qemu-devel] zmail test

[Qemu-devel] [Bug 1054180] Re: DNS activity in slirp (user networking) mode quickly depletes file descriptors and crashes qemu

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1054180 Title: DNS

Re: [Qemu-devel] [Qemu-trivial] [PATCH] Update Paul Burton's email address

On 10/20/2017 11:00 PM, no-re...@patchew.org wrote: > > This series failed build test on s390x host. Please find the details below. > > Message-id: 20171020232114.5475-1-paul.bur...@mips.com > Subject: [Qemu-devel] [PATCH] Update Paul Burton's email address [...] > === OUTPUT BEGIN === [...] >

Re: [Qemu-devel] [PATCH v6 00/50] tcg tb_lock removal

On Fri, Oct 20, 2017 at 09:10:38 +0200, Paolo Bonzini wrote: > >> 2) in tb_for_each_tagged_safe, could the "prev" argument instead be > >> "next", like > > > > Is this just to make them closer to the macros in queue.h? > > > > In this case tracking *prev in the loop (rather than next) is > >

[Qemu-devel] [PATCH] Update Paul Burton's email address

From: Paul Burton Update my email address from paul.bur...@imgtec.com to paul.bur...@mips.com, since MIPS will soon no longer be a part of Imagination Technologies & as such the @imgtec.com address will soon cease to function. A mapping is added in .mailmap such that git

[Qemu-devel] [PATCH v7 48/52] translate-all: use qemu_protect_rwx/none helpers

From: "Emilio G. Cota" The helpers require the address and size to be page-aligned, so do that before calling them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v7 47/52] osdep: introduce qemu_mprotect_rwx/none

From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 2 ++ util/osdep.c | 41

[Qemu-devel] [PATCH v7 46/52] tcg: allocate optimizer temps with tcg_malloc

From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. While at it, also allocate temps_used directly as a bitmap of the required size, instead of using a bitmap of TCG_MAX_TEMPS via TCGTempSet. Performance-wise we lose about 1.12% in a translation-heavy

Re: [Qemu-devel] [libfdt][PATCH v2] implement strnlen for systems that need it

On 10/20/2017 10:55 AM, John Arbuckle wrote: > +static inline size_t strnlen(const char *string, size_t max_count) > +{ > +size_t count; > +for (count = 0; count < max_count; count++) { > +if (string[count] == '\0') { > +break; > +} > +} > +return count;

[Qemu-devel] [PATCH v7 37/52] tcg: Remove CF_IGNORE_ICOUNT

Now that we have curr_cflags, we can include CF_USE_ICOUNT early and then remove it as necessary. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 17 + accel/tcg/cpu-exec.c | 16 +--- accel/tcg/translate-all.c | 3

[Qemu-devel] [PATCH v7 51/52] tcg: Initialize cpu_env generically

This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created

[Qemu-devel] [PATCH v7 36/52] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK

These flags are used by target/*/translate.c, and affect code generation. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index

[Qemu-devel] [PATCH v7 50/52] tcg: enable multiple TCG contexts in softmmu

From: "Emilio G. Cota" This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that

[Qemu-devel] [PATCH v7 34/52] tcg: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a field to TCGContext, storing there a copy of tb->cflags. Most architectures have <= 32

[Qemu-devel] [PATCH v7 42/52] tcg: define tcg_init_ctx and make tcg_ctx a pointer

From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext

[Qemu-devel] [PATCH v7 32/52] target/sh4: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 43/52] gen-icount: fold exitreq_label into TCGContext

From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v7 49/52] tcg: introduce regions to split code_gen_buffer

From: "Emilio G. Cota" This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here

[Qemu-devel] [PATCH v7 30/52] target/m68k: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 45/52] tcg: distribute profiling counters across TCGContext's

From: "Emilio G. Cota" This is groundwork for supporting multiple TCG contexts. To avoid scalability issues when profiling info is enabled, this patch makes the profiling info counters distributed via the following changes: 1) Consolidate profile info into its own struct,

[Qemu-devel] [PATCH v7 38/52] translate-all: use a binary search tree to track TBs in TBContext

From: "Emilio G. Cota" This is a prerequisite for supporting multiple TCG contexts, since we will have threads generating code in separate regions of code_gen_buffer. For this we need a new field (.size) in struct tb_tc to keep track of the size of the translated code. This

[Qemu-devel] [PATCH v7 52/52] translate-all: exit from tb_phys_invalidate if qht_remove fails

From: "Emilio G. Cota" Two or more threads might race while invalidating the same TB. We currently do not check for this at all despite taking tb_lock, which means we would wrongly invalidate the same TB more than once. This bug has actually been hit by users: I recently saw a

[Qemu-devel] [PATCH v7 40/52] translate-all: report correct avg host TB size

From: "Emilio G. Cota" Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the corresponding translated code") we are not fully utilizing code_gen_buffer for translated code, and therefore are incorrectly reporting the amount of translated code as well as the average host TB

[Qemu-devel] [PATCH v7 27/52] target/arm: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 39/52] exec-all: rename tb_free to tb_remove

From: "Emilio G. Cota" We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Suggested-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota

[Qemu-devel] [PATCH v7 24/52] tcg: Add CPUState cflags_next_tb

We were generating code during tb_invalidate_phys_page_range, check_watchpoint, cpu_io_recompile, and (seemingly) discarding the TB, assuming that it would magically be picked up during the next iteration through the cpu_exec loop. Instead, record the desired cflags in CPUState so that we request

[Qemu-devel] [PATCH v7 44/52] tcg: introduce **tcg_ctxs to keep track of all TCGContext's

From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Note that having n_tcg_ctxs is unnecessary. However, it is convenient to have it, since it will simplify iterating over the array: we'll have just a for loop instead of having to iterate over a

[Qemu-devel] [PATCH v7 26/52] tcg: convert tb->cflags reads to tb_cflags(tb)

From: "Emilio G. Cota" Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion.

[Qemu-devel] [PATCH v7 33/52] target/sparc: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 19/52] tcg: Remove TCGV_EQUAL*

When we used structures for TCGv_*, we needed a macro in order to perform a comparison. Now that we use pointers, this is just clutter. Signed-off-by: Richard Henderson --- tcg/tcg-op.h| 6 ++ tcg/tcg.h | 4

[Qemu-devel] [PATCH v7 41/52] tcg: take tb_ctx out of TCGContext

From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v7 28/52] target/hppa: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 31/52] target/s390x: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 35/52] cpu-exec: lookup/generate TB outside exclusive region during step_atomic

From: "Emilio G. Cota" Now that all code generation has been converted to check CF_PARALLEL, we can generate !CF_PARALLEL code without having yet set !parallel_cpus -- and therefore without having to be in the exclusive region during cpu_exec_step_atomic. While at it, merge

[Qemu-devel] [PATCH v7 21/52] tcg: Use offsets not indices for TCGv_*

Using the offset of a temporary, relative to TCGContext, rather than its index means that we don't use 0. That leaves offset 0 free for a NULL representation without having to leave index 0 unused. Signed-off-by: Richard Henderson --- tcg/tcg.h | 37

[Qemu-devel] [PATCH v7 23/52] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK

From: "Emilio G. Cota" This will enable us to decouple code translation from the value of parallel_cpus at any given time. It will also help us minimize TB flushes when generating code via EXCP_ATOMIC. Note that the declaration of parallel_cpus is brought to exec-all.h to be

[Qemu-devel] [PATCH v7 25/52] tcg: Include CF_COUNT_MASK in CF_HASH_MASK

Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 352abc7450..0fdb72bb22 100644 --- a/include/exec/exec-all.h +++

[Qemu-devel] [PATCH v7 22/52] tcg: Use pointers in TCGOp->args

This limits the indexing into tcg_ctx.temps to initial opcode generation time. Signed-off-by: Richard Henderson --- tcg/tcg.h | 46 +- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h

[Qemu-devel] [PATCH v7 29/52] target/i386: check CF_PARALLEL instead of parallel_cpus

From: "Emilio G. Cota" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 17/52] tcg: Introduce temp_tcgv_{i32, i64, ptr}

Signed-off-by: Richard Henderson --- tcg/tcg.h | 26 +- tcg/tcg.c | 74 +++ 2 files changed, 53 insertions(+), 47 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index

[Qemu-devel] [PATCH v7 18/52] tcg: Remove GET_TCGV_* and MAKE_TCGV_*

The GET and MAKE functions weren't really specific enough. We now have a full compliment of functions that convert exactly between temporaries, arguments, tcgv pointers, and indices. The target/sparc change is also a bug fix, which would have affected a host that defines

[Qemu-devel] [PATCH v7 20/52] qom: Introduce CPUClass.tcg_initialize

Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Acked-by: Andreas Färber Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 13/52] tcg: Use per-temp state data in optimize

From: Richard Henderson While we're touching many of the lines anyway, adjust the naming of the functions to better distinguish when "TCGArg" vs "TCGTemp" should be used. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v7 14/52] tcg: Push tcg_ctx into generator functions

Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 100 +++ tcg/tcg-op.c | 47 ++-- 2 files changed, 69 insertions(+), 78 deletions(-)

[Qemu-devel] [PATCH v7 12/52] tcg: Remove unused TCG_CALL_DUMMY_TCGV

From: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.h | 1 - 1 file changed, 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index

[Qemu-devel] [PATCH v7 09/52] tcg: Use per-temp state data in liveness

From: Richard Henderson This avoids having to allocate external memory for each temporary. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 6 ++ tcg/tcg.c | 225

[Qemu-devel] [PATCH v7 16/52] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp}

Transform TCGv_* to an "argument" or a temporary. For now, an argument is simply the temporary index. Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 10 ++--- include/exec/helper-head.h | 12 +++--- tcg/tcg-op.h | 94

[Qemu-devel] [PATCH v7 15/52] tcg: Push tcg_ctx into tcg_gen_callN

Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 12 ++-- tcg/tcg.h | 3 +-- tcg/tcg.c | 4 ++-- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git

[Qemu-devel] [PATCH v7 11/52] tcg: Change temp_allocate_frame arg to TCGTemp

From: Richard Henderson Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 840e65c0d4..c10e73babe 100644 ---

[Qemu-devel] [PATCH v7 10/52] tcg: Avoid loops against variable bounds

From: Richard Henderson Copy s->nb_globals or s->nb_temps to a local variable for the purposes of iteration. This should allow the compiler to use low-overhead looping constructs on some hosts. Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée

[Qemu-devel] [PATCH v7 08/52] tcg: Introduce temp_arg, export temp_idx

From: Richard Henderson At the same time, adrop the TCGContext argument and use tcg_ctx instead. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 12 tcg/tcg.c | 19 ++- 2 files

[Qemu-devel] [PATCH v7 07/52] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG

From: Richard Henderson Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index fc4d1ed58b..5fcdec1fc5 100644 --- a/tcg/tcg.h

[Qemu-devel] [PATCH v7 06/52] tcg: Add temp_global bit to TCGTemp

From: Richard Henderson This avoids needing to test the index of a temp against nb_globals. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 12 tcg/optimize.c | 15 --- tcg/tcg.c

[Qemu-devel] [PATCH v7 05/52] tcg: Introduce arg_temp

From: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.h | 5 + tcg/optimize.c | 4 ++-- tcg/tcg.c | 51

[Qemu-devel] [PATCH v7 02/52] tcg: Propagate args to op->args in optimizer

From: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 430 ++--- 1 file changed, 227

[Qemu-devel] [PATCH v7 03/52] tcg: Propagate args to op->args in tcg.c

From: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 121 ++ 1 file changed, 58

[Qemu-devel] [PATCH v7 04/52] tcg: Propagate TCGOp down to allocators

From: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 75 +++ 1 file changed, 37

[Qemu-devel] [PATCH v7 01/52] tcg: Merge opcode arguments into TCGOp

From: Richard Henderson Rather than have a separate buffer of 10*max_ops entries, give each opcode 10 entries. The result is actually a bit smaller and should have slightly more cache locality. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v7 00/52] tcg queued patches

A bit silly to keep calling this "tb_lock removal", since it doesn't quite, and it has accumulated several additional patches. Changes since v6: * Dropped unnecessary rename of "temps". (Patch 13) * Changed how I avoid 0 as a TCGv_{i32,i64,ptr} value. Instead of avoiding TCGTemp index 0,

Re: [Qemu-devel] host physical address width issues/questions for x86_64

On 10/18/2017 8:33 PM, Peter Xu wrote: On Wed, Oct 18, 2017 at 10:19:31AM -0700, Prasad Singamsetty wrote: On 10/16/2017 8:56 PM, Peter Xu wrote: On Mon, Oct 16, 2017 at 10:02:25AM -0700, Prasad Singamsetty wrote: On 10/14/2017 8:53 PM, Peter Xu wrote: On Fri, Oct 13, 2017 at

Re: [Qemu-devel] [PATCH] build: allow setting a custom GIT binary for transparent proxying

Hi Daniel, > diff --git a/configure b/configure > index 6f21aaf989..ce5a2d0105 100755 > --- a/configure > +++ b/configure > @@ -271,6 +271,7 @@ then > else > git_submodules="" > fi > +git="git" > > # Don't accept a target_list environment variable. > unset target_list > @@ -1294,6

Re: [Qemu-devel] [PATCH v1] arm: Adding new arm machine, Kinetis K64 MK64FN1M0

> +/*dev = sysbus_create_simple(TYPE_KINETIS_SPI, 0x4002C000, > +qdev_get_gpio_in(nvic, 31)); *SPI0*/ > +/*dev = sysbus_create_simple(TYPE_KINETIS_SPI, 0x4002D000, > +qdev_get_gpio_in(nvic, 33)); *SPI1*/ > +/*dev = sysbus_create_simple(TYPE_KINETIS_ADC,

Re: [Qemu-devel] [PATCH v1] arm: Adding new arm machine, Kinetis K64 MK64FN1M0

On 10/19/2017 09:50 AM, gabriel291...@gmail.com wrote: > From: Gabriel Augusto Costa > > I add a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using

Re: [Qemu-devel] [PATCH v3 04/11] kinetis_k64_sim.h has been added

Hi Gabriel, On 10/20/2017 12:39 PM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using UART0 in polling mode. > I have prepared a

[Qemu-devel] [PULL v2 5/5] openrisc: Only kick cpu on timeout, not on update

Previously we were kicking the cpu on every update. This caused problems noticeable in SMP configurations where one CPU got pinned continuously servicing timer exceptions. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne ---

Re: [Qemu-devel] [PATCH v3 10/11] kinetis_k64_flextimer.c has been added

Hi Gabriel, On 10/20/2017 12:43 PM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using UART0 in polling mode. > I have prepared a

[Qemu-devel] [PULL v2 4/5] openrisc: Initial SMP support

Wire in ompic and add basic support for SMP. The OpenRISC is special in that interrupts for devices are routed to each core's PIC. This is achieved using the qemu_irq_split utility, but this currently limits OpenRISC to 2 cores. This models the reference architecture described in the OpenRISC

[Qemu-devel] [PULL v2 3/5] openrisc/cputimer: Perparation for Multicore

In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec

[Qemu-devel] [PULL v2 0/5] OpenRISC SMP Support

Hello Again, Please consider for pull. The following changes since commit e822e81e350825dd94f41ee2538ff1432b812eb9: Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-10-20 15:04:00 +0100) are available in the git repository at:

[Qemu-devel] [PULL v2 1/5] openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne ---

[Qemu-devel] [PULL v2 2/5] target/openrisc: Make coreid and numcores variable

Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Reviewed-by: Richard Henderson Signed-off-by: Stafford

Re: [Qemu-devel] [PULL 0/5] OpenRISC SMP Support

On Fri, Oct 20, 2017 at 05:51:13PM +0100, Peter Maydell wrote: > On 13 October 2017 at 15:57, Stafford Horne wrote: > > Hello, > > > > Please consider for pull. > > > > The following changes since commit 7851197b812b383ae1208c5d86391c5179c8209d: > > > > Update version for

Re: [Qemu-devel] [PATCH v3 08/11] kinetis_k64_pmux.c has been added

On 10/20/2017 12:41 PM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using UART0 in polling mode. > I have prepared a series of patchs

[Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

On a successful address translation instruction, PAR is supposed to contain cacheability and shareability attributes determined by the translation. We previously returned 0 for these bits (in line with the general strategy of ignoring caches and memory attributes), but some guest OSes may depend

Re: [Qemu-devel] [PATCH v3 01/11] kinetis_k64_uart.h has been added

Hi Gabriel Augusto, Since your series covers an ARM mcu, please also send it to the qemu-...@nongnu.org list. On 10/20/2017 12:37 PM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family.

Re: [Qemu-devel] [PATCH v3 03/11] kinetis_k64_pmux.h has been added

On 10/20/2017 12:38 PM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using UART0 in polling mode. > I have prepared a series of patchs

Re: [Qemu-devel] [PATCH v3 01/11] kinetis_k64_uart.h has been added

On 10/20/2017 03:49 PM, Gabriel Costa wrote: > Thanks, > > I found an example in [Qemu-devel] and in the next time I will include it. > also, I note now that I did not put [Qemu-devel] and arm: in the messages. > Should I resend everything corrected? The list automatically prefixes [Qemu-devel],

Re: [Qemu-devel] [PATCH v3 01/11] kinetis_k64_uart.h has been added

Thanks, I found an example in [Qemu-devel] and in the next time I will include it. also, I note now that I did not put [Qemu-devel] and arm: in the messages. Should I resend everything corrected? On Fri, Oct 20, 2017 at 4:18 PM, Eric Blake wrote: > On 10/20/2017 10:37 AM,

Re: [Qemu-devel] [PATCH v5 11/11] nbd: Minimal structured read for client

On 10/20/2017 02:58 PM, Vladimir Sementsov-Ogievskiy wrote: > 20.10.2017 01:26, Eric Blake wrote: >> From: Vladimir Sementsov-Ogievskiy >> >> Minimal implementation: for structured error only error_report error >> message. >> >> Signed-off-by: Vladimir

Re: [Qemu-devel] [PATCH v3 01/11] kinetis_k64_uart.h has been added

On 10/20/2017 10:37 AM, Gabriel Augusto Costa wrote: > I made a new arm machine with some peripherals. The machine is mk64fn1m0, a > cortex-m4 microcontroller from NXP Kinetis family. The machine can run a > simple arm binary file using UART0 in polling mode. > I have prepared a series of patchs

Re: [Qemu-devel] [PATCH v2] sockets: avoid leak of listen file descriptor

On 10/20/2017 09:12 AM, Daniel P. Berrange wrote: > If we iterate over the full port range without successfully binding+listening > on the socket, we'll try the next address, whereupon we overwrite the slisten > file descriptor variable without closing it. > > Rather than having two places where

Re: [Qemu-devel] nvme: Add tracing v3

On Thu, Oct 12, 2017 at 3:07 PM, Doug Gale wrote: > From c7f12a5949458fdd195b5e0b52f158e8f114f203 Mon Sep 17 00:00:00 2001 > From: Doug Gale > Date: Thu, 12 Oct 2017 14:29:07 -0400 > Subject: [PATCH] nvme: Add tracing > > Add trace output for commands,

Re: [Qemu-devel] [PATCH] build: allow setting a custom GIT binary for transparent proxying

On 10/20/2017 09:10 AM, Daniel P. Berrange wrote: > Some users can't run a bare 'git' command, due to need for a transparent > proxying solution such as 'tsocks'. This adds an argument to configure to > let users specify such a thing: > > ./configure --with-git="tsocks git" > > The submodule

Re: [Qemu-devel] [RFC 0/6] enable numa configuration before machine_init() from HMP/QMP

On Fri, Oct 20, 2017 at 10:07:27AM +0100, Daniel P. Berrange wrote: > On Thu, Oct 19, 2017 at 05:56:49PM -0200, Eduardo Habkost wrote: > > On Thu, Oct 19, 2017 at 04:28:59PM +0100, Daniel P. Berrange wrote: > > > On Thu, Oct 19, 2017 at 11:21:22AM -0400, Igor Mammedov wrote: > > > > - Original

Re: [Qemu-devel] [PATCH v5 11/11] nbd: Minimal structured read for client

20.10.2017 01:26, Eric Blake wrote: From: Vladimir Sementsov-Ogievskiy Minimal implementation: for structured error only error_report error message. Signed-off-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Eric Blake

Re: [Qemu-devel] [RFC 0/6] enable numa configuration before machine_init() from HMP/QMP

On Fri, Oct 20, 2017 at 12:21:30PM +1100, David Gibson wrote: > On Thu, Oct 19, 2017 at 02:23:04PM +0200, Paolo Bonzini wrote: > > On 19/10/2017 13:49, David Gibson wrote: > > > Note that describing socket/core/thread tuples as arch independent (or > > > even machine independent) is.. debatable.

[Qemu-devel] [PATCH v3 11/11] mk64fn1m0.c has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 10/11] kinetis_k64_flextimer.c has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 07/11] kinetis_k64_mcg.c has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 08/11] kinetis_k64_pmux.c has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 05/11] kinetis_k64_flextimer.h has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 04/11] kinetis_k64_sim.h has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 03/11] kinetis_k64_pmux.h has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 02/11] kinetis_k64_mcg.h has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

[Qemu-devel] [PATCH v3 01/11] kinetis_k64_uart.h has been added

I made a new arm machine with some peripherals. The machine is mk64fn1m0, a cortex-m4 microcontroller from NXP Kinetis family. The machine can run a simple arm binary file using UART0 in polling mode. I have prepared a series of patchs to include this machine: PATCH v3 n/11: It adds the machine

Re: [Qemu-devel] [PATCH v5 08/11] nbd/client: refactor nbd_receive_starttls

On 10/20/2017 02:26 PM, Vladimir Sementsov-Ogievskiy wrote: > 20.10.2017 01:26, Eric Blake wrote: >> From: Vladimir Sementsov-Ogievskiy >> >> Split out nbd_request_simple_option to be reused for structured reply >> option. >> >> Signed-off-by: Vladimir

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