On 08/02/2018 09:02 AM, Janosch Frank wrote:
> QEMU has had huge page support for a longer time already, but KVM
> memory management under s390x needed some changes to work with huge
> backings.
>
> Now that we have support, let's enable it if requested and
> available. Otherwise we now properly
On 08/02/2018 04:07 PM, David Gibson wrote:
> On Thu, Aug 02, 2018 at 10:16:32AM +0100, Peter Maydell wrote:
>> On 2 August 2018 at 08:08, David Gibson wrote:
>>> The macio fix, however, *is* a regression from 2.12. Whether it's
>>> severe enough to warrant another -rc, I'm not sure. It is a
On Thu, Aug 02, 2018 at 03:44:27PM +0100, Peter Maydell wrote:
> This patchset removes various uses of old_mmio from minor PPC
> devices:
> * hw/ppc/prep had an entirely ifdeffed-out stub of an XCSR device,
>which we remove
> * hw/ppc/ppc_boards had ref405ep_fpga
> * hw/ppc/ppc405_uc had
This adds the base for a machine model of the BBC micro:bit:
https://en.wikipedia.org/wiki/Micro_Bit
This is a system with a nRF51 SoC containing the main processor, with
various peripherals on board.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Joel Stanley
---
v2:
- Instead of setting
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.
Signed-off-by: Joel Stanley
v4: Fix number of IRQs
Based-on: 20180725085944.11856-1-stefa...@redhat.com
This short series implements a minimal definition of the Nordic
Semiconductor nRF51, a Cortex-M0 ARM SoC, and the BBC micro:bit, a
machine that will use this SoC.
This work will serve as the base for our Google Summer of
This contains the NRF51, and the machine that uses it, the BBC
micro:bit.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Joel Stanley
---
v3:
fix spelling of mailing list
add stefan's reviewed-by
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS
There's file size maximum in ext4 and it's 16TB
Can I create qcow2 ex:32TB and write more than 16TB?
thx
Hello. I'm a distro maintainer and was wondering about the efficacy of
entropy daemons like haveged and jitterentropyd in qemu-kvm. One of the
authors of haveged [0] pointed out if the hardware cycles counter is
emulated and deterministic, and thus predictible. He therefore does not
recommend
2018-08-02 18:47 GMT+08:00 Dr. David Alan Gilbert :
> * Li Qiang (liq...@gmail.com) wrote:
> > Currently, the default maximum CPU throttle for migration is
> > 99(CPU_THROTTLE_PCT_MAX). This is too big and can make a remarkable
> > performance effect for the guest. We see a lot of packets latency
Paolo, is this else branch dead code (or bug?):
/* If the lock is held, just mark the node as deleted */
if (qemu_lockcnt_count(>list_lock)) {
node->deleted = 1;
node->pfd.revents = 0;
} else {
/* Otherwise, delete it for real. We can't
> On Aug 2, 2018, at 10:10 PM, Fam Zheng wrote:
>
> On Thu, 08/02 20:50, John Arbuckle wrote:
>> Add an examples section to the help output.
>>
>> Signed-off-by: John Arbuckle
>> ---
>> qemu-img.c | 11 +++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/qemu-img.c
On Thu, 08/02 20:50, John Arbuckle wrote:
> Add an examples section to the help output.
>
> Signed-off-by: John Arbuckle
> ---
> qemu-img.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/qemu-img.c b/qemu-img.c
> index 1acddf693c..f77c82695d 100644
> --- a/qemu-img.c
>
On Mon, 09 Jul 2018 16:04:48 PDT (-0700), Michael Clark wrote:
On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis
wrote:
On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote:
> What is the state of the sifive_u emulation? When I tried to boot a bbl
> with an included kernel I get these
Add an examples section to the help output.
Signed-off-by: John Arbuckle
---
qemu-img.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/qemu-img.c b/qemu-img.c
index 1acddf693c..f77c82695d 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -199,6 +199,17 @@ static void QEMU_NORETURN
> On Aug 2, 2018, at 5:07 PM, Palmer Dabbelt wrote:
>
> On Fri, 29 Jun 2018 14:20:34 PDT (-0700), alistai...@gmail.com wrote:
>> On Fri, Jun 29, 2018 at 2:05 PM, G 3 wrote:
>>> Hi, I noticed your RISC-V patches on the mailing list and had a question
>>> that I think you may be able to answer.
Hi everyone,
I am pleased to announce that the QEMU v2.12.1 stable release is now
available:
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v2.12.1 is now tagged in the official qemu.git repository,
and the stable-2.12 branch has been updated
On 2 August 2018 at 13:43, Stefan Hajnoczi wrote:
> On Mon, Jul 30, 2018 at 07:01:53PM +0100, Peter Maydell wrote:
>> I'm still not convinced we want to add another random
>> special case only-works-on-one-architecture-and-some-boards
>> feature to the -kernel command line option.
>>
>> Adding it
On 05/18/2018 03:35 PM, Sandra Loosemore wrote:
On 05/18/2018 02:19 PM, Julian Brown wrote:
On Fri, 18 May 2018 21:52:04 +0200
Marek Vasut wrote:
On 05/18/2018 09:23 PM, Julian Brown wrote:
This patch (by Sandra Loosemore, mildly rebased) adds support for
semihosting for Nios II bare-metal
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1533219424-7627-1-git-send-email-stefan.marko...@rt-rk.com
Subject: [Qemu-devel] [PATCH v6 00/77] Add nanoMIPS support to QEMU
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On Mon, Jul 30, 2018 at 07:01:53PM +0100, Peter Maydell wrote:
> On 25 July 2018 at 09:59, Stefan Hajnoczi wrote:
> > From: Su Hang
> >
> > This patch adds Intel Hexadecimal Object File format support to the
> > loader. The file format specification is available here:
> >
On Fri, 29 Jun 2018 14:20:34 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Jun 29, 2018 at 2:05 PM, G 3 wrote:
Hi, I noticed your RISC-V patches on the mailing list and had a question
that I think you may be able to answer. Has anyone defined a RISC-V platform
yet? What I mean is defining
On 2 August 2018 at 20:13, Philippe Mathieu-Daudé wrote:
> Hi Peter,
>
> On 07/30/2018 10:23 AM, Peter Maydell wrote:
>> The tests in tests/vm/ seem to make some attempt to cope with the
>> host system not allowing the user to use KVM, but it doesn't quite
>> work. The problem is that
** Tags added: whishlist
** Tags removed: whishlist
** Tags added: wishlist
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1784919
Title:
native libgfapi glusterfs support for virtio 9p
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id:
153321150379.28572.4771679861864409417.mal...@chaenomeles.canonical.com
Subject: [Qemu-devel] [Bug 1784900] Re: QEMU (frontend) crashes upon warm
reboot with virtio-gpu
Le 02/08/2018 à 16:17, Stefan Markovic a écrit :
> From: Aleksandar Rikalo
>
> Add support for nanomips[eb] variant in scripts/qemu-binfmt-conf.sh.
>
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> scripts/qemu-binfmt-conf.sh | 12 ++--
> 1 file changed,
Hey,
Sorry for the top post. I’m on holidays at the moment and will be back next
week.
I have sent a V2 to the list, I don’t think I CCed you as I know your busy.
Once the 3.1 merge window opens I’ll send a new version with all the comments I
have received.
Alistair
From: Palmer Dabbelt
Hi Peter,
On 07/30/2018 10:23 AM, Peter Maydell wrote:
> The tests in tests/vm/ seem to make some attempt to cope with the
> host system not allowing the user to use KVM, but it doesn't quite
> work. The problem is that tests/vm/basevm.py always uses "-cpu host"
> in the QEMU options it uses to
On 08/02/2018 03:05 PM, Denis V. Lunev wrote:
> On 08/02/2018 12:50 PM, Dr. David Alan Gilbert wrote:
>> * Denis V. Lunev (d...@openvz.org) wrote:
>>
>>
I don't quite understand the last two paragraphs.
>>> we are thinking right now to eliminate delay on regular IO
>>> for migration. There
On 08/02/2018 12:50 PM, Dr. David Alan Gilbert wrote:
> * Denis V. Lunev (d...@openvz.org) wrote:
>
>
>>> I don't quite understand the last two paragraphs.
>> we are thinking right now to eliminate delay on regular IO
>> for migration. There is some thoughts and internal work in
>> progress. That
On 08/02/2018 03:06 PM, Peter Maydell wrote:
> Move the m48t59 device away from using old_mmio MemoryRegionOps
> accessors.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
> ---
> Tested with 'make check' and by booting a sparc guest.
>
> hw/timer/m48t59.c | 59
Le 02/08/2018 à 17:51, Peter Maydell a écrit :
Convert the vga-isa-mm device away from the old_mmio
MemoryRegion accessors.
This device is only used by the MIPS 'jazz' boards
"magnum" and "pica61".
Signed-off-by: Peter Maydell
---
hw/display/vga-isa-mm.c | 60
Thomas Huth writes:
> On 08/02/2018 06:53 AM, Markus Armbruster wrote:
>> Thomas Huth writes:
>>
>>> On 07/30/2018 08:32 AM, Markus Armbruster wrote:
Eric Blake writes:
> On 07/27/2018 11:46 AM, Thomas Huth wrote:
>> On 07/27/2018 05:13 PM, Markus Armbruster wrote:
>>>
Move the m48t59 device away from using old_mmio MemoryRegionOps
accessors.
Signed-off-by: Peter Maydell
---
Tested with 'make check' and by booting a sparc guest.
hw/timer/m48t59.c | 59 +--
1 file changed, 11 insertions(+), 48 deletions(-)
diff
> From: Richard Henderson
> Sent: Thursday, August 2, 2018 7:28 PM
>
> On 08/02/2018 08:29 AM, Aleksandar Markovic wrote:
> > Hi, Richard,
> >
> > We are going to remove obsoleted helpers, that was just an honest mistake
> > made in a rush.
> >
> > For unprotected access to gpr, we are going to
On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.fran...@wdc.com wrote:
Alistair Francis (5):
hw/riscv/virtio: Set the soc device tree node as a simple-bus
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the Xilinx PCIe
hw/riscv/virt: Connect a VGA PCIe device
The only difference between our implementation of the pcnet ioport
accessors and the mmio accessors is that the former check BCR_DWIO to
see what access widths are permitted for addresses in the aprom range
(0x0..0xf). In fact our failure to do this in the mmio accessors
is a bug (one which was
Convert the pcnet-pci device away from using the old_mmio
MemoryRegionOps accessor functions.
This commit is a no-behaviour-change API conversion.
(Since PCNET_PNPMMIO_SIZE is 0x20, the old "addr & 0x10"
check and the new "addr < 0x10" check are exact opposites;
the new code is phrased to be
This patchset converts the pcnet-pci's MMIO BAR MemoryRegionOps
away from the old_mmio accessors.
It does it in two stages:
* patch 1 is a no-behaviour-change patch which replaces the old
split byte/word/long accessor functions with single read and
write functions which take the size, and
On 08/02/2018 10:16 AM, Stefan Markovic wrote:
> case NM_P16_LB:
> +switch (extract32(ctx->opcode, 2, 2)) {
> +case NM_LB16:
> +offset = extract32(ctx->opcode, 0, 2);
> +gen_ld(ctx, OPC_LB, rt, rs, offset);
> +break;
> +case NM_SB16:
Le 02/08/2018 à 16:44, Peter Maydell a écrit :
The prep machine has some code which is stubs of accessors
for XCSR registers. This has been disabled via #if 0
since commit b6b8bd1819ff in 2004, and doesn't have any
actual interesting content. It also uses the deprecated
old_mmio accessor
On 08/02/2018 10:16 AM, Stefan Markovic wrote:
> From: Yongbok Kim
>
> Add emulation of nanoMIPS 16-bit arithmetic instructions.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/mips/translate.c | 125
>
On 08/02/2018 08:29 AM, Aleksandar Markovic wrote:
> Hi, Richard,
>
> We are going to remove obsoleted helpers, that was just an honest mistake
> made in a rush.
>
> For unprotected access to gpr, we are going to insert if(reg1 != 0) in two
> places.
Be careful that you do not eliminate side
On 08/02/2018 01:40 PM, Peter Maydell wrote:
> On 2 August 2018 at 16:58, Philippe Mathieu-Daudé wrote:
>> Hopefully this is a good case to show the bug I'm having with
>> access_with_adjusted_size().
>>
>> I agree with your change, so:
>> Reviewed-by: Philippe Mathieu-Daudé
>>
>> However IMO
On 2 August 2018 at 16:58, Philippe Mathieu-Daudé wrote:
> Hopefully this is a good case to show the bug I'm having with
> access_with_adjusted_size().
>
> I agree with your change, so:
> Reviewed-by: Philippe Mathieu-Daudé
>
> However IMO little endian guest access is likely to fail.
>
> The
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180801123111.3595-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH 0/4] target/arm sve fixes
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git
On my system vga_draw_graphic is called with a surface_width(surface) =
1280, the next time surface_width(surface) = 1024, and then the next
time again with surface_width(surface) = 1280. So it's a quick
resolution change. Each time the surface pointer changes as well as
surface_width(surface) and
On 08/02/2018 12:51 PM, Peter Maydell wrote:
> Convert the vga-isa-mm device away from the old_mmio
> MemoryRegion accessors.
>
> This device is only used by the MIPS 'jazz' boards
> "magnum" and "pica61".
>
> Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
> ---
>
On 08/02/2018 12:54 PM, Peter Maydell wrote:
> On 2 August 2018 at 16:45, Philippe Mathieu-Daudé wrote:
>> While not directly use the harmless UnimplementedDevice?
>>
>>create_unimplemented_device("ppc-xcsr", 0xfeff, 0x1000);
>
> I preferred not to change the current behaviour for
On 08/02/2018 11:44 AM, Peter Maydell wrote:
> Convert the devices in ppc405_uc away from using the old_mmio
> MemoryRegion accessors:
>
> * opba's 32-bit and 16-bit accessors were just calling the
>8-bit accessors and assembling a big-endian order number,
>which we can do by setting the
On 08/02/2018 04:47 PM, Greg Kurz wrote:
> On Mon, 30 Jul 2018 16:11:34 +0200
> Cédric Le Goater wrote:
>
>> The new layout using static IRQ number does not leave much space to
>> the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
>> number of IRQS for newer machines and introduce
Hi Peter,
On 08/02/2018 11:44 AM, Peter Maydell wrote:
> Switch the ref405ep_fpga device away from using the old_mmio
> MemoryRegion accessors.
>
> Signed-off-by: Peter Maydell
> ---
> hw/ppc/ppc405_boards.c | 60 +++---
> 1 file changed, 10 insertions(+),
On 2 August 2018 at 16:45, Philippe Mathieu-Daudé wrote:
> While not directly use the harmless UnimplementedDevice?
>
>create_unimplemented_device("ppc-xcsr", 0xfeff, 0x1000);
I preferred not to change the current behaviour for this
API conversion. If the PPC/prep maintainers would
These patches convert a couple of devices used only by MIPS
boards from using the old_mmio MemoryRegionOps accessor functions.
* vga-isa-mm: used by the MIPS 'jazz' boards "magnum" and "pica61"
* bonito pci controller: used by the MIPS "fulong2e" board
Tested only with "make check".
thanks
--
Move away from the old_mmio MemoryRegion accessors in the
bonito pci controller.
This device is used only in the MIPS "fulong2e" machine.
Signed-off-by: Peter Maydell
---
hw/pci-host/bonito.c | 145 +--
1 file changed, 15 insertions(+), 130 deletions(-)
Convert the vga-isa-mm device away from the old_mmio
MemoryRegion accessors.
This device is only used by the MIPS 'jazz' boards
"magnum" and "pica61".
Signed-off-by: Peter Maydell
---
hw/display/vga-isa-mm.c | 60 +
1 file changed, 13 insertions(+), 47
On 02.08.2018 09:02, Janosch Frank wrote:
> QEMU has had huge page support for a longer time already, but KVM
> memory management under s390x needed some changes to work with huge
> backings.
>
> Now that we have support, let's enable it if requested and
> available. Otherwise we now properly
On 08/02/2018 11:44 AM, Peter Maydell wrote:
> The prep machine has some code which is stubs of accessors
> for XCSR registers. This has been disabled via #if 0
> since commit b6b8bd1819ff in 2004, and doesn't have any
> actual interesting content. It also uses the deprecated
> old_mmio accessor
On 08/01/2018 09:31 AM, Richard Henderson wrote:
> Reported-by: Laurent Desnogues
> Signed-off-by: Richard Henderson
> ---
> target/arm/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index
A throttle group can have several members, and each one of them can
have several pending requests in the queue.
The requests are processed in a round-robin fashion, so the algorithm
decides the drive that is going to run the next request and sets a
timer in it. Once the timer fires and the
In the throttling code after an I/O request has been completed the
next one is selected from a different member using a round-robin
algorithm. This ensures that all members get a chance to finish their
pending I/O requests.
However, if a group member has its I/O limits disabled (because it's
On Wed, 25 Jul 2018 11:12:33 +0200
David Hildenbrand wrote:
> The "max" CPU model behaves like "-cpu host" when KVM is enabled, and like
> a CPU with the maximum possible feature set when TCG is enabled.
>
> While the "host" model can not be used under TCG ("kvm_required"), the
> "max" model
The previous patch fixes a problem in which draining a block device
with more than one throttled request can make it wait first for the
completion of requests in other members of the same group.
This patch updates test_remove_group_member() in iotest 093 to
reproduce that scenario. This updated
Switch the ref405ep_fpga device away from using the old_mmio
MemoryRegion accessors.
Signed-off-by: Peter Maydell
---
hw/ppc/ppc405_boards.c | 60 +++---
1 file changed, 10 insertions(+), 50 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c
The prep machine has some code which is stubs of accessors
for XCSR registers. This has been disabled via #if 0
since commit b6b8bd1819ff in 2004, and doesn't have any
actual interesting content. It also uses the deprecated
old_mmio accessor functions. Remove it entirely.
Signed-off-by: Peter
Hi all,
here are the patches that I promised yesterday.
I was originally thinking to propose this for the v3.0 release, but
after debugging and fixing the problem I think that it's not
essential (details below).
The important patch is the second one. The first and the third are
just test cases
Both NBD_CMD_BLOCK_STATUS and structured NBD_CMD_READ will split
their reply according to bdrv_block_status() boundaries. If the
block device has a request_alignment smaller than 512, but we
advertise a block alignment of 512 to the client, then this can
result in the server reply violating client
Add a test for the NBD server fix in the previous patch. In
short, when serving a raw POSIX file that is not aligned to
sector boundaries, qemu must not split a structured read or
block status result any smaller than the block size that it
advertised to the client; since qemu as client rejects
Commit 6fccbb475bc6effc313ee9481726a1748b6dae57 fixed a bug caused by
QEMU attempting to remove a throttle group member with no pending
requests but an active timer set. This was the result of a previous
bdrv_drained_begin() call processing the throttled requests but
leaving the timer untouched.
Rich reported a bug when using qemu as client to nbdkit serving
a non-sector-aligned image; in turn, I found a second bug with
qemu as server of such an image.
Both bugs were present in 2.12, and thus are not new regressions
in 3.0. If there is a reason to spin -rc4, then these could be
included;
The next patch needs access to a device's minimum permitted
alignment, since NBD wants to advertise this to clients. Add
an accessor function, borrowing from blk_get_max_transfer()
for accessing a backend's block limits.
Signed-off-by: Eric Blake
---
include/sysemu/block-backend.h | 1 +
When a server advertises an unaligned size but no block sizes,
the code was rounding up to a sector-aligned size (a known
limitation of bdrv_getlength()), then assuming a request_alignment
of 512 (the recommendation of the NBD spec for maximum portability).
However, this means that qemu will
From: Aleksandar Rikalo
Add support for nanomips[eb] variant in scripts/qemu-binfmt-conf.sh.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
scripts/qemu-binfmt-conf.sh | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git
On Mon, 30 Jul 2018 16:11:34 +0200
Cédric Le Goater wrote:
> The new layout using static IRQ number does not leave much space to
> the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
> number of IRQS for newer machines and introduce a legacy XICS backend
> for pre-3.1 machines to
From: Aleksandar Rikalo
Implement support for syscall statx(). The implementation is based on
invoking other (more mature) syscalls (from the same 'stat' family)
on the host side. This way, problems of availability of statx() on the
host are avoided.
Signed-off-by: Aleksandar Markovic
This patchset removes various uses of old_mmio from minor PPC
devices:
* hw/ppc/prep had an entirely ifdeffed-out stub of an XCSR device,
which we remove
* hw/ppc/ppc_boards had ref405ep_fpga
* hw/ppc/ppc405_uc had three minor devices
As you can see from the diffstat, the new API provides
From: Stefan Markovic
Add new linux user mode configuration for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
configure | 13 -
default-configs/nanomips-linux-user.mak | 1 +
2
From: Dimitrije Nikolic
Amend regular MIPS' cpu_loop.c to include nanoMIPS support.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 8 +++-
linux-user/nanomips/cpu_loop.c | 1 +
2 files changed, 8
From: Aleksandar Rikalo
Add signal trampoline support for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/signal.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
Convert the devices in ppc405_uc away from using the old_mmio
MemoryRegion accessors:
* opba's 32-bit and 16-bit accessors were just calling the
8-bit accessors and assembling a big-endian order number,
which we can do by setting the .impl.max_access_size to 1
and the endianness to
From: Aleksandar Rikalo
Amend sigaction syscall support for nanoMIPS. This must be done
since nanoMIPS' signal handling is different than MIPS' signal
handling.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 2 +-
From: Aleksandar Rikalo
Add target_syscall.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_syscall.h | 30 ++
1 file changed, 30 insertions(+)
create mode
From: Dimitrije Nikolic
Add target_structs.h header for nanoMIPS, that in fact only redirects
to the corresponding MIPS header.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_structs.h | 1 +
1 file changed,
From: Dimitrije Nikolic
This header includes common elf header, and adds cpu_get_model()
function.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_elf.h | 14 ++
1 file changed, 14 insertions(+)
From: Dimitrije Nikolic
Add signal.c as a redirection to regular mips' signal.c, but at the
same time amend regular mips' signal.c with bits and pieces specific
for nanoMIPS. This was done this way to avoid duplication of large
pieces of code.
Signed-off-by: Aleksandar Rikalo
Signed-off-by:
From: Aleksandar Rikalo
Add sockbits.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/sockbits.h | 1 +
1 file changed, 1 insertion(+)
create mode 100644 linux-user/nanomips/sockbits.h
diff
From: Aleksandar Markovic
Update constants and structures related to linux user syscall support
in nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/syscall_defs.h | 57 ++-
From: Dimitrije Nikolic
Add target_cpu.h header for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_cpu.h | 21 +
1 file changed, 21 insertions(+)
create mode 100644
From: Aleksandar Rikalo
Add termbits.h header for nanoMIPS. Reuse MIPS' termbits.h as
the functionalities are almost identical.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/termbits.h | 4
From: Aleksandar Rikalo
Add fcntl-related constants and structures for nanoMIPS.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/nanomips/target_fcntl.h | 38 ++
1 file changed, 38
From: Aleksandar Rikalo
Add syscall numbers for nanoMIPS. nanoMIPS redefines its ABI
compared to preceding MIPS architectures, and its set of
supported system calls is significantly different.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
From: Aleksandar Rikalo
nanoMIPS signal handling is much closer to the signal handling in
other mainstream platforms than to the signal handling in preceding
MIPS platforms.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
From: Stefan Markovic
Add XML support files for GDB for nanoMIPS.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
MAINTAINERS| 3 ++-
gdb-xml/nanomips-cp0.xml | 13 +
gdb-xml/nanomips-cpu.xml | 44
From: James Hogan
nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc1, and prevents writing to the PC clearing
MIPS_HFLAG_M16.
Signed-off-by: James Hogan
Signed-off-by: Yongbok
From: Stefan Markovic
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate_init.inc.c | 39 +++
1 file changed, 39 insertions(+)
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 6.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 64 +
1 file changed, 64 insertions(+)
diff --git
From: Stefan Markovic
Add testing Config1.WR bit into watch exception handling logic.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c| 1 +
target/mips/translate.c | 8
2 files changed, 9 insertions(+)
diff --git a/target/mips/helper.c
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
hw/mips/mips_malta.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index d1a7c1f..8bb1686 100644
---
From: Paul Burton
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 5.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 159
1 file changed, 159 insertions(+)
diff --git
1 - 100 of 197 matches
Mail list logo
