From: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 67 +
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index
From: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 43 +++--
1 file changed, 20 insertions(+), 23 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/pci-host/ppce500.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/ppce500.c
From: Roman Kapl
External PID is a mechanism present on BookE 2.06 that enables application to
store/load data from different address spaces. There are special version of some
instructions, which operate on alternate address space, which is specified in
the EPLC/EPSC regiser.
This
From: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 60 ++---
1 file changed, 26 insertions(+), 34 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index
The following changes since commit 4de6bb0c02ad3f0ec48f0f84ba1a65ab06e81b86:
Update version for v3.1.0-rc0 release (2018-11-06 18:27:35 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-3.1-20181108
for you to fetch changes up
From: Richard Henderson
The always_inline trick only works if the function is always
called from the outer-most helper. But it isn't, so pass in
the outer-most return address. There's no need for a switch
statement whose argument is always a constant. Unravel the
switch and goto via more
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/ppc4xx_pci.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/ppc440_pcix.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c
Hi,
while going through the reviews of the riscv-decodetree patches, two bugs came
up that I fix here. There is one more problem [1] mentioned by Richard but
I don't have the time to investigate it further.
[1] https://patchwork.kernel.org/patch/10650293/
Bastian Koppelmann (2):
sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/translate.c
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d147..5359088e24 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1237,13
On Thu, 8 Nov 2018 11:15:31 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Cc: Philippe Mathieu-Daudé
>
On Thu, 8 Nov 2018 11:15:30 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Cc: Richard Henderson
>
On 08/11/2018 11:14, Thomas Huth wrote:
> On 2018-11-08 10:55, Paolo Bonzini wrote:
>> On 07/11/2018 20:30, Thomas Huth wrote:
>>> On 2018-11-07 20:24, Eduardo Habkost wrote:
On Wed, Nov 07, 2018 at 06:39:54PM +0100, Paolo Bonzini wrote:
> On 07/11/2018 16:41, Samuel Ortiz wrote:
>> -
On Thu, 8 Nov 2018 11:15:29 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Cc: Paolo Bonzini
> Suggested-by:
On Thu, 8 Nov 2018 11:15:28 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Suggested-by: Eric Blake
>
On Thu, 8 Nov 2018 11:15:27 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Also change git.qemu-project.org to
On 08.11.18 12:07, Cornelia Huck wrote:
> On Wed, 7 Nov 2018 15:28:31 -0500
> Collin Walling wrote:
>
>> On 11/5/18 6:50 AM, David Hildenbrand wrote:
>>> On 05.11.18 12:40, Christian Borntraeger wrote:
On 11/05/2018 12:37 PM, David Hildenbrand wrote:
> On 05.11.18 12:21,
On Thu, 8 Nov 2018 11:15:26 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Reported-by: Jann Horn
>
On Thu, 8 Nov 2018 11:15:25 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Reported-by: Jann Horn
>
On Thu, 8 Nov 2018 11:15:24 +
Stefan Hajnoczi wrote:
> When you clone the repository without previous commit history, 'git://'
> doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> since the client verifies the server certificate.
>
> Reported-by: Jann Horn
>
On Wed, 7 Nov 2018 15:46:35 +1100
David Gibson wrote:
> On Mon, Oct 15, 2018 at 12:49:53PM +1100, Alexey Kardashevskiy wrote:
> >
> >
> > On 12/10/2018 20:05, Greg Kurz wrote:
> > > According to CODING_STYLE, structured types names are expected to be
> > > in CamelCase but we have:
> > >
>
On 6 November 2018 at 21:37, Paolo Bonzini wrote:
> The following changes since commit fc3d1bad1edf08871275cf469a64e12dae4eba96:
>
> oslib-posix: Use MAP_STACK in qemu_alloc_stack() on OpenBSD (2018-11-06
> 10:52:23 +)
>
> are available in the git repository at:
>
>
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20181106110548.4209-1-luc.mic...@greensocs.com
Subject: [Qemu-devel] [PATCH v4 00/16] gdbstub: support for the multiprocess
extension
=== TEST SCRIPT BEGIN ===
#!/bin/bash
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Suggested-by: Eric Blake
Reviewed-by: Eric Blake
Signed-off-by: Stefan Hajnoczi
---
MAINTAINERS|
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Cc: Philippe Mathieu-Daudé
Suggested-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Tested-by:
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Cc: Paolo Bonzini
Suggested-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Reported-by: Jann Horn
Reviewed-by: Daniel P. Berrangé
Acked-by: Cornelia Huck
Signed-off-by: Stefan
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Also change git.qemu-project.org to git.qemu.org (we control both domain
names but qemu.org is used more
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Reported-by: Jann Horn
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Tested-by:
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Cc: Richard Henderson
Suggested-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe
v4:
* Once more, with feeling! Fix 'https//' in get_maintainer.pl [Philippe]
v3:
* Fix broken openhackware URL [Eric]
* Convert a few remaining URLs [Eric]
v2:
* Use HTTPS for repo.or.cz [Eric]
Jeff Cody has enabled git smart HTTP support on qemu.org. From now on HTTPS is
the preferred
When you clone the repository without previous commit history, 'git://'
doesn't protect from man-in-the-middle attacks. HTTPS is more secure
since the client verifies the server certificate.
Reported-by: Jann Horn
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Tested-by:
On 8 November 2018 at 10:59, Li Zhijian wrote:
> In order to support >= 2G initrd, we need to change len type from int to
> uin32_t.
>
> Below is the flow sample to show how qemu copy initrd from qemu
> side to VM when using optionroms bootlinux_dma.bin:
> dma_memory_read(uint32_t len)
> ->
On Mon, 5 Nov 2018 13:46:10 +0100
David Hildenbrand wrote:
> On 05.11.18 13:41, Cornelia Huck wrote:
> > On Mon, 5 Nov 2018 13:04:04 +0100
> > Thomas Huth wrote:
> >
> >> On 2018-11-05 12:03, David Hildenbrand wrote:
> >>> Right now, errors during realize()/pre_plug/plug of the zPCI device
On 08/11/2018 11:59, Alex Bennée wrote:
> host_rt_dev_ptr is set while looping through a control structure. The
> compiler can not know that all structures passed to do_ioctl_rt will
> trigger the if clause so rightly complains with an --enable-sanitizers
> build. To keep the compiler happy we
On Wed, 7 Nov 2018 15:28:31 -0500
Collin Walling wrote:
> On 11/5/18 6:50 AM, David Hildenbrand wrote:
> > On 05.11.18 12:40, Christian Borntraeger wrote:
> >>
> >>
> >> On 11/05/2018 12:37 PM, David Hildenbrand wrote:
> >>> On 05.11.18 12:21, Cornelia Huck wrote:
> On Mon, 5 Nov
On Wed, Nov 07, 2018 at 05:24:14PM -0200, Eduardo Habkost wrote:
> On Wed, Nov 07, 2018 at 06:39:54PM +0100, Paolo Bonzini wrote:
> > On 07/11/2018 16:41, Samuel Ortiz wrote:
> > > - The Kconfig parser would be used to generate the equivalent of what we
> > > currently have under
On 8 November 2018 at 10:59, Li Zhijian wrote:
> x86/x86_64 has alredy supported 4G initrd.
>
> linux/arch/x86/boot/header.S:
> # (Header version 0x0203 or later) the highest safe address for the contents
> # of an initrd. The current kernel allows up to 4 GB, but leave it at 2 GB to
> # avoid
On 8 November 2018 at 10:59, Li Zhijian wrote:
> allow load_image to load >= 2G file
>
> CC: Philip Li
> Signed-off-by: Li Zhijian
> ---
> hw/core/loader.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/core/loader.c b/hw/core/loader.c
> index aa0b3fc..8fbc4bd
host_rt_dev_ptr is set while looping through a control structure. The
compiler can not know that all structures passed to do_ioctl_rt will
trigger the if clause so rightly complains with an --enable-sanitizers
build. To keep the compiler happy we default the host_rt_dev_ptr and
check it has been
On Sun, Nov 04, 2018 at 11:37:21PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Stefan,
>
> On 4/11/18 12:24, Stefan Hajnoczi wrote:
> > When you clone the repository without previous commit history, 'git://'
> > doesn't protect from man-in-the-middle attacks. HTTPS is more secure
> > since the
On Wed, 7 Nov 2018 11:26:50 -0500
Collin Walling wrote:
> On 11/5/18 6:19 AM, Cornelia Huck wrote:
> > On Mon, 5 Nov 2018 12:03:10 +0100
> > David Hildenbrand wrote:
> >
> >> I fail to see why this is useful as we require MSIX always and
> >> completely fail adding a device.
> >>
> >>
Le jeu. 8 nov. 2018 11:30, Thomas Huth a écrit :
> On 2018-11-08 10:55, Paolo Bonzini wrote:
> > On 07/11/2018 20:30, Thomas Huth wrote:
> >> On 2018-11-07 20:24, Eduardo Habkost wrote:
> >>> On Wed, Nov 07, 2018 at 06:39:54PM +0100, Paolo Bonzini wrote:
> On 07/11/2018 16:41, Samuel Ortiz
On Mon, Nov 05, 2018 at 05:54:25PM +, Peter Maydell wrote:
> On 5 November 2018 at 10:45, Julia Suvorova wrote:
> > Some functional tests for:
> > Basic reception/transmittion
> > Suspending
> > INTEN* registers
> >
> > Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de>
Am 08.11.2018 um 11:02 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 07.11.2018 21:16, Kevin Wolf wrote:
> > (Broken quoting in text/plain again)
> >
> > Am 01.11.2018 um 13:17 hat Vladimir Sementsov-Ogievskiy geschrieben:
> >> 27.09.2018 20:35, Max Reitz wrote:
> >>
> >> On 07.08.18 19:43,
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng
---
Address Igor's comments to add a doc
---
docs/specs/acpi_hest_ghes.txt | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 docs/specs/acpi_hest_ghes.txt
diff --git
On Mon, Nov 05, 2018 at 01:45:24PM +0300, Julia Suvorova wrote:
> +writel(NRF51_UART_BASE + A_UART_SUSPEND, 0x01);
> +writel(NRF51_UART_BASE + A_UART_TXD, 'h');
> +writel(NRF51_UART_BASE + A_UART_STARTTX, 0x01);
> +w_to_txd("world");
> +g_assert(read(sock_fd, s, 10) == 5);
> +
Long long ago, linux kernel have supported up to 4G initrd, but it's header
still
hard code to allow 2G - 1 only.
# (Header version 0x0203 or later) the highest safe address for the contents
# of an initrd. The current kernel allows up to 4 GB, but leave it at 2 GB to
# avoid possible
Add SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fill this PA
to guest APEI GHES memory, then notify guest according to the SIGBUS type.
There are two kinds of SIGBUS that QEMU needs to handle, which are
BUS_MCEERR_AO
In the ARMv8 platform, the CPU error type are synchronous external
abort(SEA) and SError Interrupt (SEI). If exception happens to guest,
sometimes guest itself do the recovery is better, because host
does not know guest's detailed information. For example, if a guest
user-space application
x86/x86_64 has alredy supported 4G initrd.
linux/arch/x86/boot/header.S:
# (Header version 0x0203 or later) the highest safe address for the contents
# of an initrd. The current kernel allows up to 4 GB, but leave it at 2 GB to
# avoid possible bootloader bugs.
CC: Philip Li
Signed-off-by:
kvm_hwpoison_page_add() and kvm_unpoison_all() will be used both
by X86 and ARM platforms, so move these functions to a common
accel/kvm/ folder to avoid duplicate code.
Signed-off-by: Dongjiu Geng
---
Address Peter's comments to move related hwpoison page function to
accel/kvm folder in [1]
Add Generic Error Status Block structures and some macros
definitions, which is referred to the ACPI 4.0 or ACPI 6.2. The
HEST table generation and CPER record will use them.
Signed-off-by: Dongjiu Geng
---
Change since v14:
Thanks Igor's review and comments
1. Update spec comment for
allow load_image to load >= 2G file
CC: Philip Li
Signed-off-by: Li Zhijian
---
hw/core/loader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index aa0b3fc..8fbc4bd 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -77,7 +77,8
Support this feature since version 2.12, disable it by
default in the old version.
Signed-off-by: Dongjiu Geng
---
Address Shannon's comments to add platform version in [1].
[1]: https://lkml.org/lkml/2017/8/25/821
---
hw/arm/virt-acpi-build.c | 14 +-
hw/arm/virt.c| 4
Add synchronous external abort injection logic, setup
exception type and syndrome value. When switch to guest,
guest will jump to the synchronous external abort vector
table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10),
and ESR_ELx.FnV is set to not valid(0x1), which will
This implements APEI GHES Table generation and record CPER in
runtime via fw_cfg blobs.Now we only support two types of GHESv2,
which are GPIO-Signal and ARMv8 SEA. Afterwards, we can extend the
supported types if needed. For the CPER section type, currently it
is memory section because kernel
> From: Fredrik Noring
> Sent: Wednesday, November 7, 2018 8:18 PM
> To: Aleksandar Markovic; Aurelien Jarno; Philippe Mathieu-Daudé; Richard
> Henderson
> Cc: Jürgen Urban; Maciej W. Rozycki; Jia Liu; qemu-devel@nongnu.org
> Subject: [PATCH v2 3/6] target/mips: Fix HI[ac] and LO[ac] 32-bit
It will help to add Generic Error Status Block to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 14 ++
include/hw/acpi/aml-build.h | 6 ++
2 files
It will help to add Generic Error Data Entry to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 32
include/hw/acpi/aml-build.h | 6
It will help to add Hardware Error Notification to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 22 ++
include/hw/acpi/aml-build.h | 8
It will help to add Generic Error Status Block to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 14 ++
include/hw/acpi/aml-build.h | 6 ++
2 files
On Tue, Nov 06, 2018 at 05:16:14PM +0100, Laurent Vivier wrote:
> On 06/11/2018 16:15, Philippe Mathieu-Daudé wrote:
> > On 6/11/18 15:13, Michael S. Tsirkin wrote:
> >> On Tue, Nov 06, 2018 at 02:27:18PM +0100, Philippe Mathieu-Daudé wrote:
> >>> On 5/11/18 19:14, Michael S. Tsirkin wrote:
>
>
> From: Fredrik Noring
> Subject: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special R5900
> opcodes
>
> MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
> DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
> instead of the generic
It will help to add Hardware Error Notification to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 22 ++
include/hw/acpi/aml-build.h | 8
Add synchronous external abort injection logic, setup
exception type and syndrome value. When switch to guest,
guest will jump to the synchronous external abort vector
table entry.
The ESR_ELx.DFSC is set to synchronous external abort(0x10),
and ESR_ELx.FnV is set to not valid(0x1), which will
On 8 November 2018 at 10:20, Joel Stanley wrote:
> On Thu, 8 Nov 2018 at 20:12, Peter Maydell wrote:
>>
>> On 8 November 2018 at 09:32, Stefan Hajnoczi wrote:
>> > On Fri, Nov 02, 2018 at 01:07:17PM -0400, Steffen Görtz wrote:
>> >
>> > Thank you, Steffen! I have posted my Reviewed-by on all
On 2018-11-08 10:55, Paolo Bonzini wrote:
> On 07/11/2018 20:30, Thomas Huth wrote:
>> On 2018-11-07 20:24, Eduardo Habkost wrote:
>>> On Wed, Nov 07, 2018 at 06:39:54PM +0100, Paolo Bonzini wrote:
On 07/11/2018 16:41, Samuel Ortiz wrote:
> - The Kconfig parser would be used to generate
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng
Address Igor's comments to add a doc
---
docs/specs/acpi_hest_ghes.txt | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 docs/specs/acpi_hest_ghes.txt
diff --git
In the ARMv8 platform, the CPU error type are synchronous external
abort(SEA) and SError Interrupt (SEI). If exception happens to guest,
sometimes guest itself do the recovery is better, because host
does not know guest's detailed information. For example, if a guest
user-space application
In order to support >= 2G initrd, we need to change len type from int to
uin32_t.
Below is the flow sample to show how qemu copy initrd from qemu
side to VM when using optionroms bootlinux_dma.bin:
dma_memory_read(uint32_t len)
-> dma_memory_rw(uint32_t len)
->
Add SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fill this PA
to guest APEI GHES memory, then notify guest according to the SIGBUS type.
There are two kinds of SIGBUS that QEMU needs to handle, which are
BUS_MCEERR_AO
Add Generic Error Status Block structures and some macros
definitions, which is referred to the ACPI 4.0 or ACPI 6.2. The
HEST table generation and CPER record will use them.
Signed-off-by: Dongjiu Geng
Change since v14:
Thanks Igor's review and comments
1. Update spec comment for
kvm_hwpoison_page_add() and kvm_unpoison_all() will be used both
by X86 and ARM platforms, so move these functions to a common
accel/kvm/ folder to avoid duplicate code.
Signed-off-by: Dongjiu Geng
Address Peter's comments to move related hwpoison page function to
accel/kvm folder in [1]
It will help to add Generic Error Data Entry to ACPI tables
without using packed C structures and avoid endianness
issues as API doesn't need explicit conversion.
Signed-off-by: Dongjiu Geng
---
hw/acpi/aml-build.c | 32
include/hw/acpi/aml-build.h | 6
Support this feature since version 2.12, disable it by
default in the old version.
Signed-off-by: Dongjiu Geng
Address Shannon's comments to add platform version in [1].
[1]: https://lkml.org/lkml/2017/8/25/821
---
hw/arm/virt-acpi-build.c | 14 +-
hw/arm/virt.c| 4
This implements APEI GHES Table generation and record CPER in
runtime via fw_cfg blobs.Now we only support two types of GHESv2,
which are GPIO-Signal and ARMv8 SEA. Afterwards, we can extend the
supported types if needed. For the CPER section type, currently it
is memory section because kernel
On Thu, 8 Nov 2018 at 20:12, Peter Maydell wrote:
>
> On 8 November 2018 at 09:32, Stefan Hajnoczi wrote:
> > On Fri, Nov 02, 2018 at 01:07:17PM -0400, Steffen Görtz wrote:
> >
> > Thank you, Steffen! I have posted my Reviewed-by on all patches.
> >
> > Joel: Will you send pull requests for the
Hello,
On Thu, 2018-11-08 at 07:49 +0100, Gerd Hoffmann wrote:
> Hi,
>
> > + * The device_display_id_{start,count} denotes the sequence of device
> > display
> > + * IDs that map to the zero-based sequence of monitor IDs provided by
> > monitors
> > + * config on this interface. For example
07.11.2018 21:16, Kevin Wolf wrote:
> (Broken quoting in text/plain again)
>
> Am 01.11.2018 um 13:17 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 27.09.2018 20:35, Max Reitz wrote:
>>
>> On 07.08.18 19:43, Vladimir Sementsov-Ogievskiy wrote:
>>
>> Memory allocation may become
> On 8 Nov 2018, at 11:50, Paolo Bonzini wrote:
>
> On 08/11/2018 01:45, Jim Mattson wrote:
>> I have no attachments to the current design. I had used a data[] blob,
>> because I didn't think userspace would have any need to know what was
>> in there. However, I am now seeing the error of my
On 08/11/2018 09:46, Philippe Mathieu-Daudé wrote:
>
> Almost; if there's a conflict between the decision from "depends on" and
> "select" says, it's an error. (Likewise if there's a conflict between
> default-configs/ on one side, and "depends on"/"select" on the other).
>
>
On 07/11/2018 20:30, Thomas Huth wrote:
> On 2018-11-07 20:24, Eduardo Habkost wrote:
>> On Wed, Nov 07, 2018 at 06:39:54PM +0100, Paolo Bonzini wrote:
>>> On 07/11/2018 16:41, Samuel Ortiz wrote:
- The Kconfig parser would be used to generate the equivalent of what we
currently have
On 08/11/2018 01:45, Jim Mattson wrote:
> I have no attachments to the current design. I had used a data[] blob,
> because I didn't think userspace would have any need to know what was
> in there. However, I am now seeing the error of my ways. For example,
> the userspace instruction emulator
On 8 November 2018 at 09:32, Stefan Hajnoczi wrote:
> On Fri, Nov 02, 2018 at 01:07:17PM -0400, Steffen Görtz wrote:
>
> Thank you, Steffen! I have posted my Reviewed-by on all patches.
>
> Joel: Will you send pull requests for the microbit machine types or do
> you want Peter to merge this?
I
On 25 October 2018 at 12:38, Philippe Mathieu-Daudé wrote:
> Depending of the response to Peter's question [*]:
>
> I'd also like some confirmation from folks more familiar with the
> current state of the art in guest-to-management-layer communication
> that pvpanic is still the
On 7 November 2018 at 20:21, Eric Blake wrote:
> On 11/6/18 3:45 AM, Paolo Bonzini wrote:
>>
>> On 06/11/2018 00:16, Eric Blake wrote:
>>>
>>> On 10/18/18 3:31 PM, Paolo Bonzini wrote:
From: Artem Pisarenko
Attributes are simple flags, associated with individual timers for
On Fri, Nov 02, 2018 at 01:07:17PM -0400, Steffen Görtz wrote:
Thank you, Steffen! I have posted my Reviewed-by on all patches.
Joel: Will you send pull requests for the microbit machine types or do
you want Peter to merge this?
> This series contains additional peripheral devices for the
On Fri, Nov 02, 2018 at 01:07:28PM -0400, Steffen Görtz wrote:
> This patch adds the model for the nRF51 timer peripheral.
> Currently, only the TIMER mode is implemented.
>
> Signed-off-by: Steffen Görtz
> ---
> hw/timer/Makefile.objs | 1 +
> hw/timer/nrf51_timer.c | 368
On Fri, Nov 02, 2018 at 01:07:22PM -0400, Steffen Görtz wrote:
> The nRF51 contains three regions of non-volatile memory (NVM):
> - CODE (R/W): contains code
> - FICR (R): Factory information like code size, chip id etc.
> - UICR (R/W): Changeable configuration data. Lock bits, Code
> protection
Am 11.10.2018 um 09:21 hat Fam Zheng geschrieben:
> v5: Address Max's comments (Thanks for reviewing):
> - Clean up after test done.
> - Add rev-by to patch 1 and 2.
>
> v4: Fix test on systems without OFD. [Patchew]
>
> The first patch reduces chances of QEMU crash in unusual (but not
On 11/6/18 5:41 PM, Peter Maydell wrote:
> Remove a TODO comment about implementing the vectored interrupt
> controller. We have had an implementation of that for a decade;
> it's in hw/intc/pl190.c.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 1 -
> 1 file changed, 1
On 11/6/18 5:38 PM, Peter Maydell wrote:
> Before we supported direct execution from MMIO regions, we
> implemented workarounds in commit 720424359917887c926a33d2
> which let us avoid doing so, even if the SAU or MPU region
> was less than page-sized.
>
> Once we implemented execute-from-MMIO, we
Hello, Stefan.
I appreciate your note and guidance.
>
> On 25.10.18 22:19, Aleksandar Markovic wrote:
> > From: Aleksandar Markovic
> >
> > Add disassembler support for nanoMIPS.
> >
> > Reviewed-by: Stefan Markovic
> > Signed-off-by: Matthew Fortune
> > Signed-off-by: Aleksandar Markovic
On Sun, Oct 28, 2018 at 02:07:25AM +0800, Peng Hao wrote:
> The first patches are simple cleanups:
> - patch 1 move the pvpanic device with the 'ocmmon objects' so we compile
> it once for the x86/arm/aarch64 archs,
> - patch 2 simply renames ISA fields/definitions to generic ones.
>
> Then
David Hildenbrand writes:
>>> Would it be valid to do something like this (skipping elements without a
>>> proper visit_type_int)
>>>
>>> visit_start_list();
>>> visit_next_list(); more input, returns "there's more"
>>> visit_next_list(); parses "1-3,", buffers 2-3, skips over 1
>>>
Hi Markus,
Le jeu. 8 nov. 2018 09:46, Markus Armbruster a écrit :
> Cleber Rosa writes:
>
> > On 11/7/18 1:05 AM, Markus Armbruster wrote:
> >> Eduardo Habkost writes:
> >>
> >>> The $(SHELLSTATUS) variable requires GNU make >= 4.2, but Travis
> >>> seems to provide an older version. Change
On Sun, Oct 28, 2018 at 02:07:29AM +0800, Peng Hao wrote:
> add pvpanic device in aarch64 virt machine.
Why only aarch64 and not also arm?
Thanks,
drew
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