MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
corresponding external IRQ pin of selected subset of connected xtensa
cores. It has per-CPU and per-IRQ enable
The following changes since commit 5f39a91dbd9a186edb999afd4d17524f4b1da14f:
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into
staging (2019-01-28 12:54:06 +)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
From: Vitaly Kuznetsov
Modern AMD CPUs support NPT and NRIPSAVE features and KVM exposes these
when present. NRIPSAVE apeared somewhere in Opteron_G3 lifetime (e.g.
QuadCore AMD Opteron 2378 has is but QuadCore AMD Opteron HE 2344 doesn't),
NPT was introduced a bit earlier.
Add the FEAT_SVM
From: Tao Xu
Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.
Signed-off-by: Tao Xu
Message-Id: <20181227024304.12182-2-tao3...@intel.com>
Signed-off-by: Eduardo Habkost
---
Peter Maydell, le lun. 28 janv. 2019 15:44:21 +, a ecrit:
> Note that g_spawn_async_with_fds() is one of the glib routines
> which we have a version of in glib-compat.h to cope with older
> glib versions -- have you removed the #include of that and
> not provided the equivalent code for slirp?
Possibly a duplicate of https://bugs.launchpad.net/qemu/+bug/1776920
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1813406
Title:
qemu-img convert malfunction on macOS
Status in QEMU:
New
Bug
On Mon, 28 Jan 2019 18:13:55 +0100
Cornelia Huck wrote:
> On Fri, 25 Jan 2019 17:04:04 +0100
> Halil Pasic wrote:
>
> > Do we expect userspace/QEMU to fence the bad scenarios as tries to do
> > today, or is this supposed to change to hardware should sort out
> > requests whenever possible.
>
On 1/14/19 9:16 AM, Cornelia Huck wrote:
On Thu, 10 Jan 2019 11:22:48 -0500
Tony Krowiak wrote:
Can you extend this patch description a little bit, including what we
discussed here?
Maybe a short comment that explains why qdev_simple_device_unplug_cb()
is appropriate as well (i.e. hits that
On 1/28/19 11:08 AM, Kevin Wolf wrote:
> Am 25.01.2019 um 22:57 hat John Snow geschrieben:
>> On 1/25/19 3:34 PM, Philippe Mathieu-Daudé wrote:
>>> Since the ahci-test uses qemu-img, add a dependency to build it
>>> before using it.
>>> This fixes:
>>>
>>> $ gmake check-qtest V=1
>>>
On 28/01/2019 22:11, Eric Blake wrote:
> On 1/28/19 12:40 PM, Andrey Shinkevich wrote:
>> A new test file 239 added to the qemu-iotests set. It checks
>> the output format of 'qemu-img info' for bitmaps extension of
>> qcow2 specific information.
>>
>> Signed-off-by: Andrey Shinkevich
>> ---
>
On Mon, 28 Jan 2019 18:09:48 +0100
Cornelia Huck wrote:
> On Fri, 25 Jan 2019 15:01:01 +0100
> Halil Pasic wrote:
>
> > On Fri, 25 Jan 2019 13:58:35 +0100
> > Cornelia Huck wrote:
>
> > > - The code should not be interrupted while we process the channel
> > > program, do the ssch etc. We
On 1/28/19 12:40 PM, Andrey Shinkevich wrote:
> A new test file 239 added to the qemu-iotests set. It checks
> the output format of 'qemu-img info' for bitmaps extension of
> qcow2 specific information.
>
> Signed-off-by: Andrey Shinkevich
> ---
> +++ b/tests/qemu-iotests/239.out
> @@ -0,0
On Mon, Jan 28, 2019 at 06:22:30PM +, Dr. David Alan Gilbert wrote:
> * Vitaly Kuznetsov (vkuzn...@redhat.com) wrote:
> > Roman Kagan writes:
> >
> > > On Fri, Jan 25, 2019 at 02:46:42PM +0100, Vitaly Kuznetsov wrote:
> > >> Roman Kagan writes:
> > >>
> > >> > On Fri, Jan 25, 2019 at
On Thu, 24 Jan 2019 at 14:11, Stefan Hajnoczi wrote:
>
> From: Steffen Görtz
>
> Signed-off-by: Steffen Görtz
> Signed-off-by: Stefan Hajnoczi
> ---
> This resolves the conflict with Julia's UART test series due to
> global_qtest removal.
>
> tests/microbit-test.c | 108
In the 'Format specific information' section of the 'qemu-img info'
command output, the supplemental information about existing QCOW2
bitmaps will be shown, such as a bitmap name, flags and granularity:
image: /vz/vmprivate/VM1/harddisk.hdd
file format: qcow2
virtual size: 64G (68719476736 bytes)
A new test file 239 added to the qemu-iotests set. It checks
the output format of 'qemu-img info' for bitmaps extension of
qcow2 specific information.
Signed-off-by: Andrey Shinkevich
---
tests/qemu-iotests/239 | 58 ++
tests/qemu-iotests/239.out
Here is the update for the bitmap extension of the qcow2 specific
information as the output of the 'qemu-img info' command.
The version #7 was in email with the message ID:
<1544698788-52893-1-git-send-email-andrey.shinkev...@virtuozzo.com>
v8:
The output benchmark files for the qemu-iotests,
28 янв. 2019 г. 20:40 пользователь Kevin Wolf написал:
Am 28.01.2019 um 17:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 28.01.2019 18:59, Max Reitz wrote:
> > On 28.01.19 12:29, Vladimir Sementsov-Ogievskiy wrote:
> >> 18.01.2019 17:56, Max Reitz wrote:
> >>> On 29.12.18 13:20, Vladimir
On Mon, Jan 28, 2019 at 04:08:59PM -0200, Eduardo Habkost wrote:
> On Mon, Jan 28, 2019 at 11:54:49AM -0600, miny...@acm.org wrote:
> > From: Corey Minyard
> >
> > Migration capability is being added for pm_smbus and SMBus devices.
> > This change will allow backwards compatibility to be kept
Alberto Garcia writes:
> On Thu 24 Jan 2019 07:07:47 PM CET, Eric Blake wrote:
> 093 and 136 seem really flaky to me. I can reproduce that by
> running:
That's interesting, I can make 093 fail quite easily now (I haven't
tested the other one yet), but I don't think this
On 1/28/19 7:02 PM, Peter Maydell wrote:
> On Mon, 28 Jan 2019 at 17:47, Philippe Mathieu-Daudé
> wrote:
>>
>> Cc'ing Thomas/Paolo for Makefile rules...
>>
>> On 1/24/19 12:43 PM, Gerd Hoffmann wrote:
>>> Oops, fails the build:
>>>
>>> LINKlm32-softmmu/qemu-system-lm32
>>>
From: Steffen Görtz
Signed-off-by: Steffen Görtz
Signed-off-by: Stefan Hajnoczi
Acked-by: Thomas Huth
Message-id: 20190124141147.8416-1-stefa...@redhat.com
Signed-off-by: Peter Maydell
---
tests/microbit-test.c | 108 ++
1 file changed, 108
* Vitaly Kuznetsov (vkuzn...@redhat.com) wrote:
> Roman Kagan writes:
>
> > On Fri, Jan 25, 2019 at 02:46:42PM +0100, Vitaly Kuznetsov wrote:
> >> Roman Kagan writes:
> >>
> >> > On Fri, Jan 25, 2019 at 12:41:51PM +0100, Vitaly Kuznetsov wrote:
> >> >> In many case we just want to give Windows
Now we're keeping the cluster index in the CPUState, we don't
need to jump through hoops in gdb_get_cpu_pid() to find the
associated cluster object.
Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
Message-id: 20190121152218.9592-5-peter.mayd...@linaro.org
From: Cédric Le Goater
The m25p80 models dummy cycles using byte transfers. This works well
when the transfers are initiated by the QEMU model of a SPI controller
but when these are initiated by the OS, it breaks emulation.
Snoop the SPI transfer to catch commands requiring dummy cycles and
In checkpatch we attempt to check for and warn about
block comments which start with /* or /** followed by a
non-blank. Unfortunately a bug in the regex meant that
we would incorrectly warn about comments starting with
"/**" with no following text:
git show
Currently the cluster implementation doesn't have any constraints
on the ordering of realizing the TYPE_CPU_CLUSTER and populating it
with child objects. We want to impose a constraint that realize
must happen only after all the child objects are added, so move
the realize of rpu_cluster. (The
From: Cédric Le Goater
The SMC controllers have a register containing the byte that will be
used as dummy output. It can be modified by software.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Joel Stanley
Message-id:
From: Cédric Le Goater
0x should be returned for non implemented registers.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-id: 20190124140519.13838-2-...@kaod.org
Signed-off-by: Peter Maydell
---
hw/ssi/aspeed_smc.c | 2 +-
1 file changed, 1 insertion(+), 1
If we aren't going to create any RPUs, then don't create the
rpu-cluster unit. This allows us to add an assertion to the
cluster object that it contains at least one CPU, which helps
to avoid bugs in creating clusters and putting CPUs in them.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E.
From: Julia Suvorova
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
Acked-by: Thomas Huth
Message-id: 20190123120759.7162-4-jus...@mail.ru
Signed-off-by: Peter Maydell
---
are available in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-tcg-20190128
>
> for you to fetch changes up to e77c89fb086a9bf09dd11f72e4cb2093b426f32b:
>
> cputlb: Remove st
In cpu_signal_handler() for aarch64 hosts, currently we parse
the faulting instruction to see if it is a load or a store.
Since the 3.16 kernel (~2014), the kernel has provided us with
the syndrome register for a fault, which includes the WnR bit.
Use this instead if it is present, only falling
From: Julia Suvorova
Run qtest with a socket that connects QEMU chardev and test code.
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Message-id: 20190123120759.7162-2-jus...@mail.ru
Signed-off-by: Peter Maydell
---
For TCG we want to distinguish which cluster a CPU is in, and
we need to do it quickly. Cache the cluster index in the CPUState
struct, by having the cluster object set cpu->cluster_index for
each CPU child when it is realized.
This means that board/SoC code must add all CPUs to the cluster
On Mon, Jan 28, 2019 at 06:06:56AM +, Kang, Luwei wrote:
> > > > > Intel Processor Trace required CPUID[0x14] but the cpuid level is
> > > > > 0xd when create a kvm guest with e.g. "-cpu qemu64,+intel-pt".
> > > > >
> > > > > Signed-off-by: Luwei Kang
> > > > > ---
> > > > >
Include the cluster number in the hash we use to look
up TBs. This is important because a TB that is valid
for one cluster at a given physical address and set
of CPU flags is not necessarily valid for another:
the two clusters may have different views of physical
memory, or may have different CPU
From: Steffen Görtz
Recent microbit firmwares panic if the TWI magnetometer/accelerometer
devices are not detected during startup. We don't implement TWI (I2C)
so let's stub out these devices just to let the firmware boot.
Signed-off by: Steffen Görtz
Signed-off-by: Stefan Hajnoczi
From: Julia Suvorova
Using of global_qtest is not required here. Let's replace functions like
readl() with the corresponding qtest_* counterparts.
Signed-off-by: Julia Suvorova
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
Reviewed-by: Stefan Hajnoczi
Message-id:
From: Cédric Le Goater
The model should expose one control register per possible CS. When
testing the validity of the register number in the read operation,
replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum
number of flash devices a controller can handle.
Signed-off-by:
From: Richard Henderson
When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.
Fixes: ba97be9f4a4
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190125184913.5970-1-richard.hender...@linaro.org
Am 28.01.2019 um 17:53 hat Anton Kuchin geschrieben:
> On 28/01/2019 17:47, Kevin Wolf wrote:
> > Am 28.01.2019 um 15:27 hat Anton Kuchin geschrieben:
> > > Some HMP and QMP commands are targeting BlockBackend but
> > > for hotplugged devices name of BB is deprecated, instead
> > > name of root
From: Stefan Hajnoczi
ROM devices go via MemoryRegionOps->write() callbacks for write
operations and do not dirty/invalidate that memory. Device emulation
must be able to mark memory ranges that have been modified internally
(e.g. using memory_region_get_ram_ptr()).
Introduce the
From: Steffen Görtz
The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
protection configuration, Bootloader address, Nordic
From: Aaron Lindsay OS
A bug was introduced during a respin of:
commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
This patch introduced two calls to get_pmceid() during CPU
initialization - one each for
On 1/28/19 11:03 AM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Add a qmp command that can trigger guest announcements.
>
> It uses it's own announce-timer instance, and parameters
s/it's/its/ (here, you want the possessive form without apostrophe; the
contraction
Cc'ing Thomas/Paolo for Makefile rules...
On 1/24/19 12:43 PM, Gerd Hoffmann wrote:
> On Thu, Jan 24, 2019 at 02:15:54AM +0100, Philippe Mathieu-Daudé wrote:
>> Move the complexity of milkymist_tmu2_create() into the
>> source file. Doing so we avoid to include the X11/OpenGL
>> headers in all
From: Steffen Görtz
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC.
Signed-off-by: Steffen Görtz
Reviewed-by: Peter Maydell
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Stefan Hajnoczi
Message-id: 20190123212234.32068-5-stefa...@redhat.com
Signed-off-by: Peter Maydell
---
From: Cleber Rosa
This is the simplest possible migration test, exercising the multi
VM capabilities of the test class.
Signed-off-by: Cleber Rosa
---
tests/acceptance/migration.py | 45 +++
1 file changed, 45 insertions(+)
create mode 100644
On 28/01/2019 18:39, Alex Bennée wrote:
> Userspace programs should (in theory) query the ELF HWCAP before
> probing these registers. Now we have implemented them all make it
> public.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
> ---
> linux-user/elfload.c | 1 +
> 1 file
From: Stefan Hajnoczi
New source files were added without corresponding ./MAINTAINERS file
entries. Let's get things up to date.
Reviewed-by: Thomas Huth
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20190123183352.11025-1-stefa...@redhat.com
Signed-off-by:
From: Stefan Hajnoczi
This test verifies that we read back the expected I2C WHO_AM_I register
values for the accelerometer/magnetometer.
Signed-off-by: Stefan Hajnoczi
Message-id: 20190110094020.18354-3-stefa...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
In the softmmu version of cpu_memory_rw_debug(), we ask the
CPU for the attributes to use for the virtual memory access,
and we correctly use those to identify the address space
index. However, we were not passing them in to the
address_space_write_rom() and address_space_rw() functions.
The
On Mon, Jan 28, 2019 at 12:19:37PM -0500, Stefan Berger wrote:
> On 1/28/19 11:14 AM, Stefan Berger wrote:
> > On 1/28/19 9:45 AM, Igor Mammedov wrote:
> > > On Fri, 25 Jan 2019 16:00:58 -0500
> > > Stefan Berger wrote:
> > >
> > > > This patch makes the a TPM 2.0 with TIS interface available
From: Corey Minyard
smbus.c and smbus.h had device side code, master side code, and
smbus.h has some smbus_eeprom.c definitions. Split them into
separate files.
Signed-off-by: Corey Minyard
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
MAINTAINERS
repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20190128
for you to fetch changes up to dc192cb2d851c51ebd8d8e1a3b6b14ce9d16efc7:
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-28
18:03:16 +0
From: Thomas Roth
The current behavior of v8m_security_lookup in helper.c only checks whether the
IDAU specifies a higher security if the SAU is enabled. If SAU.ALLNS is set to
1, this will lead to addresses being treated as non-secure, even though the
IDAU indicates that they must be secure.
Am 28.01.2019 um 17:55 hat Markus Armbruster geschrieben:
> Kevin Wolf writes:
>
> > Am 28.01.2019 um 09:50 hat Peter Krempa geschrieben:
> [...]
> >> 2) Is actually using 'scsi-cd'/'scsi-hd' the better option than
> >> 'scsi-disk'?
> >
> > Yes, scsi-disk is a legacy device. Maybe we should
From: Luc Michel
a TID or PID value means "any thread" (resp. "any process"). This commit
fixes the different combinations when at least one value is 0.
When both are 0, the function now returns the first attached CPU,
instead of the CPU with TID 1, which is not necessarily attached or even
From: Corey Minyard
There were two different read functions, and with the removal of
the command passed in there is no functional difference. So remove
one of them. With that you don't need one of the states, so that
can be removed, too.
Signed-off-by: Corey Minyard
---
On Mon, Jan 28, 2019 at 11:54:49AM -0600, miny...@acm.org wrote:
> From: Corey Minyard
>
> Migration capability is being added for pm_smbus and SMBus devices.
> This change will allow backwards compatibility to be kept when
> migrating back to an old qemu version. Add a bool to the machine
>
This is the second attempt to add the multi vm capability to base class
of acceptance tests. The difference from first version is that in this
current version a simple migration test was added (done by Cleber) so
the new code that is being added is properly used and we're not adding
"new dead
I've forced some time open to work on this, it's been too long.
Changes since v3:
Change I2C to "I2C and SMBus" in the MAINTAINERS file.
Added a comment to the smbus_eeprom reset to make the reasoning for
the choice clear.
Fix a logic error introduced in "i2c: Don't check return value from
On Mon, Jan 28, 2019 at 6:13 PM Daniel P. Berrangé
wrote:
> On Mon, Jan 28, 2019 at 04:37:50PM +0100, Kevin Wolf wrote:
> > Am 28.01.2019 um 16:15 hat Anton Kuchin geschrieben:
> > > This option is broken since a6baa60807 in v2.9 and returns mostly
> > > zeroes instead of real stats because
On Mon, 28 Jan 2019 at 17:47, Philippe Mathieu-Daudé wrote:
>
> Cc'ing Thomas/Paolo for Makefile rules...
>
> On 1/24/19 12:43 PM, Gerd Hoffmann wrote:
> > Oops, fails the build:
> >
> > LINKlm32-softmmu/qemu-system-lm32
> > hw/lm32/milkymist.o: In function `milkymist_init':
> >
From: Corey Minyard
i2c_recv() cannot fail, so there is no need to check the return
value. It also returns unt8_t, so comparing with < 0 is not
meaningful.
Fix up various I2C controllers to remove the unneeded code.
Signed-off-by: Corey Minyard
Suggested-by: Peter Maydell
---
On 1/28/19 11:39 AM, Anton Kuchin wrote:
> Only part of block/qapi.c is used by qemu-io qemu-nbd and qemu-img
> and its not realy about QAPI, so move it to separate file to reduce
s/realy/really/
> amount of unused code linked to utilities and avoid unnecessary
> dependencies.
That's a decent
From: Corey Minyard
There were two different write functions and the SMBus code kept
track of the command.
Keeping track of the command wasn't useful, in fact it wasn't quite
correct for the eeprom_smbus code. And there is no need for two write
functions. Just have one write function and the
On Fri, Jan 18, 2019 at 01:38:26PM +, Daniel P. Berrangé wrote:
> A number of virtio devices (gpu, crypto, mouse, keyboard, tablet) only
> support the virtio-1 (aka modern) mode. Currently if the user launches
> QEMU, setting those devices to enable legacy mode, QEMU will silently
> create
From: Corey Minyard
Transfer the state information for the SMBus registers and
internal data so it will work on a VM transfer.
Signed-off-by: Corey Minyard
Cc: Michael S. Tsirkin
Cc: Paolo Bonzini
Cc: Dr. David Alan Gilbert
Reviewed-by: Dr. David Alan Gilbert
---
hw/acpi/piix4.c
From: Corey Minyard
This will be needed by coming I2C changes.
Signed-off-by: Corey Minyard
Reviewed-by: Dr. David Alan Gilbert
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index
From: Corey Minyard
The I2C block read function of pm_smbus was completely broken. It
required doing some direct I2C handling because it didn't have a
defined size, the OS code just reads bytes until it marks the
transaction finished.
This also required adjusting how the AMIBIOS workaround
From: Corey Minyard
It's not necessary, it won't be called if it's NULL.
Signed-off-by: Corey Minyard
---
hw/i2c/smbus_eeprom.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index c2b9e3383e..4bc579e69e 100644
---
From: Corey Minyard
Create a type name and a cast macro and use those through the
code.
Signed-off-by: Corey Minyard
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i2c/smbus_eeprom.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
From: Corey Minyard
It is never supposed to fail and cannot return an error, so just
have it return the proper type. Have it return 0xff on nothing
available, since that's what would happen on a real bus.
Signed-off-by: Corey Minyard
Reviewed-by: Peter Maydell
Reviewed-by: Philippe
From: Corey Minyard
Transfer the state of the EEPROM on a migration. This way the
data remains consistent on migration.
This required moving the actual data to a separate array and
using the data provided in the init function as a separate
initialization array, since a pointer property has to
From: Corey Minyard
Migration capability is being added for pm_smbus and SMBus devices.
This change will allow backwards compatibility to be kept when
migrating back to an old qemu version. Add a bool to the machine
class tho keep smbus migration from happening. Future changes
will use this.
From: Corey Minyard
It can't fail, and now that it returns a uint8_t a 0xff mask
is unnecessary.
Signed-off-by: Corey Minyard
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/arm/stellaris.c | 2 +-
1 file
From: Corey Minyard
It had spaces between cases in some places and not others. Add a space
for every one.
Signed-off-by: Corey Minyard
---
hw/i2c/smbus_eeprom.c | 1 +
hw/i2c/smbus_slave.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/hw/i2c/smbus_eeprom.c
From: Corey Minyard
Reset the contents to init data and reset the offset on a machine
reset.
Signed-off-by: Corey Minyard
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i2c/smbus_eeprom.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/smbus_eeprom.c
From: Corey Minyard
It was hard-coded to 256 in a number of places, create a constant
for that.
Signed-off-by: Corey Minyard
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i2c/smbus_eeprom.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/smbus_eeprom.c
From: Corey Minyard
There is no vmstate handling for SMBus, so no device sitting on SMBus
can have a state transfer that works reliably. So add it.
Signed-off-by: Corey Minyard
Cc: Paolo Bonzini
Cc: Michael S. Tsirkin
Cc: Dr. David Alan Gilbert
Reviewed-by: Dr. David Alan Gilbert
---
From: Corey Minyard
The logic of handling quick SMBus commands was wrong. If you get a
finish event with no data, that's a quick command.
Document the quick command while we are at it.
Signed-off-by: Corey Minyard
---
hw/i2c/smbus_slave.c | 35 +++
From: Corey Minyard
Keep someone from passing in a bogus number
Signed-off-by: Corey Minyard
---
hw/i2c/smbus_eeprom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 44887b4a27..ee392f7cb1 100644
--- a/hw/i2c/smbus_eeprom.c
+++
This change adds the possibility to write acceptance tests with multi
virtual machine support. It's done keeping the virtual machines objects
stored in a test attribute (dictionary). This dictionary shouldn't be
accessed directly but through the new method added `get_vm`. This new
method accept a
On 1/28/19 11:03 AM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The 'announce timer' will be used by migration, and explicit
> requests for qemu to perform network announces.
>
> Based on the work by Germano Veit Michel
> and Vlad Yasevich
>
> Signed-off-by:
On 1/28/19 11:03 AM, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Add migration parameters that control RARP/GARP announcement timeouts.
>
> Based on earlier patches by myself and
> Vladislav Yasevich
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> +++
On Fri, 25 Jan 2019 16:00:38 -0500
Eric Farman wrote:
> On 01/21/2019 06:03 AM, Cornelia Huck wrote:
> > Add a region to the vfio-ccw device that can be used to submit
> > asynchronous I/O instructions. ssch continues to be handled by the
> > existing I/O region; the new region handles hsch and
The tcg_register_iommu_notifier() code has a GArray of
TCGIOMMUNotifier structs which it has registered by passing
memory_region_register_iommu_notifier() a pointer to the embedded
IOMMUNotifier field. Unfortunately, if we need to enlarge the
array via g_array_set_size() this can cause a
Am 28.01.2019 um 17:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 28.01.2019 18:59, Max Reitz wrote:
> > On 28.01.19 12:29, Vladimir Sementsov-Ogievskiy wrote:
> >> 18.01.2019 17:56, Max Reitz wrote:
> >>> On 29.12.18 13:20, Vladimir Sementsov-Ogievskiy wrote:
> Drop write notifiers and
Userspace programs should (in theory) query the ELF HWCAP before
probing these registers. Now we have implemented them all make it
public.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
linux-user/elfload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/elfload.c
Hi,
I posted a series to expose some of the CPU registers to user-space.
The counter registers got merged at the time but the HW_CPUID had some
comments that needed addressing. I've re-spun the series and cleaned
it up, hopefully addressing the comments at the same time. The test
case has been
This tests a bunch of registers that the kernel allows userspace to
read including the CPUID registers.
Signed-off-by: Alex Bennée
---
v4
- also test for extra bits that shouldn't be exposed
---
tests/tcg/aarch64/Makefile.target | 2 +-
tests/tcg/aarch64/sysregs.c | 120
Although technically not visible to userspace the kernel does make
them visible via a trap and emulate ABI. We provide a new permission
mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
the minimum permission check accordingly.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h
A number of CPUID registers are exposed to userspace by modern Linux
kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's
user-mode emulation we don't need to emulate the kernels trap but just
return the value the trap would have done. For this we use the PL0U_R
permission mask
Only part of block/qapi.c is used by qemu-io qemu-nbd and qemu-img
and its not realy about QAPI, so move it to separate file to reduce
amount of unused code linked to utilities and avoid unnecessary
dependencies.
Signed-off-by: Anton Kuchin
---
block.c | 2 +-
* Leonardo Soares Müller (leozinho29...@hotmail.com) wrote:
> Here is the backtrace with the debug symbols added:
OK, great; can can you confirm the version of the spice packages
on both the guest and host, and the kernel on the guest.
Dave
> (gdb) bt
> #0 0x70373e97 in __GI_raise
On Fri, 25 Jan 2019 16:00:18 -0500
Eric Farman wrote:
> On 01/25/2019 11:19 AM, Eric Farman wrote:
> >
> >
> > On 01/21/2019 06:03 AM, Cornelia Huck wrote:
> >> Allow to extend the regions used by vfio-ccw. The first user will be
> >> handling of halt and clear subchannel.
> >>
> >>
On 28/01/2019 18:37, Kevin Wolf wrote:
Am 28.01.2019 um 16:15 hat Anton Kuchin geschrieben:
This option is broken since a6baa60807 in v2.9 and returns mostly
zeroes instead of real stats because actual querring of BlockStats
that resides in blk is missing.
And it makes no sense because with
On Fri, 25 Jan 2019 15:22:56 -0500
Eric Farman wrote:
> If we come into mdev_write with state=BUSY and we get the lock,
> copy_from_user, and do our jump table we go to fsm_io_busy to set
> ret_code and return -EAGAIN. Why then don't we set the jump table for
> state=NOT_OPER||STANDBY to do
101 - 200 of 439 matches
Mail list logo
