[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
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https://bugs.launchpad.net/bugs/1541643
Title:
Now that I am checking out 4.0.0 rc's I see this diff is broken and
depends on a function libfdt does not expose. The breakage is
hidden by the fallback check in the configure script.
On 1/8/2019 5:45 PM, David Gibson wrote:
From: Alexey Kardashevskiy
SLOF receives a device tree and updates
On 3/22/19 7:23 PM, asavah wrote:
> I'm using qemu-user-arm for crosscompilation needs, usually via a wrapper.
> qemu-user-arm (4.0.0-rc0) crashes with SIGILL on at least 2 instructions:
>
> first case (sadly I don't have more data handy, can reproduce at a later time
> if needed):
> (gdb) x/i
On Sat, Mar 23, 2019 at 05:26:36PM +0300, Jafar Abdi wrote:
> Clean up wrong usage of FALSE and TRUE in places that use "bool" from
> stdbool.h.
>
> FALSE and TRUE (with capital letters) are the constants defined by glib for
> being used with the "gboolean" type of glib. But some parts of the
On Sat, Mar 23, 2019 at 11:20:39AM +0100, Philippe Mathieu-Daudé wrote:
> Le sam. 23 mars 2019 07:50, Alistair Francis a
> écrit :
>
> > On Thu, Mar 21, 2019 at 11:49 PM Peter Maydell
> > wrote:
> > >
> > > Alex and I just noticed that we didn't pick up this
> > > MAINTAINERS patch for the
With Kevin's "block: Fix slow pre-zeroing in qemu-img convert"[1]
we skip the pre zero step called like this:
blk_make_zero(s->target, BDRV_REQ_MAY_UNMAP | BDRV_REQ_NO_FALLBACK)
And we write zeroes later using:
blk_co_pwrite_zeroes(s->target,
sector_num <<
On Fri, Mar 22, 2019 at 10:47 PM Eric Blake wrote:
> On 3/22/19 3:22 PM, Nir Soffer wrote:
>
> > Thanks for fixing this! This will be a very important performance fix for
> > importing
> > VMs.
> >
> > The change description sounds good to me.
> >
> > Can you make these patches available on some
Attaching the patch and sending for review as:
https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg06562.html
** Patch added: "patch to fix denormals"
https://bugs.launchpad.net/qemu/+bug/1821444/+attachment/5248915/+files/0001-powerpc-fix-denorm-float-double-conversion.patch
--
The bug is initially discovered in GHC test suite. Here is minimal reproducer:
```c
int main() {
volatile float f;
volatile double d;
*(volatile uint32_t*) = 0xc0de;
d = f;
printf("f = %#x\n", *(volatile uint32_t*));
printf("d = %#llx (expect 0x37981bc0)\n",
On Sat, Mar 23, 2019 at 8:48 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 3/23/19 2:10 AM, Howard Spoelstra wrote:
> > I applied this series to master on a G5 and a G4, both with Lubuntu. The
> > qemu-system-ppc and qemu-system-ppc64 builds fail to run on both. Below
> is the
Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 6 ++
target/xtensa/overlay_tool.h | 2 +
target/xtensa/translate.c| 162
The Memory Protection Unit Option (MPU) is a combined instruction and
data memory protection unit with more protection flexibility than the
Region Protection Option or the Region Translation Option but without
any translation capability. It does no demand paging and does not
reference a
Remove declarations of the internal mmu_helper functions from the cpu.h,
make these functions static and shuffle them.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h| 19 --
target/xtensa/mmu_helper.c | 163 -
2 files changed, 87
IDMA and scatter/gather features introduced new IRQ types that
overlay_tool.h need to initialize Xtensa configuration.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 3 +++
target/xtensa/overlay_tool.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/target/xtensa/cpu.h
SR numbers are not unique: different Xtensa options may reuse SR number
for different purposes. Introduce generic rsr/wsr functions and xsr
template and use them instead of centralized SR access functions. Change
prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use
them instead
Hello,
this series adds support for memory protection unit, parity/ECC option
and IDMA and gather/scatter IRQ types. With these additions it is possible
to emulate basic opcode subset of the recent xtensa LX vision cores.
Max Filippov (5):
target/xtensa: get rid of centralized SR properties
Rich pointed out some fishy corner-case behavior of qemu in dealing
with a non-compliant NBD server on NBD_CMD_BLOCK_STATUS. Fix a real
bug in qemu-img, as well as teaching NBD to be a bit more tolerant of
buggy servers for more interoperability (be strict in what you
produce, but loose in what
The NBD spec states that NBD_CMD_FLAG_REQ_ONE (which we currently
always use) should not reply with an extent larger than our request,
and that the server's response should be exactly one extent. Right
now, that means that if a server sends more than one extent, we treat
the server as broken, fail
If bdrv_block_status_above() fails, we are aborting the convert
process but failing to print an error message. Broken in commit
690c7301 (v2.4) when rewriting convert's logic.
Discovered when teaching nbdkit to support NBD_CMD_BLOCK_STATUS, and
accidentally violating the protocol by returning
On 3/22/19 9:23 AM, Andrew Jones wrote:
> Andrew Jones (3):
> target/arm: fix crash on pmu register access
> target/arm: cortex-a7 and cortex-a15 have pmus
> target/arm: make pmccntr_op_start/finish static
Reviewed-by: Richard Henderson
r~
On 3/22/19 1:02 PM, Max Filippov wrote:
> Don't announce that exit simcall has been invoked: this is just noise.
>
> Signed-off-by: Max Filippov
> ---
> target/xtensa/xtensa-semi.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
Hi,
On Sat, Mar 23, 2019 at 1:43 PM Kenneth B. Jensen wrote:
> Could anybody please create an account for me?
>
> I would like to add some documentation to the Documentation/Networking
> page on setting up taps and bridges using iproute2.
I've created an account for you, user name:
On 3/22/19 1:43 PM, Emilio G. Cota wrote:
> From: Kito Cheng
>
> Before falling back to softfloat FMA, we do not restore the original
> values of inputs A and C. Fix it.
Reviewed-by: Richard Henderson
r~
On 3/23/19 2:50 PM, Max Filippov wrote:
I've created an account for you, user name: kenneth_b_jensen
I'll send password privately.
Thank you very much, Max!
Hi,
Could anybody please create an account for me?
I would like to add some documentation to the Documentation/Networking
page on setting up taps and bridges using iproute2.
Thanks,
Kenneth
Patchew URL:
https://patchew.org/QEMU/20190323190925.21324-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190323190925.21324-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH for-4.1
For all targets, do this just before including exec/cpu-all.h.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 4 ++--
target/arm/cpu.h| 4 ++--
target/cris/cpu.h | 4 ++--
target/hppa/cpu.h | 4 ++--
target/i386/cpu.h | 5 ++---
target/lm32/cpu.h
This started merely as an attempt to reduce the size of each
softmmu lookup by using smaller offsets from env. But in the
end it also represents a significant cleanup in the boilerplate
that each target must define.
With respect to the initial goal, here are the relevant code
snips generated for
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 8 ++--
accel/tcg/softmmu_template.h | 20 +-
include/exec/cpu-all.h
On 3/23/19 2:10 AM, Howard Spoelstra wrote:
> I applied this series to master on a G5 and a G4, both with Lubuntu. The
> qemu-system-ppc and qemu-system-ppc64 builds fail to run on both. Below is the
> gdb output from running a debug-enabled qemu-system-ppc on the G5.
Please try the following,
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 17 -
accel/tcg/cputlb.c | 24
2 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 8f2a848bf5..52d150aaf1 100644
---
Combined uses of CPU(arm_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 --
linux-user/aarch64/cpu_loop.c | 6 +-
linux-user/aarch64/signal.c | 4 +-
For all targets, do this just before including exec/cpu-all.h.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/cris/cpu.h | 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/lm32/cpu.h | 1 +
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Signed-off-by: Richard Henderson
---
accel/tcg/softmmu_template.h | 4 +-
include/exec/cpu-defs.h | 61 ---
Signed-off-by: Richard Henderson
---
target/cris/cpu.h | 5 -
linux-user/cris/cpu_loop.c | 2 +-
target/cris/mmu.c | 3 +--
target/cris/op_helper.c| 10 +++---
target/cris/translate.c| 2 +-
5 files changed, 6 insertions(+), 16 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 35 ++--
linux-user/microblaze/cpu_loop.c | 2 +-
target/microblaze/mmu.c | 5 ++---
target/microblaze/op_helper.c| 2 +-
target/microblaze/translate.c| 2 +-
5 files changed,
This will foo_env_get_cpu with a generic definition.
No changes to the target specific code so far.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
Combined uses of CPU(hppa_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h | 5 -
linux-user/hppa/cpu_loop.c | 2 +-
target/hppa/helper.c | 3 +--
Signed-off-by: Richard Henderson
---
linux-user/m68k/target_cpu.h | 2 +-
target/m68k/cpu.h| 5 -
linux-user/m68k-sim.c| 3 +--
linux-user/m68k/cpu_loop.c | 2 +-
target/m68k/helper.c | 33 -
target/m68k/m68k-semi.c | 4
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 5 -
bsd-user/main.c | 2 +-
hw/sparc/leon3.c| 4 ++--
hw/sparc/sun4m.c| 4 ++--
hw/sparc64/sparc64.c| 2 +-
linux-user/sparc/cpu_loop.c | 2 +-
target/sparc/fop_helper.c |
Signed-off-by: Richard Henderson
---
target/lm32/cpu.h | 5 -
target/lm32/helper.c| 19 ++-
target/lm32/op_helper.c | 6 +++---
target/lm32/translate.c | 2 +-
4 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
With exactly one exception, most uses of alpha_env_get_cpu
were failures to use the more proper, ENV_GET_CPU macro,
now replaced by env_cpu.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 5 -
linux-user/alpha/cpu_loop.c | 2 +-
target/alpha/helper.c | 8 +++-
Signed-off-by: Richard Henderson
---
target/tricore/cpu.h | 5 -
target/tricore/op_helper.c | 4 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index ed32622388..9ea5060a87 100644
--- a/target/tricore/cpu.h
+++
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 5 -
linux-user/sh4/cpu_loop.c | 2 +-
target/sh4/helper.c | 26 --
target/sh4/op_helper.c| 9 +++--
4 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/target/sh4/cpu.h
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h | 5 -
linux-user/riscv/cpu_loop.c | 2 +-
target/riscv/cpu_helper.c | 4 ++--
target/riscv/csr.c | 12 ++--
target/riscv/op_helper.c| 8
5 files changed, 13 insertions(+), 18 deletions(-)
Combined uses of CPU(x86_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Signed-off-by: Richard Henderson
---
target/i386/cpu.h | 5 -
bsd-user/main.c| 3 +--
hw/i386/kvmvapic.c | 4 ++--
hw/i386/pc.c
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index ac765137ae..979efbcfe4 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++
Signed-off-by: Richard Henderson
---
target/s390x/cpu.h | 5
linux-user/s390x/cpu_loop.c | 2 +-
target/s390x/cc_helper.c| 5 ++--
target/s390x/diag.c | 2 +-
target/s390x/excp_helper.c | 6 ++---
target/s390x/fpu_helper.c | 4 +--
target/s390x/helper.c |
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 17 ++---
hw/xtensa/pic_cpu.c | 2 +-
linux-user/xtensa/cpu_loop.c | 2 +-
target/xtensa/dbg_helper.c | 4 ++--
target/xtensa/exc_helper.c | 9 -
target/xtensa/helper.c | 2 +-
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 5 -
hw/nios2/cpu_pic.c | 5 +
target/nios2/mmu.c | 10 +-
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index e0e12a910e..3fc27ead81 100644
---
Signed-off-by: Richard Henderson
---
target/moxie/cpu.h | 5 -
target/moxie/helper.c| 6 +++---
target/moxie/translate.c | 2 +-
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index c050d6e15d..71e7cf0f08 100644
---
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h | 5 -
linux-user/openrisc/cpu_loop.c | 2 +-
target/openrisc/exception_helper.c | 5 ++---
target/openrisc/sys_helper.c | 8
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 109 +++
1 file changed, 52 insertions(+), 57 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 4a8c12e9a4..e2fd42e218 100644
--- a/tcg/arm/tcg-target.inc.c
+++
Amusingly, we had already ignored the comment to keep this
value at the end of CPUState. This restores the minimum
negative offset from TCG_AREG0 for code generation.
This is slightly complicated for qom/cpu.c and tcg-all.c,
in that they are compiled once. This means we need an out
of line
Signed-off-by: Richard Henderson
---
target/unicore32/cpu.h | 5 -
hw/unicore32/puv3.c | 2 +-
target/unicore32/helper.c | 8 ++--
target/unicore32/op_helper.c| 2 +-
target/unicore32/softmmu.c | 11 ---
target/unicore32/translate.c| 26
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h| 7 +-
target/ppc/helper_regs.h| 4 +-
hw/ppc/ppc.c| 18 ++---
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc_booke.c | 4 +-
linux-user/ppc/cpu_loop.c | 2 +-
This macro is now always empty, so remove it. This leaves the
entire contents of CPUArchState under the control of the guest
architecture.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 2 --
target/alpha/cpu.h | 3 ---
target/arm/cpu.h| 4 +---
target/cris/cpu.h
Signed-off-by: Richard Henderson
---
target/tilegx/cpu.h | 5 -
linux-user/tilegx/cpu_loop.c | 2 +-
target/tilegx/helper.c | 2 +-
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 135df63523..7f8fe7c513 100644
---
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 2 ++
target/alpha/cpu.h| 1 -
target/arm/cpu.h | 2 --
target/cris/cpu.h | 1 -
target/hppa/cpu.h | 1 -
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 24
include/exec/cpu-defs.h | 8
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h
Signed-off-by: Richard Henderson
---
target/mips/cpu.h| 5 -
hw/intc/mips_gic.c | 2 +-
hw/mips/mips_int.c | 2 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/helper.c | 15 +--
target/mips/op_helper.c
As requested I tarred the failing binaries.
The first one (first case in the original report) is g-ir-compiler from
gobjact-introspection, this one has another interesting detail:
if compiled with -mcpu=cortex-a53 -mfpu=neon-fp-armv8 (the correct flags for
raspberry pi 3) it crashes on
On 3/23/19 2:10 AM, Howard Spoelstra wrote:
> I applied this series to master on a G5 and a G4, both with Lubuntu. The
> qemu-system-ppc and qemu-system-ppc64 builds fail to run on both. Below is the
> gdb output from running a debug-enabled qemu-system-ppc on the G5.
...
> #4 0x1002d638 in
On 3/23/19 9:40 AM, Richard W.M. Jones wrote:
> On Sat, Mar 23, 2019 at 09:24:55AM -0500, Eric Blake wrote:
>> The NBD spec is clear that when structured replies are active, a
>> simple error reply is acceptable to any command except for
>> NBD_CMD_READ. However, we were mistakenly requiring
On Sat, Mar 23, 2019 at 09:24:55AM -0500, Eric Blake wrote:
> The NBD spec is clear that when structured replies are active, a
> simple error reply is acceptable to any command except for
> NBD_CMD_READ. However, we were mistakenly requiring structured errors
> for NBD_CMD_BLOCK_STATUS, and
On 3/23/19 9:26 AM, Jafar Abdi wrote:
> Clean up wrong usage of FALSE and TRUE in places that use "bool" from
> stdbool.h.
>
> FALSE and TRUE (with capital letters) are the constants defined by glib for
> being used with the "gboolean" type of glib. But some parts of the code also
> use
> TRUE
Dear Eric Blake,
Thank you very much for your review I learned a lot from it, I did what you
told me (hopefully I didn't forget something) and send V2 of the patch
Again thank you for your time,
best regards,
Jafar Abdi
On Fri, 22 Mar 2019 at 20:39, Eric Blake wrote:
> On 3/22/19 7:05 AM,
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are declared as "bool"
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are declared as "bool"
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are declared as "bool"
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are declared as "bool"
Clean up wrong usage of FALSE and TRUE in places that use "bool" from stdbool.h.
FALSE and TRUE (with capital letters) are the constants defined by glib for
being used with the "gboolean" type of glib. But some parts of the code also use
TRUE and FALSE for variables that are declared as "bool"
The NBD spec is clear that when structured replies are active, a
simple error reply is acceptable to any command except for
NBD_CMD_READ. However, we were mistakenly requiring structured errors
for NBD_CMD_BLOCK_STATUS, and hanging up on a server that gave a
simple error (since qemu does not
A bit more investigation:
It looks like the bug happens in float->double conversion direction.
$ cat a.c
#include
#include
int main() {
volatile uint32_t i = 1;
volatile float f;
volatile double d;
*(volatile uint32_t*) = i;
d = f;
printf("d = %#llx (expect
Can you provide binaries that reproduce this, please ? Attaching them to
the bug is fine.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1821430
Title:
qemu-user-arm (4.0.0-rc0) crashes
Status in
Emilio G. Cota writes:
> From: Kito Cheng
>
> Before falling back to softfloat FMA, we do not restore the original
> values of inputs A and C. Fix it.
>
> This bug was caught by running gcc's testsuite on RISC-V qemu.
>
> Note that this change gives a small perf increase for fp-bench:
>
>
Richard Henderson writes:
> The second word has been loaded from the unincremented
> address since the first commit.
>
> Fixes: 44ac14b06fa
> Reported-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate-a64.c | 2 +-
> 1 file changed, 1 insertion(+), 1
[adding qemu]
On 3/23/19 6:57 AM, Eric Blake wrote:
> On 3/23/19 6:42 AM, Richard W.M. Jones wrote:
>> nbdkit (upstream 5a7a394c699) currently fails with qemu 2.12.0:
>>
>> $ ./nbdkit memory size=64M --run 'qemu-img convert $nbd /var/tmp/out'
>> nbdkit: memory.2: error: invalid request:
Shorter example without relying on printf() implementation. Looks like
uint32_t<->float<->double transitions are enough.
$ cat a.c
#include
#include
int main() {
volatile uint32_t i = 1;
volatile float f;
volatile double d;
*(volatile uint32_t*) = i;
d = f; f = d; // double
My native system is x86_64-pc-linux-gnu with a few binfmt_misc handlers wired.
Checking other targets I have locally I get the following:
affected targets:
- powerpc
- powerpc64
- powerpc64le
unaffected targets:
- arm
- arm64
- hppa
- sparc
probably unaffected:
- alpha (maybe it's ok as alpha is
Le sam. 23 mars 2019 07:50, Alistair Francis a
écrit :
> On Thu, Mar 21, 2019 at 11:49 PM Peter Maydell
> wrote:
> >
> > Alex and I just noticed that we didn't pick up this
> > MAINTAINERS patch for the "Device Tree" section.
> > In the interim Peter Crosthwaite has also removed himself
> >
Public bug reported:
I'm using qemu-3.1.0 (Gentoo).
When I was running regression test suite via qemu-ppc for GHC I noticed
a few uint32_t<->float32 failures I did not expect to encounter.
Here is an example
$ cat a.c
#include
#include
int main() {
volatile uint32_t i = 1;
On Tue, Mar 19, 2019 at 6:26 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Changes since v2:
> * Several generic tcg patches to improve dup vs dupi vs dupm.
>
> In particular, if a global temp (like guest r10) is not in
> a host register, we should duplicate from memory
Closing this ticket since it was a bug in DPDK, and not in QEMU.
** Changed in: qemu
Status: New => Invalid
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https://bugs.launchpad.net/bugs/1558175
Title:
virtio: vm killed
Can you still reproduce this problem with the latest version of upstream
QEMU?
** Changed in: qemu
Status: New => Incomplete
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https://bugs.launchpad.net/bugs/1562653
Title:
Looking through old bug tickets... can you still reproduce these issues
with the latest version of QEMU?
** Changed in: qemu
Status: New => Incomplete
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On Fri, Mar 15, 2019 at 4:54 AM Markus Armbruster wrote:
>
> Cleaned up with scripts/clean-header-guards.pl.
>
> Signed-off-by: Markus Armbruster
For the RISC-V part:
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/ide/ahci_internal.h | 2 +-
> include/block/aio-wait.h
On Fri, Mar 15, 2019 at 7:16 AM Markus Armbruster wrote:
>
> Philippe Mathieu-Daudé writes:
>
> > On 3/15/19 3:51 PM, Markus Armbruster wrote:
> >> Leading underscores are ill-advised because such identifiers are
> >> reserved. Trailing underscores are merely ugly. Strip both.
> >>
> >> Our
On Fri, Mar 15, 2019 at 6:17 AM Philippe Mathieu-Daudé
wrote:
>
> On 3/15/19 3:51 PM, Markus Armbruster wrote:
> > Reuse of the same guard symbol in multiple headers is okay as long as
> > they cannot be included together. scripts/clean-header-guards.pl
> > can't tell, so it warns.
> >
> > Since
On Thu, Mar 21, 2019 at 11:49 PM Peter Maydell wrote:
>
> Alex and I just noticed that we didn't pick up this
> MAINTAINERS patch for the "Device Tree" section.
> In the interim Peter Crosthwaite has also removed himself
> from maintainership, so by default this will move into
> the "Orphan"
On 22/03/2019 17.30, Andrew Jones wrote:
> In the kconfig shuffle arm lost pci-testdev which is used by
> kvm-unit-tests. Let's add it back.
... the other architectures use "imply TEST_DEVICES" in the Kconfig
files, but since the Kconfig-for-arm patches have not included before
the hard-freeze,
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