On 08/01/2020 12:06, David Gibson wrote:
> On Tue, Jan 07, 2020 at 03:21:42PM +0100, Cédric Le Goater wrote:
>> On 1/7/20 5:48 AM, David Gibson wrote:
>>> The table of RMA limits based on the LPCR[RMLS] field is slightly wrong.
>>> We're missing the RMLS == 0 => 256 GiB RMA option, which is
On 07/01/2020 15:48, David Gibson wrote:
> For the "pseries" machine, we use "virtual hypervisor" mode where we only
> model the CPU in non-hypervisor privileged mode. This means that we need
> guest physical addresses within the modelled within the cpu to be treated
> as absolute physical
void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
{
-int irq = book3s_dbell2irq(rb);
+int irq = book3s_dbell2irq(rb, 1);
>>>
>>> true/false are preferred to 0/1 for bool types.
>>
>> yes or a define ?
>
> Sorry, I don't understand the question. The second
On 09.01.20 03:20, Richard Henderson wrote:
> On 1/9/20 11:05 AM, Philippe Mathieu-Daudé wrote:
>> Philippe Mathieu-Daudé (3):
>> hw/hppa/machine: Correctly check the firmware is in PDC range
>> hw/hppa/machine: Restrict the total memory size to 3GB
>> hw/hppa/machine: Map the PDC memory
Hi Philippe, thanks for replying.
The 'kernel_irqchip' parameter is a bit confusing to me. It looks like
the documentation was updated from it defaulted to 'off' as a -machine
parameter, to now it will default to 'on' as an -accel parameter.
This bug described how the value for
On 09/01/2020 15:07, David Gibson wrote:
> On Wed, Jan 08, 2020 at 03:07:41PM +1100, Alexey Kardashevskiy wrote:
>>
>>
>> On 07/01/2020 16:26, David Gibson wrote:
>>
+static uint32_t client_setprop(SpaprMachineState *sm,
+ uint32_t nodeph,
On Tue, Jan 07, 2020 at 18:00:03 +, Alex Bennée wrote:
> Re-calling the main make is counter-productive and really messes up
> with parallel builds. Just ensure we have built the pre-requisites
> before we build the fp-test bits. If the user builds manually just
> complain if the parent build
Ping.
Pavel Dovgalyuk
> -Original Message-
> From: Pavel Dovgalyuk [mailto:pavel.dovga...@gmail.com]
> Sent: Monday, December 23, 2019 12:46 PM
> To: qemu-devel@nongnu.org
> Cc: kw...@redhat.com; peter.mayd...@linaro.org; crosthwaite.pe...@gmail.com;
> boost.li...@gmail.com;
On Tue, Jan 07, 2020 at 03:01:01PM +0100, Julia Suvorova wrote:
> On Tue, Jan 7, 2020 at 2:06 PM Eryu Guan wrote:
> >
> > On Thu, Jan 02, 2020 at 10:08:50AM +0800, Eryu Guan wrote:
> > > On Tue, Dec 31, 2019 at 11:51:35AM +0100, Igor Mammedov wrote:
> > > > On Tue, 31 Dec 2019 18:34:34 +0800
> >
On Wed, Jan 08, 2020 at 03:07:41PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 07/01/2020 16:26, David Gibson wrote:
>
> >> +static uint32_t client_setprop(SpaprMachineState *sm,
> >> + uint32_t nodeph, uint32_t pname,
> >> +
On Wed, Jan 08, 2020 at 04:53:06PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 08/01/2020 15:20, Alexey Kardashevskiy wrote:
> >
> >
> > On 07/01/2020 16:54, David Gibson wrote:
> >> On Tue, Jan 07, 2020 at 03:44:35PM +1100, Alexey Kardashevskiy wrote:
> >>>
> >>>
> >>> On 06/01/2020 15:19,
On Wed, Jan 08, 2020 at 03:20:22PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 07/01/2020 16:54, David Gibson wrote:
> > On Tue, Jan 07, 2020 at 03:44:35PM +1100, Alexey Kardashevskiy wrote:
> >>
> >>
> >> On 06/01/2020 15:19, David Gibson wrote:
> +
> +static uint32_t
According to the specification "Semihosting for AArch32 and Aarch64",
the SYS_OPEN operation should return:
- A nonzero handle if the call is successful
- -1 if the call is not successful
So, it should never return 0.
Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
code
1. How to enable this feature:
(a) In KVM mode: ./qemu-system-aarch64 --enable-kvm -cpu host --bios
QEMU_EFI.fd_new -machine virt,gic-version=3,ras,kernel-irqchip=on -smp 4
-nographic -kernel Image -append "rdinit=/init console=ttyAMA0 mem=512M
root=/dev/ram0" -initrd guestfs_new.cpio.gz
On 2020/1/8 下午9:53, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
Hyperv's synic (that we emulate) is a feature that allows the guest
to place some magic (4k) pages of RAM anywhere it likes in GPA.
This confuses vhost's RAM section merging when these pages
land over the
There's little point in leaving these data structures half initialized,
and relying on a flush to be done during reset.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index
No functional change, but the smaller expressions make
the code easier to read.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index c7dc1dc85a..eff427f137
Do not call get_clock_realtime() in tlb_mmu_resize_locked,
but hoist outside of any loop over a set of tlbs. This is
only two (indirect) callers, tlb_flush_by_mmuidx_async_work
and tlb_flush_page_locked, so not onerous.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 14
Merge into the only caller, but at the same time split
out tlb_mmu_init to initialize a single tlb entry.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 33 -
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/accel/tcg/cputlb.c
No functional change, but the smaller expressions make
the code easier to read.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index
We will want to be able to flush a tlb without resizing.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index eff427f137..e60e501334 100644
---
We do not need the entire CPUArchState to compute these values.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e4a8ed9534..49c605b6d8 100644
---
I had a conversation with Alistair Francis at KVM forum about
being able to represent ASIDs "properly". This lead to the idea
that target-specific code might be able to cache TLBs outside of
the "main" NB_MMU_MODES -- possibly thousands of them.
This goes nowhere near that far. But it does
There are no users of this function outside cputlb.c,
and its interface will change in the next patch.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 5 -
accel/tcg/cputlb.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git
There is only one caller for tlb_table_flush_by_mmuidx. Place
the result at the earlier line number, due to an expected user
in the near future.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: Thursday, January 09, 2020 12:39 AM
> To: Zengtao (B)
> Cc: Michael S. Tsirkin; qemu-devel@nongnu.org; qemu-triv...@nongnu.org;
> Shannon Zhao; Peter Maydell; qemu-...@nongnu.org
> Subject: Re: [PATCH]
On Mon, 09 Dec 2019 10:12:12 PST (-0800), Alistair Francis wrote:
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 11 +++
On 1/9/20 11:49 AM, Palmer Dabbelt wrote:
>> + irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg &
>> -sie);
>
> Isn't "-unsigned" implementation defined? I can't get GCC to throw a warning
> and it was already there, so maybe I'm just wrong?
(1) You're confusing
On Mon, 09 Dec 2019 10:12:09 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++
target/riscv/csr.c| 25
On Wed, Jan 08, 2020 at 10:03:46AM +0100, Cédric Le Goater wrote:
> Hello,
>
> Here are small cleanups of the PnvPNOR model.
Applied to ppc-for-5.0, thanks.
>
> Thanks,
>
> C.
>
> Cédric Le Goater (2):
> ppc/pnv: use QEMU unit definition MiB
> ppc/pnv: improve error logging when a PNOR
On Mon, 09 Dec 2019 10:12:04 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index
On Mon, 09 Dec 2019 10:12:06 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 43c6629014..aa033b8590 100644
---
On 1/9/20 11:05 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (3):
> hw/hppa/machine: Correctly check the firmware is in PDC range
> hw/hppa/machine: Restrict the total memory size to 3GB
> hw/hppa/machine: Map the PDC memory region with higher priority
Reviewed-by: Richard
The result of g_strsplit is never NULL.
Signed-off-by: Richard Henderson
---
vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index c9329fe699..887dbfbb5d 100644
--- a/vl.c
+++ b/vl.c
@@ -2776,7 +2776,7 @@ static void configure_accelerators(const char
The accel_initialised variable no longer has any setters.
Fixes: 6f6e1698a68c
Signed-off-by: Richard Henderson
---
vl.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index 86474a55c9..be79b03c1a 100644
--- a/vl.c
+++ b/vl.c
@@ -2749,7 +2749,6 @@ static void
Running qemu-system-foo with no options should not generate
a warning for "invalid accelerator bar".
Also, fix some mistakes made while moving the code from accel/accel.c.
r~
Richard Henderson (4):
vl: Remove unused variable in configure_accelerators
vl: Free accel_list in
By choosing "tcg:kvm" when kvm is not enabled, we generate
an incorrect warning: "invalid accelerator kvm".
Presumably the inverse is also true with --disable-tcg.
Fixes: 28a0961757fc
Signed-off-by: Richard Henderson
---
vl.c | 18 --
1 file changed, 12 insertions(+), 6
We allocate the list with g_strsplit, so free it too.
This freeing was lost during one of the rearrangements.
Fixes: 6f6e1698a68c
Signed-off-by: Richard Henderson
---
vl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index be79b03c1a..c9329fe699 100644
---
On Mon, 09 Dec 2019 10:12:01 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 193 ++
2 files changed, 175 insertions(+), 19 deletions(-)
diff --git a/target/riscv/cpu.h
On Thu, Jan 09, 2020 at 12:19:12AM +0530, Ganesh wrote:
>
>
> On 1/8/20 6:34 AM, David Gibson wrote:
> > On Tue, Jan 07, 2020 at 11:57:08AM +0530, Ganesh wrote:
> > > On 1/3/20 7:49 AM, David Gibson wrote:
> > > > On Thu, Jan 02, 2020 at 01:21:09PM +0530, Ganesh Goudar wrote:
> > > > > From:
On Wed, Jan 08, 2020 at 04:32:19PM +0100, Cédric Le Goater wrote:
> On 12/17/19 5:00 AM, David Gibson wrote:
> > On Thu, Nov 28, 2019 at 02:46:58PM +0100, Cédric Le Goater wrote:
> >> From: Suraj Jitindar Singh
> >>
> >> Privileged message send facilities exist on POWER8 processors and
> >> later
On Wed, Jan 08, 2020 at 11:58:45AM +0100, Greg Kurz wrote:
> On Wed, 8 Jan 2020 11:54:53 +1100
> David Gibson wrote:
>
> > On Tue, Jan 07, 2020 at 07:32:03PM +0100, Philippe Mathieu-Daudé wrote:
> > > Hi Greg,
> > >
> > > On 1/7/20 5:32 PM, Greg Kurz wrote:
> > > > The proper way to do that
On Mon, 09 Dec 2019 10:11:59 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
On Mon, 09 Dec 2019 10:11:56 PST (-0800), Alistair Francis wrote:
mark_fs_dirty() is the only place in translate.c that uses the
virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and
HSTATUS.SPRV when setting the bool as this is used for performing
floating point operations when V=0.
On Mon, 09 Dec 2019 10:11:30 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 54edfb280e..d028dfb60b 100644
---
On Mon, 09 Dec 2019 10:11:32 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index
On Mon, 09 Dec 2019 10:11:48 PST (-0800), Alistair Francis wrote:
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.inc.c | 5
On 12/27/19 8:41 AM, Wainer dos Santos Moschetta wrote:
> The `error` and `timeout` attributes in QEMUMonitorProtocol are
> not used, so this delete them.
>
> Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: John Snow
> ---
> python/qemu/qmp.py | 4
> 1 file changed, 4
On 12/27/19 8:41 AM, Wainer dos Santos Moschetta wrote:
> This implement the __enter__ and __exit__ functions on
> QEMUMonitorProtocol class so that it can be used on 'with'
> statement and the resources will be free up on block end:
>
> with QEMUMonitorProtocol(socket_path) as qmp:
>
On 12/27/19 8:40 AM, Wainer dos Santos Moschetta wrote:
> Currently the timeout of QEMUMonitorProtocol.accept() is
> hard-coded to 15 seconds. This added the parameter `timeout`
> so the value can be configured by the user.
>
> Signed-off-by: Wainer dos Santos Moschetta
> ---
>
On 12/27/19 8:40 AM, Wainer dos Santos Moschetta wrote:
> This clean up the pylint-3 report on qmp:
>
> * Module qemu.qmp
> python/qemu/qmp.py:1:0: C0111: Missing module docstring (missing-docstring)
> python/qemu/qmp.py:17:0: C0111: Missing class docstring (missing-docstring)
>
On 12/27/19 8:40 AM, Wainer dos Santos Moschetta wrote:
> The socket.error is deprecated from Python 3.3, instead it is
> made a link to OSError. This change replaces the occurences
> of socket.error with OSError.
>
> Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: John Snow
(Are
The hardware expects DIMM slots of 1 or 2 GB, allowing up to
4 GB of memory. We want to accept the same amount of memory the
hardware can deal with. DIMMs of 768MB are not available.
However we have to deal with a firmware limitation: currently
SeaBIOS only supports 32-bit, and expects the RAM
Following the discussion of Igor's patch "hppa: allow max
ram size upto 4Gb" [1] I tried to simplify the current
code so Igor's series doesn't change the CLI with this
machine.
v2: Simplify by limiting to 3GB (Helge review)
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg667903.html
On Mon, 06 Jan 2020 16:10:28 +0100
Christian Schoenebeck wrote:
> On Montag, 6. Januar 2020 13:30:24 CET Greg Kurz wrote:
> > On Wed, 18 Dec 2019 14:17:59 +0100
> >
> > Christian Schoenebeck wrote:
> > > A good 9p client sends T_readdir with "count" parameter that's
> > > sufficiently smaller
The region in range [0xf000 - 0xf100] is the PDC area
(Processor Dependent Code), where the firmware is loaded.
This region has higher priority than the main memory.
When the machine has more than 3840MB of RAM, there is an
overlap. Since the PDC is closer to the CPU in the bus
hierarchy,
The firmware has to reside in the PDC range. If the Elf file
expects to load it below FIRMWARE_START, it is incorrect,
regardless the RAM size.
Acked-by: Helge Deller
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hppa/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wed, 18 Dec 2019 14:30:43 +0100
Christian Schoenebeck wrote:
> This first readdir test simply checks the amount of directory
> entries returned by 9pfs server, according to the created amount
> of virtual files on 9pfs synth driver side.
>
> Signed-off-by: Christian Schoenebeck
> ---
More
On Wed, Jan 8, 2020 at 10:39 PM Helge Deller wrote:
> On 08.01.20 19:14, Philippe Mathieu-Daudé wrote:
> > The hardware expects DIMM slots of 1 or 2 GB, allowing up to
> > 4 GB of memory. Accept the same amount of memory the hardware
> > can deal with.
> >
> > The CPU doesn't have access to the
The smbios_get_tables() function has access the a machine state.
Use the field instead of accessing the global ram_size variable.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/smbios/smbios.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/smbios/smbios.c
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and
"Ethernet"
various I/O modules. This commit
On Mon, Jan 6, 2020 at 9:23 AM Geert Uytterhoeven wrote:
> > The rest I think we cleared out else I will see it when I review again.
>
> The remaining discussion point is "GPIO Repeater in Device Tree", i.e.
> the GPIO inverter usecase, which might be solved better by adding a
> GPIO_INVERTED
On Thu, 9 Jan 2020 02:22:26 +0530
Kirti Wankhede wrote:
> On 1/8/2020 5:39 AM, Alex Williamson wrote:
> > On Wed, 8 Jan 2020 02:15:01 +0530
> > Kirti Wankhede wrote:
> >
> >> On 12/18/2019 5:42 AM, Alex Williamson wrote:
> >>> On Tue, 17 Dec 2019 22:40:51 +0530
> >>> Kirti Wankhede wrote:
The idea of this is split the build across stages so any failure in
one stage will save time running later stages. So far I have have
arbitrarily chosen:
canary: up-front quick to build and run
platforms: common build configurations
rest: everything else
The ideal should be canary and
On Thu, 9 Jan 2020 02:11:11 +0530
Kirti Wankhede wrote:
> On 1/9/2020 12:01 AM, Alex Williamson wrote:
> > On Wed, 8 Jan 2020 15:59:55 +0100
> > Cornelia Huck wrote:
> >
> >> On Tue, 7 Jan 2020 11:56:02 -0700
> >> Alex Williamson wrote:
> >>
> >>> On Tue, 7 Jan 2020 23:23:17 +0530
> >>>
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other
On 08/01/2020 17:18, Alexey Kardashevskiy wrote:
> The Petitboot bootloader is way more advanced than SLOF is ever going to
> be as Petitboot comes with the full-featured Linux kernel with all
> the drivers, and initramdisk with quite user friendly interface.
> The problem with ditching SLOF is
On Thu, 9 Jan 2020 01:31:16 +0530
Kirti Wankhede wrote:
> On 1/8/2020 3:32 AM, Alex Williamson wrote:
> > On Wed, 8 Jan 2020 01:37:03 +0530
> > Kirti Wankhede wrote:
> >
>
>
>
> +
> +unlocked = vfio_iova_put_vfio_pfn(dma, vpfn, dirty_tracking);
>
>
On 08.01.20 19:14, Philippe Mathieu-Daudé wrote:
> The hardware expects DIMM slots of 1 or 2 GB, allowing up to
> 4 GB of memory. Accept the same amount of memory the hardware
> can deal with.
>
> The CPU doesn't have access to the RAM mapped in the
> [0xf000 - 0xf100] range because this
On 08.01.20 19:14, Philippe Mathieu-Daudé wrote:
> The firmware has to reside in the PDC range. If the Elf file
> expects to load it below FIRMWARE_START, it is incorrect,
> regardless the RAM size.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
> ---
> Note we define
On 1/9/20 6:55 AM, Alex Bennée wrote:
>
> Alex Bennée writes:
>
>> There are linux-user users of semihosting so we'd better check things
>> work for them as well.
>>
>> Signed-off-by: Alex Bennée
>>
>> ---
>> v3
>> - include aarch64 version
>> v4
>> - use common semicall.h, test thumb &
On 1/8/2020 5:39 AM, Alex Williamson wrote:
On Wed, 8 Jan 2020 02:15:01 +0530
Kirti Wankhede wrote:
On 12/18/2019 5:42 AM, Alex Williamson wrote:
On Tue, 17 Dec 2019 22:40:51 +0530
Kirti Wankhede wrote:
This will fail when there are devices within the IOMMU group that are
not
On 1/9/20 2:02 AM, Alex Bennée wrote:
> There are two types of ARM semicall - lets test them both. Putting the
> logic in a header will make re-using the functions easier later.
>
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/arm/semicall.h | 35 +++
>
On 1/9/2020 12:01 AM, Alex Williamson wrote:
On Wed, 8 Jan 2020 15:59:55 +0100
Cornelia Huck wrote:
On Tue, 7 Jan 2020 11:56:02 -0700
Alex Williamson wrote:
On Tue, 7 Jan 2020 23:23:17 +0530
Kirti Wankhede wrote:
There are 3 invalid states:
* 101b => Invalid state
* 110b =>
On Mon, 09 Dec 2019 10:11:27 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fc38c45a7e..54edfb280e 100644
---
in subject: s/usused/unused/
Le 08/01/2020 à 20:24, Thomas Huth a écrit :
> The no_quit variable has been removed in commit 78782712a62d56 ("vl: drop
> no_quit variable"), so let's remove the extern declaration in the header
> now, too.
Fixes: 78782712a62d ("vl: drop no_quit variable")
>
Patchew URL:
https://patchew.org/QEMU/642f73c78a99258dc134e3879a0287db8ef176c0.1578497245.git.tgole...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Sure, I will try to reproduce permissions issue and create a new issue
later. I will try to provide small patches too.
I've created a question on kernel bugzilla.
https://bugzilla.kernel.org/show_bug.cgi?id=206135 They should know that
applications wants much more than "tbl" provides.
** Bug
Thomas Huth writes:
> The no_quit variable has been removed in commit 78782712a62d56 ("vl: drop
> no_quit variable"), so let's remove the extern declaration in the header
> now, too.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Alex Bennée
> ---
> include/sysemu/sysemu.h | 1 -
> 1 file
From: Philippe Mathieu-Daudé
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance"
I have certain concerns over a refactoring that changes the behavior.
Refactorings in general should not do it, and if they still do, one
should at least have a clear explanation. That is why I want more
details on "emerge" problem.
--
You received this bug notification because you are a member
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3
On 1/8/2020 3:32 AM, Alex Williamson wrote:
On Wed, 8 Jan 2020 01:37:03 +0530
Kirti Wankhede wrote:
+
+ unlocked = vfio_iova_put_vfio_pfn(dma, vpfn, dirty_tracking);
if (do_accounting)
vfio_lock_acct(dma, -unlocked, true);
@@ -571,8 +606,12 @@ static int
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 3 +
From: Philippe Mathieu-Daudé
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
*
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
---
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make
Dear QEMU developers,
Hereby I would like to contribute the following set of patches to QEMU
which add support for the Allwinner H3 System on Chip and the
Orange Pi PC machine. The following features and devices are supported:
* SMP (Quad Core Cortex A7)
* Generic Interrupt Controller
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
512MB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
Alex Bennée writes:
> There are linux-user users of semihosting so we'd better check things
> work for them as well.
>
> Signed-off-by: Alex Bennée
>
> ---
> v3
> - include aarch64 version
> v4
> - use common semicall.h, test thumb & arm
> ---
> tests/tcg/arm/semiconsole.c | 27
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