It's a minimalist machine type without PCI nor ACPI support, designed
for short-lived guests. microvm also establishes a baseline for
benchmarking and optimizing both QEMU and guest operating systems,
since it is optimized for both boot time and footprint.
Signed-off-by: Xu Yandong
---
Move fdt and fdt_size member from VirtMachineState to ArmMachineState.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 303 ++
include/hw/arm/arm.h | 2 +
include/hw/arm/virt.h | 2 -
3 files changed, 163 insertions(+), 144 deletions(-)
diff
In the following patches, VirtMachineState and VirtMachineClass will
splited to and deriving ArmMachineState and ArmMachineClass.
This allows sharing code with other arm machine types.
Signed-off-by: Xu Yandong
---
hw/arm/Makefile.objs | 2 +-
hw/arm/arm.c | 77
Move memmap member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 21 +++--
hw/arm/virt.c| 178 ---
include/hw/arm/arm.h | 1 +
Move fdt related functions that will be shared between VIRT and
non-VIRT machine types to arm.c.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 226
hw/arm/virt.c| 238 +--
include/hw/arm/arm.h | 8
Move gic member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 35 ++
hw/arm/virt-acpi-build.c | 8 +--
hw/arm/virt.c| 139
Move device related functions to arm.c, include RTC(pl031), UART(pl011),
virtio devices.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 137 +
hw/arm/virt.c | 156 +++---
include/hw/arm/arm.h | 8 +++
Move bootinfo member from VirtMachineState to ArmMachineState.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 9 +
hw/arm/virt.c | 28 +---
include/hw/arm/arm.h | 3 +++
include/hw/arm/virt.h | 1 -
4 files changed, 21 insertions(+), 20
Move cpu related functions that will be shared between VIRT and
non-VIRT machine types to arm.c.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 89 ++
hw/arm/virt.c | 91 +--
include/hw/arm/arm.h |
Move irqmap member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 8
hw/arm/virt.c| 25 +
include/hw/arm/arm.h | 1 +
Implement Microvm for aarch64 architecture
This series attempts to implement microvm for aarch64
architecture.
Just like how Sergio Lopez does for implementing microvm
for x86 architecture. We remove parts of emulate devices which
are not needed in microvm, compared with normal VM,
We only keep
Move psci_enable member from VirtMachineState to ArmMachineState.
Move claim_edge_triggered_timers member from VirtMachineClass to
ArmMachineClass.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 7 ---
hw/arm/virt.c
Split sharable GIC qdev create and sysbus initiatea codes as independent
function.
Signed-off-by: Xu Yandong
---
hw/arm/arm.c | 106 +++
hw/arm/virt.c| 93 +
include/hw/arm/arm.h | 4 ++
3 files
GICv2m and GICits is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9031fd6757..32c3977e32 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -605,6 +605,15
EL2 extension is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 116 +-
1 file changed, 77 insertions(+), 39 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 32c3977e32..afaf143888 100644
--- a/hw/arm/virt.c
+++
EL3 extension is not always needed.
Signed-off-by: Xu Yandong
---
hw/arm/virt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index afaf143888..087616190e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -627,6 +627,14 @@ static
Move smp_cpus member from VirtMachineState to ArmMachineState.
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Shannon Zhao
Signed-off-by: Xu Yandong
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 12 ++--
include/hw/arm/arm.h | 1 +
include/hw/arm/virt.h|
Hi Howard, could you test out this patch for me on Fedora 31? It is to be
> applied over the v3 patch.
>
> Thank you.
>
> ---
> hw/audio/screamer.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
> index
Kevin Wolf writes:
> This patch adds a new 'coroutine' flag to QMP command definitions that
> tells the QMP dispatcher that the command handler is safe to be run in a
> coroutine.
>
> The documentation of the new flag pretends that this flag is already
> used as intended, which it isn't yet
Maxim Levitsky writes:
> On Sat, 2020-02-15 at 15:51 +0100, Markus Armbruster wrote:
>> Review of this patch led to a lengthy QAPI schema design discussion.
>> Let me try to condense it into a concrete proposal.
>>
>> This is about the QAPI schema, and therefore about QMP. The
>>
Hello,
Philippe Mathieu-Daudé, le lun. 17 févr. 2020 01:44:35 +0100, a ecrit:
> On Sat, Feb 15, 2020 at 10:01 PM Aleksandar Markovic
> wrote:
> > 9:56 PM Sub, 15.02.2020. Philippe Mathieu-Daudé
> > је написао/ла:
> > > On Fri, Feb 14, 2020 at 12:04 AM Aleksandar Markovic
> > > wrote:
> > > >
On 2/15/2020 11:35 AM, Daniel Cho wrote:
Hi Dave,
Yes, I agree with you, it does need a timeout.
Hi Daniel and Dave,
Current colo-compare already have the timeout mechanism.
Named packet_check_timer, It will scan primary packet queue to make
sure all the primary packet not stay too long
From: Pan Nengyuan
There are some memleaks when we call 'device_list_properties'. This patch move
timer_new from init into realize to fix it.
Meanwhile, do the null check in mos6522_reset() to avoid null deref if we move
timer_new into realize().
Reported-by: Euler Robot
Signed-off-by: Pan
From: Pan Nengyuan
This patch fix memleaks when we call tests/qtest/cpu-plug-test on s390x. The
leak stack is as follow:
Direct leak of 48 byte(s) in 1 object(s) allocated from:
#0 0x7fb43c7cd970 in __interceptor_calloc (/lib64/libasan.so.5+0xef970)
#1 0x7fb43be2149d in g_malloc0
From: Pan Nengyuan
v1:
- Delay timer_new() from init() to realize() to fix memleaks.
v2:
- Similarly to other cleanups, move timer_new into realize in
target/s390x/cpu.c (Suggested by Philippe Mathieu-Daudé).
- Send these two patches as a series instead of sending each as a single
Fix posted:
http://patchwork.ozlabs.org/patch/1238946/
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https://bugs.launchpad.net/bugs/1863508
Title:
qemu-system-arm stops with SIGSEGV in helper_gvec_eq16
Status in QEMU:
In
Patchew URL:
https://patchew.org/QEMU/20200217025957.12031-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/4] tcg: Fix for Bug 1863508
Message-id:
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the DUP* expansions with the scalar argument.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 50 +++-
1 file changed, 15 insertions(+), 35 deletions(-)
diff --git
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the vec* types with their scalar expansions.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 270 +--
1 file changed, 130 insertions(+), 140 deletions(-)
diff --git
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of 8-
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace DO_CMP0 with its scalar expansion, a simple negation.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime-gvec.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c
Hi Marc,
On 2/16/20 11:34 PM, Marc Zyngier wrote:
On 2020-02-14 05:59, Gavin Shan wrote:
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter Maydell
suggested, this adds a new interrupt (ARM_CPU_SERROR), which
While other targets take advantage of using host FPU to do floating
point computations, this was disabled for PPC target because always
clearing exception flags before every FP op made it slightly slower
than emulating everyting with softfloat. To emulate some FPSCR bits,
clearing of fp_status may
Add a property to allow setting a flag in cpu env that will be used to
control if hardfloat is used for floating point ops (i.e. speed is
preferred over accuracy).
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h| 2 ++
target/ppc/translate_init.inc.c | 2 ++
2 files changed,
Hello,
This is an RFC series to start exploring the possibility of enabling
hardfloat for PPC target that haven't progressed in the last two years.
Hopefully we can work out something now. Previously I've explored this
here:
https://lists.nongnu.org/archive/html/qemu-ppc/2018-07/msg00261.html
On Mon, Feb 17, 2020 at 01:12:17PM +1100, Alexey Kardashevskiy wrote:
> The following changes since commit 05943fb4ca41f626078014c0327781815c6584c5:
>
> ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
>
> are available in the Git repository at:
>
>
The following changes since commit 05943fb4ca41f626078014c0327781815c6584c5:
ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
are available in the Git repository at:
g...@github.com:aik/qemu.git tags/qemu-slof-20200217
for you to fetch changes up to
Patchew URL:
https://patchew.org/QEMU/20200217012737.30231-1-gengdong...@huawei.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
On 17/02/2020 12:27, Alexey Kardashevskiy wrote:
> Hi!
>
> We have a SLOF repo mirrored at git.qemu.org. Once I push an update to
> my github repo, it gets mirrored soon, it works fine.
>
> Now to the problems :)
>
> 1. by accident I pushed a branch with a lot of debug stuff on top. When
> I
Hi!
We have a SLOF repo mirrored at git.qemu.org. Once I push an update to
my github repo, it gets mirrored soon, it works fine.
Now to the problems :)
1. by accident I pushed a branch with a lot of debug stuff on top. When
I noticed, I force-pushed the correct one but it was too late - the
Hi Daniel,
I have rebased these patches with newest upstream version, this series
“Optimize VM's downtime while do checkpoint in COLO”,
It is not been tested, please let me known if there are any problems.
Thanks,
Hailiang
From: Daniel Cho [mailto:daniel...@qnap.com]
Sent: Saturday, February
kvm_arch_on_sigbus_vcpu() error injection uses source_id as
index in etc/hardware_errors to find out Error Status Data
Block entry corresponding to error source. So supported source_id
values should be assigned here and not be changed afterwards to
make sure that guest will write error into
I and Xiang are willing to review the APEI-related patches and
volunteer as the reviewers for the HEST/GHES part.
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
---
MAINTAINERS | 9 +
1 file changed, 9
Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.
When guest accesses the poisoned memory, it will generate a Synchronous
This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs.
Now it only supports ARMv8 SEA, a type of Generic Hardware Error
Source version 2(GHESv2) error source. Afterwards, we can extend
the supported types if needed. For the CPER section, currently it
is memory section because kernel
Record the GHEB address via fw_cfg file, when recording
a error to CPER, it will use this address to find out
Generic Error Data Entries and write the error.
In order to avoid migration failure, make hardware
error table address to a part of GED device instead
of global variable, then this
This patch builds error_block_address and read_ack_register fields
in hardware errors table , the error_block_address points to Generic
Error Status Block(GESB) via bios_linker. The max size for one GESB
is 1kb in bytes, For more detailed information, please refer to
document:
Add APEI/GHES detailed design document
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Igor Mammedov
---
docs/specs/acpi_hest_ghes.rst | 110 ++
docs/specs/index.rst | 1 +
2 files changed,
RAS Virtualization feature is not supported now, so add a RAS machine
option and disable it by default.
Reviewed-by: Peter Maydell
Signed-off-by: Dongjiu Geng
Signed-off-by: Xiang Zheng
Reviewed-by: Jonathan Cameron
---
hw/arm/virt.c | 23 +++
The little end UUID is used in many places, so make
NVDIMM_UUID_LE to a common macro to convert the UUID
to a little end array.
Signed-off-by: Dongjiu Geng
Reviewed-by: Xiang Zheng
---
hw/acpi/nvdimm.c| 8 ++--
include/qemu/uuid.h | 5 +
2 files changed, 7 insertions(+), 6
kvm_hwpoison_page_add() and kvm_unpoison_all() will both
be used by X86 and ARM platforms, so moving them into
"accel/kvm/kvm-all.c" to avoid duplicate code.
For architectures that don't use the poison-list functionality
the reset handler will harmlessly do nothing, so let's register
the
In the ARMv8 platform, the CPU error types includes synchronous external
abort(SEA)
and SError Interrupt (SEI). If exception happens in guest, host does not know
the
detailed information of guest, so it is expected that guest can do the recovery.
For example, if an exception happens in a guest
We can migrate some dirty pages during the gap of checkpointing,
by this way, we can reduce the amount of ram migrated during checkpointing.
Signed-off-by: Hailiang Zhang
---
migration/colo.c | 69 +++---
migration/migration.h | 1 +
Hi,
This is an untested serial that tries to reduce VM's pause time
while do checkpoint in COLO state.
The second patch tries to reduce the total number of dirty pages
while do checkpoint with VM been paused, instead of sending all
dirty pages while VM been pause, it sends part of dirty pages
This patch will reduce the downtime of VM for the initial process,
Privously, we copied all these memory in preparing stage of COLO
while we need to stop VM, which is a time-consuming process.
Here we optimize it by a trick, back-up every page while in migration
process while COLO is enabled,
Split checkpoint incoming process into a helper.
Signed-off-by: Hailiang Zhang
---
migration/colo.c | 260 ---
1 file changed, 133 insertions(+), 127 deletions(-)
diff --git a/migration/colo.c b/migration/colo.c
index 2c88aa57a2..93c5a452fb 100644
> On Feb 16, 2020, at 2:57 PM, Howard Spoelstra wrote:
>
>
>
>
> On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
> wrote:
> Signed-off-by: John Arbuckle
> ---
> v3 changes:
> - Updated the location of patched code in hw/ppc/kconfig.
> - Removed setting the props variable in screamer.c.
> -
> On Feb 16, 2020, at 4:59 PM, BALATON Zoltan wrote:
>
> On Sun, 16 Feb 2020, Howard Spoelstra wrote:
>> On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
>> wrote:
>>> diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
>>> new file mode 100644
>>> index 00..ad4aba12eb
>>> ---
On Sat, Feb 15, 2020 at 10:01 PM Aleksandar Markovic
wrote:
> 9:56 PM Sub, 15.02.2020. Philippe Mathieu-Daudé
> је написао/ла:
> > On Fri, Feb 14, 2020 at 12:04 AM Aleksandar Markovic
> > wrote:
> > >
> > > 6:59 PM Čet, 13.02.2020. Peter Maydell је
> > > написао/ла:
> > > >
> > > > The
On Sun, Feb 16, 2020 at 8:27 PM Aleksandar Markovic
wrote:
>
> 5:23 PM Sub, 15.02.2020. Philippe Mathieu-Daudé је
> написао/ла:
> >
> > User-mode does not need the sytem tools. Do not build them by
> > default if user specified --disable-system.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
>
On Sat, Feb 15, 2020 at 09:30:56AM +0800, Pan Nengyuan wrote:
>
>
> On 2/14/2020 11:48 PM, Greg Kurz wrote:
> > On Fri, 14 Feb 2020 11:32:06 +0800
> > wrote:
> >
> >> From: Pan Nengyuan
> >>
> >> 'fdt' forgot to clean both e500 and pnv when we call 'system_reset' on ppc,
> >> this patch fix
On Fri, Feb 14, 2020 at 04:01:16PM +0100, Greg Kurz wrote:
> While working on getting rid of CAS reboot, I realized that we currently
> don't handle device hot unplug properly in the following situations:
>
> 1) if the device is unplugged between boot and CAS, SLOF doesn't handle
>the even,
I infer from the traceback that your host does not support AVX1.
** Changed in: qemu
Status: Incomplete => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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** Changed in: qemu
Status: New => Incomplete
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https://bugs.launchpad.net/bugs/1863508
Title:
qemu-system-arm stops with SIGSEGV in helper_gvec_eq16
Status in QEMU:
In
On 2/16/20 2:41 PM, Richard Henderson wrote:
On 2/13/20 9:59 PM, Gavin Shan wrote:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b0762a76c4..180e29fb83 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -78,7 +78,7 @@ static bool arm_cpu_has_work(CPUState *cs)
&&
Public bug reported:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data
0xf0 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data
0xf0 size 4
I am not sure this register can not be accessed differently than 32-bit.
Still I used this patch as a kludge, but it doesn't seem a clean fix:
-- >8 --
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2160,6 +2161,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
On Sun, Feb 16, 2020 at 05:33:44PM +0100, Aleksandar Markovic wrote:
> OK, I will add the patch in the next MIPS queue, since I think its
> significance is more than trivial. It will be sent no later than two weeks
> from now.
Thanks Aleksandar.
> I just wanted the patch to be in the same queue
On Sun, Feb 16, 2020 at 10:33:54PM +0100, BALATON Zoltan wrote:
> Just some small clean ups to improve readability of struct CPUPPCState.
Applied to ppc-for-5.0, thanks.
> BALATON Zoltan (2):
> target/ppc/cpu.h: Move fpu related members closer in cpu env
> target/ppc/cpu.h: Clean up comments
Patchew URL:
https://patchew.org/QEMU/20200216214232.4230-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 0/4] target/arm vector improvements
Message-id:
On Sun, 16 Feb 2020, Howard Spoelstra wrote:
On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
wrote:
diff --git a/hw/audio/screamer.c b/hw/audio/screamer.c
new file mode 100644
index 00..ad4aba12eb
--- /dev/null
+++ b/hw/audio/screamer.c
@@ -0,0 +1,983 @@
+/*
+ * File: Screamer.c
+ *
On Fri, Feb 14, 2020 at 09:08:09PM +0100, Kevin Wolf wrote:
commit_populate() is a very short function and only called in a single
place. Its return value doesn't tell us whether an error happened while
reading or writing, which would be necessary for sending the right data
in the
On Fri, Feb 14, 2020 at 09:08:11PM +0100, Kevin Wolf wrote:
Now that the error handling in the common block job is fixed, we can
expose the on-error option in QMP instead of hard-coding it as 'report'
in qmp_block_commit().
This fulfills the promise that the old comment in that function made,
On Fri, Feb 14, 2020 at 09:08:10PM +0100, Kevin Wolf wrote:
block_job_error_action() needs to know if reading from the top node or
writing to the base node failed so that it can set the right 'operation'
in the BLOCK_JOB_ERROR QMP event.
Signed-off-by: Kevin Wolf
---
block/commit.c | 7 ++-
On Fri, Feb 14, 2020 at 09:08:06PM +0100, Kevin Wolf wrote:
It is not obvious what 'ignore' actually means for block jobs: It could
be continuing the job and returning success in the end despite the error
(no block job does this). It could also mean continuing and returning
failure in the end
On Fri, Feb 14, 2020 at 09:08:07PM +0100, Kevin Wolf wrote:
The bytes_written variable is only ever written to, it serves no
purpose. This has actually been the case since the commit job was first
introduced in commit 747ff602636.
Signed-off-by: Kevin Wolf
---
block/commit.c | 2 --
1 file
On Fri, Feb 14, 2020 at 09:08:08PM +0100, Kevin Wolf wrote:
The block_job_error_action() error call in the commit job gives the
on_err and is_read arguments in the wrong order. Fix this.
(Of course, hard-coded is_read = false is wrong, too, but that's a
separate problem for a separate patch.)
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustrate why the neon changes
The gvec form will be needed for implementing SVE2.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 4 +---
target/arm/neon_helper.c | 30 --
target/arm/translate-a64.c | 28
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit
Changes for v2:
* Rename function arguments as requested by ajb.
* Minor optimization in helper_gvec_pmul_b.
Original blurb:
The first patch has been seen before.
https://patchwork.ozlabs.org/patch/1115039/
It had a bug and I didn't fix it right away and then forgot.
Fixed now; I had mixed
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Tested-by: Alex Bennée
Reviewed-by: Alex
Just some small clean ups to improve readability of struct CPUPPCState.
BALATON Zoltan (2):
target/ppc/cpu.h: Move fpu related members closer in cpu env
target/ppc/cpu.h: Clean up comments in the struct CPUPPCState
definition
target/ppc/cpu.h | 146
The cpu env struct is quite complex but comments supposed to explain
it in its definition just make it harder to read. Reformat and reword
some comments to make it clearer and more readable.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h | 145 ++-
Move fp_status and fpscr closer to other floating point and vector
related members in cpu env definition so they are in one group.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
On Sat, Feb 15, 2020 at 05:07:16PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/fuse_lowlevel.o
tools/virtiofsd/fuse_lowlevel.c:195:9: warning: Value stored to 'error' is
never read
error = -ERANGE;
^
On Sat, Feb 15, 2020 at 05:07:15PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:925:9: warning: Value stored to 'newfd' is
never read
newfd = -1;
^
On Sat, Feb 15, 2020 at 05:07:14PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/passthrough_ll.o
tools/virtiofsd/passthrough_ll.c:1083:5: warning: Value stored to 'saverr' is
never read
saverr = ENOMEM;
^
On Wed, 12 Feb 2020 at 17:30, Palmer Dabbelt wrote:
>
> The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-02-10 17:08:51 +)
>
> are available in the Git repository
On Sat, Feb 15, 2020 at 05:15:55PM +0100, Philippe Mathieu-Daudé wrote:
Fix warning reported by Clang static code analyzer:
CC block/qcow2-bitmap.o
block/qcow2-bitmap.c:650:5: warning: Value stored to 'ret' is never read
ret = -EINVAL;
^ ~~~
Reported-by: Clang Static
On Sun, 16 Feb 2020 at 19:43, Richard Henderson
wrote:
>
> The psuedocode in aarch64/functions/pac/auth/Auth and
> aarch64/functions/pac/strip/Strip always uses bit 55 for
> extfield and do not consider if the current regime has 2 ranges.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Richard
On Sun, Feb 16, 2020 at 5:32 PM John Arbuckle
wrote:
> Signed-off-by: John Arbuckle
> ---
> v3 changes:
> - Updated the location of patched code in hw/ppc/kconfig.
> - Removed setting the props variable in screamer.c.
> - Removed the screamer_properties variable in screamer.c.
>
> v2 changes:
>
Select should always be 0 for a regime with one range.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 46 +++--
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c
Now that aa64_va_parameters_both sets select based on the number
of ranges in the regime, the ttbr1_valid check is redundant.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/arm/helper.c
Something I noticed while developing and testing VHE.
For v2, fix select as a separate patch.
For v3, adjust pauth to use bit 55 explicitly, and remove a
now duplicate test within get_phys_addr_lpae.
r~
Richard Henderson (4):
target/arm: Use bit 55 explicitly for pauth
target/arm: Fix
For the purpose of rebuild_hflags_a64, we do not need to compute
all of the va parameters, only tbi. Moreover, we can compute them
in a form that is more useful to storing in hflags.
This eliminates the need for aa64_va_parameter_both, so fold that
in to aa64_va_parameter. The remaining calls
The psuedocode in aarch64/functions/pac/auth/Auth and
aarch64/functions/pac/strip/Strip always uses bit 55 for
extfield and do not consider if the current regime has 2 ranges.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/pauth_helper.c | 3 ++-
1 file changed, 2
On Sat, Feb 15, 2020 at 04:47:05PM +0100, Philippe Mathieu-Daudé wrote:
> In commit f3a508eb4e the Euler Robot reported calling timer_new()
> in instance_init() can leak heap memory. The easier fix is to
> delay the timer creation at instance realize(). Similarly move
> timer_del() into a new
Public bug reported:
Segmentation fault when trying to start FreeBSD-arm system with qemu-
system-arm (version 4.1.1 on Fedora 31)
Commandline:
gdb -q --args /bin/qemu-system-arm \
-name FreeBSD12,debug-threads=on \
-m 1536 -machine virt -smp 2 \
-M virt,highmem=off -serial mon:stdio -monitor
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