Re: [PATCH 2/2] hw/sd/sd: Delay timer_new_ns() from init to realize to avoid memleaks

On 2/17/20 2:26 PM, Peter Maydell wrote: > On Sat, 15 Feb 2020 at 15:48, Philippe Mathieu-Daudé > wrote: >> >> In commit f3a508eb4e the Euler Robot reported calling timer_new() >> in instance_init() can leak heap memory. The easier fix is to >> delay the timer creation at instance realize().

Re: [PATCH v8 4/4] new qTest case to test the vhost-user-blk-server

On 05/06/2020 01.35, Coiby Xu wrote: > This test case has the same tests as tests/virtio-blk-test.c except for > tests have block_resize. Since vhost-user server can only server one > client one time, two instances of qemu-storage-daemon are launched > for the hotplug test. > > In order to not

[PATCH v2 17/17] tests/tcg/aarch64: Add mte smoke tests

Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 54 +++ tests/tcg/aarch64/mte-1.c | 25 ++ tests/tcg/aarch64/mte-2.c | 42 tests/tcg/aarch64/mte-3.c | 47 +++

[PATCH v2 16/17] target/arm: Enable MTE for user-only

Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 + 1 file changed, 17 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37b7cc2c9c..6395918524 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,6 +39,7 @@ #include "kvm_arm.h" #include

[PATCH v2 15/17] target/arm: Add allocation tag storage for user mode

Use the now-saved PAGE_ANON and PAGE_TARGET_2 bits, and the per-page saved data. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c

[PATCH v2 11/17] linux-user/aarch64: Implement PROT_MTE

Remember the PROT_MTE bit as PAGE_TARGET_2. Otherwise this does not yet have effect. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h| 1 + linux-user/syscall_defs.h | 1 + linux-user/mmap.c | 20 3 files changed, 14 insertions(+), 8 deletions(-)

[PATCH v2 14/17] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 34 +- target/arm/mte_helper.c| 10 + 3 files changed, 35 insertions(+), 10 deletions(-) diff --git

[PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG

These prctl fields are required for the function of MTE. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 9 ++ linux-user/syscall.c| 46 + 2 files changed, 55 insertions(+) diff --git

[PATCH v2 08/17] exec: Add support for TARGET_TAGGED_ADDRESSES

The AArch64 Linux ABI has always enabled TBI, but has historically required that pointer tags be removed before a syscall. This has changed in the lead-up to ARMv8.5-MTE, in a way that affects the ABI generically and not specifically to MTE. This patch allows the target to indicate that (1)

[PATCH v2 13/17] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index ddd73169f0..777fb667fe 100644 ---

[PATCH v2 09/17] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE

This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 4 linux-user/syscall.c| 23 +++

[PATCH v2 06/17] linux-user: Do not use guest_addr_valid for h2g_valid

This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the

[PATCH v2 07/17] linux-user: Fix guest_addr_valid vs reserved_va

We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu_ldst.h

[PATCH v2 05/17] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE

These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/bsd-user/qemu.h

[PATCH v2 04/17] linux-user: Tidy VERIFY_READ/VERIFY_WRITE

These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Signed-off-by: Richard Henderson --- linux-user/qemu.h | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git

[PATCH v2 12/17] linux-user/aarch64: Pass syndrome to EXC_*_ABORT

A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 23 --- target/arm/tlb_helper.c | 27 +--

[PATCH v2 02/17] linux-user: Introduce PAGE_ANON

Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We

[PATCH v2 03/17] linux-user: Check for overflow in access_ok

Verify that addr + size - 1 does not wrap around. Signed-off-by: Richard Henderson --- linux-user/qemu.h | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index d36b18b678..2bf35e66ac 100644 --- a/linux-user/qemu.h +++

[PATCH v2 00/17] target-arm: Implement ARMv8.5-MemTag, user mode

Version 1 was back in October: https://patchew.org/QEMU/20191015163254.12041-1-richard.hender...@linaro.org/ Although that post claims there was an actual v1 in March 2019, I can't locate it, so... whatever. This version -- call it 2 -- is the first attempt to implement the actual in-progress

[PATCH v2 01/17] tcg: Introduce target-specific page data for user-only

This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h| 20 ++-- accel/tcg/translate-all.c |

[Bug 1805256] Re: qemu-img hangs on rcu_call_ready_event logic in Aarch64 when converting images

I've looked and retried the tests - all green now. Let us give it a few extra days in proposed as planned, but other than that it looks ok to be released. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 6/4/20 7:50 PM, LIU Zhiwei wrote: > So no scalar insns will require changes within a translation block. Not true -- scalar insns can encode rm into the instruction. > I think there is a error in gen_set_rm > > static void gen_set_rm(DisasContext *ctx, int rm) > { >     TCGv_i32 t0; > >    

Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions

On 2020/6/5 4:51, Richard Henderson wrote: On 5/21/20 2:43 AM, LIU Zhiwei wrote: +static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) Return bool, better than uint8_t. Yes. +{ +int compare = float16_compare_quiet(a, b, s); New since your last revision is that

Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions

On 2020/6/5 5:32, Richard Henderson wrote: On 5/21/20 2:44 AM, LIU Zhiwei wrote: +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) +{ +if (!s->vill && has_ext(s, RVF) && +(s->mstatus_fs != 0) && (s->sew != 0)) { +unsigned int ofs = (8 << s->sew); +

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 2020/6/5 4:15, Richard Henderson wrote: On 6/2/20 10:46 PM, LIU Zhiwei wrote: I think you are right.  Maybe I should transmit frm to ctx->frm, and check ctx->frm in vector fp ops. We can set ctx->frm = env->frm instead of ctx->frm = -1 in riscv_tr_init_disas_context. And  remove the

[Bug 1882123] Re: ARM cpu emulation regression on QEMU 4.2.0

I have tested 4.2.0 release candidate versions to pinpoint which commit caused the regression. - 4.2.0-rc2: Same with 4.2.0, dotnet command crashes with SEHException. - 4.2.0-rc0, 4.2.0-rc1: Launching dotnet command with any argument crashes with illegal hardware instruction message. $ dotnet

Re: [PATCH 1/2] Introduce (x86) CPU model deprecation API

On Thu, 2020-06-04 at 06:59 -0500, Eric Blake wrote: > On 6/4/20 3:07 AM, Robert Hoo wrote: > > > > > +++ b/qapi/machine-target.json > > > > @@ -309,7 +309,8 @@ > > > >'static': 'bool', > > > >'*unavailable-features': [ 'str' ], > > > >'typename':

Re: hw/char: a question about watch callback function in serial

On 2020/6/4 21:32, Peter Maydell wrote: On Thu, 4 Jun 2020 at 13:15, LIU Zhiwei wrote: I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s->watch_tag = qemu_chr_fe_add_watch(>chr, G_IO_OUT

Re: [PATCH v3] migration/xbzrle: add encoding rate

On 06/05/2020 12:57 AM, Richard Henderson wrote: On 6/4/20 3:27 AM, Wei Wang wrote: On 06/04/2020 05:38 PM, Dr. David Alan Gilbert wrote: Hmm OK; I'll admit to not liking NaN/Inf in output. Dave OK. To deal with the reported issue, how about using FLT_MAX (as opposed to UINT64_MAX or inf):

Re: [PATCH 3/3] numa: Initialize node initiator with respect to .has_cpu

On 6/3/20 5:16 PM, Michal Privoznik wrote: On 6/2/20 10:00 AM, Tao Xu wrote: On 6/1/2020 4:10 PM, Michal Privoznik wrote: On 5/29/20 5:09 PM, Igor Mammedov wrote: On Fri, 29 May 2020 15:33:48 +0200 Michal Privoznik wrote: The initiator attribute of a NUMA node is documented as the 'NUMA

[PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 6 +++ target/riscv/helper.h | 1 + target/riscv/csr.c | 64 - target/riscv/insn_trans/trans_rvh.inc.c | 2 +- target/riscv/op_helper.c|

[PATCH v2 14/17] target/riscv: Only support little endian guests

Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 973404d0aa..5b64539efb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -772,6 +772,8 @@ static int read_hstatus(CPURISCVState

[PATCH v2 10/17] target/riscv: Fix the interrupt cause code

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3b1a2f75ca..4ea39d5641 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@

[PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 5 +++-- target/riscv/cpu_helper.c | 20 target/riscv/csr.c| 6 +++--- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[PATCH v7] linux-user: syscall: ioctls: support DRM_IOCTL_VERSION

From: Chen Gang Another DRM_IOCTL_* commands will be done later. Signed-off-by: Chen Gang --- configure | 10 linux-user/ioctls.h| 5 ++ linux-user/syscall.c | 98 ++ linux-user/syscall_defs.h | 15 ++

[PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 40 2 files changed, 43 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8a145e0a32..690f327828 100644 ---

[PATCH v2 13/17] target/riscv: Only support a single VSXL length

Signed-off-by: Alistair Francis --- target/riscv/csr.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 69a3c8379c..973404d0aa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -768,12 +768,21 @@ static int

[PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst

Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 383be0a955..53665b0985 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -854,7 +854,6 @@ static int read_htinst(CPURISCVState *env,

[PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses

When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis --- target/riscv/csr.c | 46 target/riscv/op_helper.c |

[PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 54 +++ 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 68abccc993..1521c14b72 100644 --- a/target/riscv/cpu_helper.c

[PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/insn_trans/trans_rvh.inc.c | 340

[PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status

Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 80569f0d44..93ae472490 100644 ---

[PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6b97c27711..8a145e0a32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@

[PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry

Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 8 +--- target/riscv/op_helper.c | 8 ++-- target/riscv/translate.c | 10 -- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu_bits.h

[PATCH v2 02/17] target/riscv: Report errors validating 2nd-stage PTEs

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index eda7057663..75d2ae3434 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@

[PATCH v2 01/17] target/riscv: Set access as data_load when validating stage-2 PTEs

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62fe1ecc8f..eda7057663 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -435,7

[PATCH v2 04/17] target/riscv: Implement checks for hfence

Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5

[PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1

From: Alistair Francis This series updates the experimental QEMU RISC-V Hypervisor spec to the v0.6.1 draft implementation. THis includes support for the new 2-stage lookup instructions and the new CSRs. It also includes the new 0.6.1 support for the virtual instruction fault. This was tested

[PATCH v2 03/17] target/riscv: Move the hfence instructions to the rvh decode

Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis --- target/riscv/insn32.decode| 8 ++- .../riscv/insn_trans/trans_privileged.inc.c | 38 - target/riscv/insn_trans/trans_rvh.inc.c | 57 +++

Re: [PATCH v4 2/3] hw/acpi/nvdimm: add a helper to augment SRAT generation

On Thu, 2020-06-04 at 12:33 +0200, Igor Mammedov wrote: > On Thu, 28 May 2020 16:34:36 -0600 > Vishal Verma wrote: > > > NVDIMMs can belong to their own proximity domains, as described by the > > NFIT. In such cases, the SRAT needs to have Memory Affinity structures > > in the SRAT for these

Re: [RFC v2 00/18] Refactor configuration of guest memory protection

On 05/06/20 01:30, Thiago Jung Bauermann wrote: > Paolo Bonzini writes: >> On 04/06/20 23:54, Thiago Jung Bauermann wrote: >>> QEMU could always create a PEF object, and if the command line defines >>> one, it will correspond to it. And if the command line doesn't define one, >>> then it would

[PATCH v8 4/4] new qTest case to test the vhost-user-blk-server

This test case has the same tests as tests/virtio-blk-test.c except for tests have block_resize. Since vhost-user server can only server one client one time, two instances of qemu-storage-daemon are launched for the hotplug test. In order to not block scripts/tap-driver.pl, vhost-user-blk-server

[PATCH v8 3/4] vhost-user block device backend server

By making use of libvhost-user, block device drive can be shared to the connected vhost-user client. Only one client can connect to the server one time. Since vhost-user-server needs a block drive to be created first, delay the creation of this object. Signed-off-by: Coiby Xu ---

[PATCH v8 2/4] generic vhost user server

Sharing QEMU devices via vhost-user protocol. Only one vhost-user client can connect to the server one time. Signed-off-by: Coiby Xu --- util/Makefile.objs | 1 + util/vhost-user-server.c | 406 +++ util/vhost-user-server.h | 59 ++ 3 files

[PATCH v8 1/4] Allow vu_message_read to be replaced

Allow vu_message_read to be replaced by one which will make use of the QIOChannel functions. Thus reading vhost-user message won't stall the guest. Signed-off-by: Coiby Xu --- contrib/libvhost-user/libvhost-user-glib.c | 2 +- contrib/libvhost-user/libvhost-user.c | 11 ++-

[PATCH v8 0/4] vhost-user block device backend implementation

v8 - re-try connecting to socket server to fix asan error - fix license naming issue v7 - fix docker-test-debug@fedora errors by freeing malloced memory v6 - add missing license header and include guard - vhost-user server only serve one client one time - fix a bug in custom

Re: [RFC v2 00/18] Refactor configuration of guest memory protection

Paolo Bonzini writes: > On 04/06/20 23:54, Thiago Jung Bauermann wrote: >> QEMU could always create a PEF object, and if the command line defines >> one, it will correspond to it. And if the command line doesn't define one, >> then it would also work because the PEF object is already there. >

[PATCH] docker: update Ubuntu to 20.04

Signed-off-by: Paolo Bonzini --- tests/docker/dockerfiles/ubuntu.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/dockerfiles/ubuntu.docker b/tests/docker/dockerfiles/ubuntu.docker index eeb3b22bf2..43872417de 100644 ---

Re: [RFC v2 00/18] Refactor configuration of guest memory protection

On 04/06/20 23:54, Thiago Jung Bauermann wrote: > QEMU could always create a PEF object, and if the command line defines > one, it will correspond to it. And if the command line doesn't define one, > then it would also work because the PEF object is already there. How would you start a

[PATCH] linux-headers: update to Linux 5.8-rc1

Signed-off-by: Paolo Bonzini --- include/standard-headers/asm-x86/kvm_para.h | 17 ++- include/standard-headers/drm/drm_fourcc.h | 140 ++-- include/standard-headers/linux/ethtool.h| 16 ++- linux-headers/asm-arm/unistd-common.h | 1 +

Re: [PATCH v4] osdep: Make MIN/MAX evaluate arguments only once

On 6/4/20 2:52 PM, Eric Blake wrote: > I'm not aware of any immediate bugs in qemu where a second runtime > evalution of the arguments to MIN() or MAX() causes a problem, but > proactively preventing such abuse is easier than falling prey to an > unintended case down the road. At any rate, here's

Re: [PATCH v4] osdep: Make MIN/MAX evaluate arguments only once

On 6/4/20 4:52 PM, Eric Blake wrote: I'm not aware of any immediate bugs in qemu where a second runtime evalution of the arguments to MIN() or MAX() causes a problem, but evaluation proactively preventing such abuse is easier than falling prey to an unintended case down the road. At any

Re: [RFC v2 00/18] Refactor configuration of guest memory protection

David Gibson writes: > On Thu, Jun 04, 2020 at 01:39:22AM -0300, Thiago Jung Bauermann wrote: >> >> Hello David, >> >> David Gibson writes: >> >> > A number of hardware platforms are implementing mechanisms whereby the >> > hypervisor does not have unfettered access to guest memory, in

[PATCH v4] osdep: Make MIN/MAX evaluate arguments only once

I'm not aware of any immediate bugs in qemu where a second runtime evalution of the arguments to MIN() or MAX() causes a problem, but proactively preventing such abuse is easier than falling prey to an unintended case down the road. At any rate, here's the conversation that sparked the current

[PATCH] pflash: cfi02: Convert debug log to tracing

When trying to track down problems such as failing unlock sequences it is essential to have a complete trace log. Having part of it as debug output and the rest as trace output is counter-productive. Convert all debug logs to tracing. Signed-off-by: Guenter Roeck --- hw/block/pflash_cfi02.c |

Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions

On 5/21/20 2:44 AM, LIU Zhiwei wrote: > +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > +{ > +if (!s->vill && has_ext(s, RVF) && > +(s->mstatus_fs != 0) && (s->sew != 0)) { > +unsigned int ofs = (8 << s->sew); > +unsigned int len = 64 - ofs; > +

Re: [PATCH v8 56/62] target/riscv: integer extract instruction

On 5/21/20 2:44 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > --- > target/riscv/insn32.decode | 1 + > target/riscv/insn_trans/trans_rvv.inc.c | 116 > 2 files changed, 117 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH v8 42/62] target/riscv: vector floating-point merge instructions

On 5/21/20 2:43 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > --- > target/riscv/helper.h | 4 +++ > target/riscv/insn32.decode | 2 ++ > target/riscv/insn_trans/trans_rvv.inc.c | 38 + > target/riscv/vector_helper.c| 24

Re: [PATCH v13 1/5] i386: Add support for CPUID_8000_001E for AMD

On Thu, Jun 04, 2020 at 09:06:27AM -0500, Babu Moger wrote: > > > > -Original Message- > > From: Eduardo Habkost > > Sent: Tuesday, June 2, 2020 12:52 PM > > To: Moger, Babu > > Cc: m...@redhat.com; marcel.apfelb...@gmail.com; pbonz...@redhat.com; > > r...@twiddle.net;

Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions

On 5/21/20 2:43 AM, LIU Zhiwei wrote: > +static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) Return bool, better than uint8_t. > +{ > +int compare = float16_compare_quiet(a, b, s); New since your last revision is that compare should be type FloatRelation. And similarly

[V2][PATCH 1/1] lockable: use QLNULL for a null lockable

Allows us to build with -Og and optimizations that do not clean up dead-code. If we use QLNULL for null lockables, we can always use referencing unknown_lock_type as a link time error indicator. Signed-off-by: Joe Slater --- include/qemu/lockable.h| 20

[PATCH v3 16/16] python/qemu: Add mypy type annotations

These should all be purely annotations with no changes in behavior at all. You need to be in the python folder, but you should be able to confirm that these annotations are correct (or at least self-consistent) by running `mypy --strict qemu`. Signed-off-by: John Snow --- python/qemu/accel.py

[PATCH v3 15/16] iotests.py: Adjust HMP kwargs typing

mypy wants to ensure there's consistency between the kwargs arguments types and any unspecified keyword arguments. In this case, conv_keys is a bool, but the remaining keys are Any type. Mypy (correctly) infers the **kwargs type to be **Dict[str, str], which is not compatible with conv_keys: bool.

Re: [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation

On 5/21/20 2:43 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > Reviewed-by: Alistair Francis > --- > target/riscv/helper.h | 9 ++ > target/riscv/insn32.decode | 2 + > target/riscv/insn_trans/trans_rvv.inc.c | 4 + > target/riscv/vector_helper.c

[PATCH v3 10/16] python/machine.py: Handle None events in events_wait

If the timeout is 0, we can get None back. Handle this explicitly. Signed-off-by: John Snow --- python/qemu/machine.py | 27 --- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/python/qemu/machine.py b/python/qemu/machine.py index 92528a44097..4afd67a9351

[PATCH v3 12/16] python/machine.py: Add _qmp access shim

Like many other Optional[] types, it's not always a given that this object will be set. Wrap it in a type-shim that raises a meaningful error and will always return a concrete type. Signed-off-by: John Snow --- python/qemu/machine.py | 12 +--- 1 file changed, 9 insertions(+), 3

[PATCH v3 14/16] python/qemu: make 'args' style arguments immutable

These arguments don't need to be mutable and aren't really used as such. Clarify their types as immutable and adjust code to match where necessary. In general, It's probably best not to accept a user-defined mutable object and store it as internal object state unless there's a strong

[PATCH v3 02/16] iotests.py: use qemu.qmp type aliases

iotests.py should use the type definitions from qmp.py instead of its own. Signed-off-by: John Snow --- tests/qemu-iotests/iotests.py | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index

[PATCH v3 13/16] python/machine.py: fix _popen access

As always, Optional[T] causes problems with unchecked access. Add a helper that asserts the pipe is present before we attempt to talk with it. Signed-off-by: John Snow --- python/qemu/machine.py | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git

[PATCH v3 01/16] python/qmp.py: Define common types

Define some common types that we'll need to annotate a lot of other functions going forward. Signed-off-by: John Snow --- python/qemu/qmp.py | 18 ++ 1 file changed, 18 insertions(+) diff --git a/python/qemu/qmp.py b/python/qemu/qmp.py index e64b6b5faa7..8388c7b6030 100644 ---

[PATCH v3 03/16] python/qmp.py: re-absorb MonitorResponseError

When I initially split this out, I considered this more of a machine error than a QMP protocol error, but I think that's misguided. Move this back to qmp.py and name it QMPResponseError. Convert qmp.command() to use this exception type. Signed-off-by: John Snow Reviewed-by: Philippe

[PATCH v3 08/16] python/machine.py: reorder __init__

Put the init arg handling all at the top, and mostly in order (deviating when one is dependent on another), and put what is effectively runtime state declaration at the bottom. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé --- python/qemu/machine.py | 29

[PATCH v3 06/16] python/qmp.py: add QMPProtocolError

In the case that we receive a reply but are unable to understand it, use this exception name to indicate that case. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé --- python/qemu/qmp.py | 10 ++ 1 file changed, 10 insertions(+) diff --git a/python/qemu/qmp.py

[PATCH v3 11/16] python/machine.py: use qmp.command

machine.py and qmp.py both do the same thing here; refactor machine.py to use qmp.py's functionality more directly. Signed-off-by: John Snow --- python/qemu/machine.py | 26 +++--- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/python/qemu/machine.py

[PATCH v3 04/16] python/qmp.py: Do not return None from cmd_obj

This makes typing the qmp library difficult, as it necessitates wrapping Optional[] around the type for every return type up the stack. At some point, it becomes difficult to discern or remember why it's None instead of the expected object. Use the python exception system to tell us exactly why

[PATCH v3 07/16] python/machine.py: Fix monitor address typing

Prior to this, it's difficult for mypy to intuit what the concrete type of the monitor address is; it has difficulty inferring the type across two variables. Create _monitor_address as a property that always returns a valid address to simply static type analysis. To preserve our ability to clean

[PATCH v3 09/16] python/machine.py: Don't modify state in _base_args()

Don't append to the _remove_files list during _base_args; instead do so during _launch. Rework _base_args as a @property to help facilitate this impression. This has the additional benefit of making the type of _console_address easier to analyze statically. Signed-off-by: John Snow ---

[PATCH v3 05/16] python/qmp.py: add casts to JSON deserialization

mypy and python type hints are not powerful enough to properly describe JSON messages in Python 3.6. The best we can do, generally, is describe them as Dict[str, Any]. Add casts to coerce this type for static analysis; but do NOT enforce this type at runtime in any way. Note: Python 3.8 adds a

Re: [PATCH v8 25/62] target/riscv: vector single-width averaging add and subtract

On 5/21/20 2:43 AM, LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > Reviewed-by: Alistair Francis > --- > target/riscv/helper.h | 17 > target/riscv/insn32.decode | 5 ++ > target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ > target/riscv/vector_helper.c

[PATCH v3 00/16] python: add mypy support to python/qemu

Based-on: 20200604195252.20739-1-js...@redhat.com This series is extracted from my larger series that attempted to bundle our python module as an installable module. These fixes don't require that, so they are being sent first as I think there's less up for debate in here. This requires my

Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes

On 6/2/20 10:46 PM, LIU Zhiwei wrote: > I think you are right.  Maybe I should transmit frm to ctx->frm, and check > ctx->frm in vector fp ops. > > We can set ctx->frm = env->frm instead of ctx->frm = -1 in > riscv_tr_init_disas_context. > And  remove the sentence ctx->frm = rm; from gen_set_rm.

[PATCH v3 2/3] python/machine.py: refactor shutdown

This is done primarily to avoid the 'bare except' pattern, which suppresses ALL exceptions and not just ones that we are anticipating to see. Replace this with a pattern that isolates the different kind of shutdown paradigms and a new fallback shutdown handler that gracefully attempts one before

[PATCH v3 1/3] python/machine.py: consolidate _post_shutdown()

Move more cleanup actions into _post_shutdown. As a change, if QEMU should so happen to be terminated during a call to wait(), that event will now be logged. This is not likely to occur during normative use. Signed-off-by: John Snow --- python/qemu/machine.py | 27 +--

Re: [PATCH] checkpatch: reversed logic with acpi test checks

On Thu, 4 Jun 2020 at 20:09, Michael S. Tsirkin wrote: > On Thu, Jun 04, 2020 at 08:45:15PM +0200, Paolo Bonzini wrote: > > On 02/06/20 07:36, Michael S. Tsirkin wrote: > > > + } elsif (not $name =~ > > > m#^tests/qtest/bios-tables-test-allowed-diff.h$#) { > > >

[PATCH v3 3/3] python/machine.py: re-add sigkill warning suppression

If the user kills QEMU on purpose, we don't need to warn them about that having happened: they know already. Signed-off-by: John Snow --- python/qemu/machine.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/python/qemu/machine.py b/python/qemu/machine.py index

[PATCH v3 0/3] python/machine.py: refactor shutdown

v3: - Split _post_shutdown refactor into own patch (now 1/3) - Re-add sigkill warning squelch (now 3/3) NOTE: I re-added the squelch in its own patch for review purposes, but for the purposes of avoiding temporary breakage, a maintainer may wish to squash patches 2 and 3 if they are accepted.

Re: [PATCH v4 00/12] iotests: Dump QCOW2 dirty bitmaps metadata

Patchew URL: https://patchew.org/QEMU/20200604174135.11042-1-vsement...@virtuozzo.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20200604174135.11042-1-vsement...@virtuozzo.com Subject: [PATCH v4 00/12] iotests: Dump QCOW2

Re: [PATCH] checkpatch: reversed logic with acpi test checks

On Thu, Jun 04, 2020 at 08:45:15PM +0200, Paolo Bonzini wrote: > On 02/06/20 07:36, Michael S. Tsirkin wrote: > > Logic reversed: allowed list should just be ignored. Instead we > > only take that into account :( > > > > Fixes: e11b06a880ca ("checkpatch: ignore allowed diff list") > >

Re: [PATCH v2 1/1] python/machine.py: refactor shutdown

On 6/4/20 8:39 AM, Kevin Wolf wrote: > Am 02.06.2020 um 21:48 hat John Snow geschrieben: >> This is done primarily to avoid the 'bare except' pattern, which >> suppresses ALL exceptions and not just ones that we are anticipating to >> see. >> >> Replace this with a pattern that isolates the

Re: [PATCH] replay: fix replay shutdown for console mode

On 22/05/20 08:45, Pavel Dovgalyuk wrote: > When QEMU is used without any graphical window, > QEMU execution is terminated with the signal (e.g., Ctrl-C). > Signal processing in QEMU does not include > qemu_system_shutdown_request call. That is why shutdown > event is not recorded by record/replay

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