On 7/6/20 12:15 AM, Klaus Jensen wrote:
> On Jul 2 16:33, Andrzej Jakowski wrote:
>> On 7/2/20 10:51 AM, Klaus Jensen wrote:
>>> On Jul 2 08:07, Andrzej Jakowski wrote:
On 7/2/20 3:31 AM, Klaus Jensen wrote:
> Aight, an update here. This only happens when QEMU is run with a virtual
On Tue, Jul 07, 2020 at 06:35:57PM +0200, Greg Kurz wrote:
> QEMU aborts with -device pnv-psi-POWER8:
>
> $ qemu-system-ppc64 -device pnv-psi-POWER8
> qemu-system-ppc64: hw/intc/xics.c:605: ics_realize: Assertion
> `ics->xics' failed.
> Aborted (core dumped)
>
> The Processor Service Interface
Hi Alistair,
On Wed, Jul 8, 2020 at 1:33 AM Alistair Francis wrote:
>
> On Thu, Jul 2, 2020 at 6:25 PM Bin Meng wrote:
> >
> > On Wed, Jul 1, 2020 at 4:23 AM Alistair Francis
> > wrote:
> > >
> > > When a guest specificies the the rounding mode should be dynamic 0b111
> > > then we want to
On Fri, 2020-07-03 at 05:05 -0400, Michael S. Tsirkin wrote:
> From: Cindy Lu
>
> Currently we have 2 types of vhost backends in QEMU: vhost kernel and
> vhost-user. The above patch provides a generic device for vDPA
> purpose,
> this vDPA device exposes to user space a non-vendor-specific
>
Hello Eduardo,
Eduardo Habkost writes:
> On Tue, Jul 07, 2020 at 05:43:33PM -0300, Thiago Jung Bauermann wrote:
>> PowerPC sPAPRs CPUs start in the halted state, but generic QEMU code
>> assumes that CPUs start in the non-halted state. spapr_reset_vcpu()
>> attempts to rectify this by setting
On Thu, Jul 2, 2020 at 8:20 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Update the install blob list to include the generic platform
> fw_dynamic bios images.
>
> Signed-off-by: Bin Meng
Shouldn't this patch be included in an earlier patch?
Otherwise won't this break `make install` bisection?
On Thu, Jul 2, 2020 at 8:19 PM Bin Meng wrote:
>
> From: Bin Meng
>
> This updates the GitLab CI opensbi job to build opensbi bios images
> for the generic platform.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v3:
> -
On Tue, Jul 7, 2020 at 12:21 PM Alex Bennée wrote:
> Well it ran some xtensa tests thanks to the docker cross compiler
> support. Do you know what toolchains we need?
>
> Currently we have the following:
>
> ENV CPU_LIST csp dc232b dc233c
> ENV TOOLCHAIN_RELEASE 2018.02
>
> RUN for cpu in
On Tuesday, July 7, 2020, Paolo Bonzini wrote:
> I haven't looked at the disassembler code; assuming it comes from an
> upstream code base I don't think we should treat it differently from the
> ARM disassembler (or for that matter the binutils ones) and basically
> handle it as a black box for
Hi Richard,
Ping for other patches in this patch set.
I may not get you ideas. Could you give more information?
Zhiwei
On 2020/7/3 20:33, LIU Zhiwei wrote:
On 2020/7/3 1:37, Richard Henderson wrote:
On 6/26/20 1:59 PM, LIU Zhiwei wrote:
Multiple precison shoule be supported by NaN-boxing.
On Thu, Jul 2, 2020 at 8:22 PM Bin Meng wrote:
>
> From: Bin Meng
>
> The RISC-V generic platform is a flattened device tree (FDT) based
> platform where all platform specific functionality is provided based
> on FDT passed by previous booting stage. The support was added in
> the upstream
On 2020/6/18 12:25, Richard Henderson wrote:
I know this patch set is too big, and that there are parts that
can be split out that are prepatory rather that specifically sve2.
It's also not 100% tested. I have done some amount of testing
vs ArmIE, but because of bugs and missing features
Signed-off-by: Mark Cave-Ayland
---
pc-bios/openbios-ppc | Bin 696912 -> 696912 bytes
pc-bios/openbios-sparc32 | Bin 382048 -> 382048 bytes
pc-bios/openbios-sparc64 | Bin 1593408 -> 1593408 bytes
roms/openbios| 2 +-
4 files changed, 1 insertion(+), 1 deletion(-)
diff --git
-20200707
for you to fetch changes up to 1e04092feecfc8caaf314df2670bf9c645a0b122:
Update OpenBIOS images to 75fbb41d built from submodule. (2020-07-07 21:54:37
+0100)
qemu-openbios queue
I haven't looked at the disassembler code; assuming it comes from an
upstream code base I don't think we should treat it differently from the
ARM disassembler (or for that matter the binutils ones) and basically
handle it as a black box for which we don't really care about the code
quality or
PowerPC sPAPRs CPUs start in the halted state, but generic QEMU code
assumes that CPUs start in the non-halted state. spapr_reset_vcpu()
attempts to rectify this by setting CPUState::halted to 1. But that's too
late for hotplugged CPUs in a machine configured with 2 or mor threads per
core.
By
Am 2020-07-07 18:30, schrieb Peter Maydell:
On Sun, 5 Jul 2020 at 22:10, Philippe Mathieu-Daudé
wrote:
The 'card is readonly' and 'card inserted' IRQs are not wired.
Add a comment in case someone know where to wire them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lm32/milkymist.c | 1 +
Vladimir Sementsov-Ogievskiy writes:
> 07.07.2020 19:50, Markus Armbruster wrote:
>> From: Vladimir Sementsov-Ogievskiy
>>
>> Introduce a new ERRP_AUTO_PROPAGATE macro, to be used at start of
>> functions with an errp OUT parameter.
>>
>> It has three goals:
>>
>> 1. Fix issue with error_fatal
On Mon, 6 Jul 2020 at 11:04, Max Reitz wrote:
>
> The following changes since commit eb6490f544388dd24c0d054a96dd304bc7284450:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200703' into staging (2020-07-04
> 16:08:41 +0100)
>
> are available in the Git repository
Hi Philippe,
Just tried out your patch on latest master, and I noticed I couldn't apply
it without getting this error:
$ git am ~/Downloads/patches/\[PATCH\ 2_2\]\ hw_sd_sdcard\:\ Do\ not\
allow\ invalid\ SD\ card\ sizes\ -\ Philippe\ Mathieu-Daudé\ \<
f4...@amsat.org\>\ -\ 2020-07-07\ 1521.eml
On Tue, Jul 7, 2020 at 12:57 AM Gerd Hoffmann wrote:
> Hi,
> >
> > Gerd, do you know the purpose of the 'short_not_ok' parameter to
> > usb_packet_setup()?
>
> Well, some usb host controllers have a flag in the transfer control
> blocks to indicate the host controller should stop processing
On 07/07/2020 18.40, Aleksandar Markovic wrote:
> The following changes since commit 710fb08fd297d7a92163debce1959fae8f3b6ed7:
>
> Merge remote-tracking branch
> 'remotes/huth-gitlab/tags/pull-request-2020-07-06' into staging (2020-07-07
> 12:41:15 +0100)
>
> are available in the git
The TPM 2 code in libtpms was fixed to handle the PCR 'TCB group' according
to the PCClient profile. The change of the PCRs belonging to the 'TCB group'
now affects the pcrUpdateCounter in the TPM2_PCRRead() responses where its
value is now different (typically lower by '1') than what it was
This series of patches fixes the TPM SPAPR device model so that it reacts
in the same way as the other device models do when the backend device did
not start up properly. It now calls exit(1).
Due to a change in the TPM 2 code, the pcrUpdateCounter (14th byte) in the
TPM2_Pcrread response now
Exit on TPM backend failures in the same way as the TPM CRB and TIS device
models do. With this change we now get an error report when the backend
did not start up properly:
error: internal error: qemu unexpectedly closed the monitor:
2020-07-07T12:49:28.333928Z qemu-system-ppc64: tpm-emulator: \
Eric Blake writes:
> On 7/7/20 11:50 AM, Markus Armbruster wrote:
>> From: Vladimir Sementsov-Ogievskiy
>>
>> Script adds ERRP_AUTO_PROPAGATE macro invocation where appropriate and
>> does corresponding changes in code (look for details in
>> include/qapi/error.h)
>>
>> Usage example:
>> spatch
07.07.2020 19:50, Markus Armbruster wrote:
From: Vladimir Sementsov-Ogievskiy
Introduce a new ERRP_AUTO_PROPAGATE macro, to be used at start of
functions with an errp OUT parameter.
It has three goals:
1. Fix issue with error_fatal and error_prepend/error_append_hint: user
can't see this
Eric Blake writes:
> On 7/7/20 11:50 AM, Markus Armbruster wrote:
>> From: Vladimir Sementsov-Ogievskiy
>>
>> Introduce a new ERRP_AUTO_PROPAGATE macro, to be used at start of
>> functions with an errp OUT parameter.
>>
>> It has three goals:
>>
>> 1. Fix issue with error_fatal and
On 7/7/20 11:07 AM, Kevin Wolf wrote:
Am 06.07.2020 um 22:39 hat Eric Blake geschrieben:
There are many existing qcow2 images that specify a backing file but
no format. This has been the source of CVEs in the past, but has
become more prominent of a problem now that libvirt has switched to
On Tue, Jul 07, 2020 at 04:03:10PM +0800, Jason Wang wrote:
>
> On 2020/7/3 下午9:03, Peter Xu wrote:
> > On Fri, Jul 03, 2020 at 03:24:19PM +0800, Jason Wang wrote:
> > > On 2020/7/2 下午11:45, Peter Xu wrote:
> > > > On Thu, Jul 02, 2020 at 11:01:54AM +0800, Jason Wang wrote:
> > > > > So I think
On 7/7/20 2:23 PM, Markus Armbruster wrote:
It helps that you have repeated the same pattern as above. But that
means if you change the layout, both groupings should have the same
layout. Maybe:
Intro for a task:
- when the function returns...
- when it doesn't
Also, are there functions
On Tue, 7 Jul 2020 18:05:38 +0200
Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> Reviewed-by: Eric Blake
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> ---
Reviewed-by: Greg Kurz
> util/qemu-option.c | 18 +-
> 1 file changed, 5 insertions(+), 13
On 7/7/20 11:50 AM, Markus Armbruster wrote:
From: Vladimir Sementsov-Ogievskiy
If we want to add some info to errp (by error_prepend() or
error_append_hint()), we must use the ERRP_AUTO_PROPAGATE macro.
Otherwise, this info will not be added when errp == _fatal
(the program will exit prior to
On Tue, 7 Jul 2020 18:05:30 +0200
Markus Armbruster wrote:
> Add headlines to the big comment.
>
> Explain examples for NULL, _abort and _fatal argument
> better.
>
> Tweak rationale for error_propagate_prepend().
>
> Signed-off-by: Markus Armbruster
> ---
Reviewed-by: Greg Kurz
>
On 7/7/20 11:50 AM, Markus Armbruster wrote:
From: Vladimir Sementsov-Ogievskiy
Script adds ERRP_AUTO_PROPAGATE macro invocation where appropriate and
does corresponding changes in code (look for details in
include/qapi/error.h)
Usage example:
spatch --sp-file
Eric Blake writes:
> On 7/7/20 11:05 AM, Markus Armbruster wrote:
>> This merely codifies existing practice, with one exception: the rule
>> advising against returning void, where existing practice is mixed.
>>
>> When the Error API was created, we adopted the (unwritten) rule to
>> return void
Max Filippov writes:
> On Tue, Jul 7, 2020 at 4:31 AM Alex Bennée wrote:
>> I've only looked at the softfloat bits as I'm not familiar with xtensa
>
> Thanks for taking a look!
>
>> at all. However you can have a vague:
>>
>> Tested-by: Alex Bennée
>>
>> for the series - congratulations you
Max Filippov writes:
> target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU
> implementations with and without the corresponding property. With
> NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU
> executable.
> Replace macro with new property in float_status to
On Sun, Jul 5, 2020 at 10:40 AM BALATON Zoltan wrote:
>
> Several callers of load_elf() pass pointers for lowaddr and highaddr
> parameters which are then not used for anything. This may stem from a
> misunderstanding that load_elf need a value here but in fact it can
> take NULL to ignore these
On Jul 7 19:27, Maxim Levitsky wrote:
> On Wed, 2020-07-01 at 14:48 -0700, Andrzej Jakowski wrote:
> > This patch sets CMBS bit in controller capabilities register when user
> > configures NVMe driver with CMB support, so capabilites are correctly
> > reported to guest OS.
> >
> > Signed-off-by:
On 7/7/20 11:50 AM, Markus Armbruster wrote:
From: Vladimir Sementsov-Ogievskiy
Introduce a new ERRP_AUTO_PROPAGATE macro, to be used at start of
functions with an errp OUT parameter.
It has three goals:
1. Fix issue with error_fatal and error_prepend/error_append_hint: user
the user
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: c8eaf81f (
https://gitlab.com/qemu-project/qemu/-/commit/c8eaf81fd22638691c5bdcc7d723d31fbb80ff6f
)
Commit Message: Merge
On 7/7/20 11:50 AM, Markus Armbruster wrote:
To speed things up, I'm taking the liberty to respin Vladimir's series
with my documentation amendments.
After my documentation work, I'm very much inclined to rename
ERRP_AUTO_PROPAGATE() to ERRP_GUARD(). The fact that it propagates
below the hood
Il mar 7 lug 2020, 20:42 Peter Maydell ha
scritto:
> Also it broke my working tree, in the sense that when I
> rolled back to current master incremental-rebuild didn't
> work but instead failed with:
>
> make: *** No rule to make target '/home/ubuntu/qemu/Kconfig', needed
> by
07.07.2020 19:50, Markus Armbruster wrote:
To speed things up, I'm taking the liberty to respin Vladimir's series
with my documentation amendments.
Thank you!
After my documentation work, I'm very much inclined to rename
ERRP_AUTO_PROPAGATE() to ERRP_GUARD(). The fact that it propagates
This implements a device model for the NPCM7xx SPI flash controller.
Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.
All the FIU instances are available in the SoC's address space,
regardless of whether or not
On Tue, 7 Jul 2020, Alistair Francis wrote:
On Sun, Jul 5, 2020 at 10:41 AM BALATON Zoltan wrote:
Several callers of load_elf() pass pointers for lowaddr and highaddr
parameters which are then not used for anything. This may stem from a
misunderstanding that load_elf need a value here but in
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx.c| 10 +
hw/mem/Makefile.objs| 1 +
hw/mem/npcm7xx_mc.c | 84
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 92 +
docs/system/target-arm.rst | 1 +
2 files changed, 93 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
diff --git
If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.
A minimal Apache-2.0-licensed boot ROM can be found at
https://github.com/google/vbootrom
It is by no means feature complete,
This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:
IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
-bios ~/qemu/bootrom/npcm7xx_bootrom.bin \
-drive
The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).
This
The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).
Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is
This adds two new machines, both supported by OpenBMC:
- npcm750-evb: Nuvoton NPCM750 Evaluation Board.
- quanta-gsj: A board with a NPCM730 chip.
They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which
Add a config symbol for the NPCM7xx BMC SoC family that subsequent
patches can use in Makefiles.
Reviewed-by: Tyrone Ting
Acked-by: Joel Stanley
Signed-off-by: Havard Skinnemoen
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Kconfig | 8
2 files changed, 9
Enough functionality to boot the Linux kernel has been implemented. This
includes:
- Correct power-on reset values so the various clock rates can be
accurately calculated.
- Clock enables stick around when written.
In addition, a best effort attempt to implement SECCNT and CNTR25M was
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx.c | 32 +++
hw/nvram/Makefile.objs | 1 +
hw/nvram/npcm7xx_otp.c
Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.
This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.
The reset values of the MDLR
On 7/7/20 8:45 PM, Laurent Vivier wrote:
> From: "Daniel P. Berrange"
>
> When QEMU sets up a tap based network device backend, it mostly ignores errors
> reported from various ioctl() calls it makes, assuming the TAP file descriptor
> is valid. This assumption can easily be violated when the
I also pushed this and the previous two patchsets to my qemu fork on github.
The branches are named npcm7xx-v[1-4].
https://github.com/hskinnemoen/qemu
This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to boot
an OpenBMC image built for quanta-gsj. This includes device
On 7/7/20 11:05 AM, Markus Armbruster wrote:
This merely codifies existing practice, with one exception: the rule
advising against returning void, where existing practice is mixed.
When the Error API was created, we adopted the (unwritten) rule to
return void when the function returns no useful
qemu_set_nonblock() checks that the file descriptor can be used and, if
not, crashes QEMU. An assert() is used for that. The use of assert() is
used to detect programming error and the coredump will allow to debug
the problem.
But in the case of the tap device, this assert() can be triggered by
a
v4: use qemu_try_set_nonblock() with vhostfd in net_init_tap_one(),
and with fd in net_init_socket()
v3: move qemu_fd_is_valid() checking into a new function
qemu_try_set_nonblock(), and use qemu_try_set_nonblock() in
qemu_set_nonblock().
v2: Add patch from Daniel to check the fd can
From: "Daniel P. Berrange"
When QEMU sets up a tap based network device backend, it mostly ignores errors
reported from various ioctl() calls it makes, assuming the TAP file descriptor
is valid. This assumption can easily be violated when the user is passing in a
pre-opened file descriptor. At
On Tue, 7 Jul 2020 at 19:37, Peter Maydell wrote:
>
> On Mon, 6 Jul 2020 at 17:48, Paolo Bonzini wrote:
> >
> > The following changes since commit fc1bff958998910ec8d25db86cd2f53ff125f7ab:
> >
> > hw/misc/pca9552: Add missing TypeInfo::class_size field (2020-06-29
> > 21:16:10 +0100)
> >
> >
On 7/7/20 11:05 AM, Markus Armbruster wrote:
Add headlines to the big comment.
Explain examples for NULL, _abort and _fatal argument
better.
Tweak rationale for error_propagate_prepend().
Signed-off-by: Markus Armbruster
---
include/qapi/error.h | 51
On Mon, 6 Jul 2020 at 17:48, Paolo Bonzini wrote:
>
> The following changes since commit fc1bff958998910ec8d25db86cd2f53ff125f7ab:
>
> hw/misc/pca9552: Add missing TypeInfo::class_size field (2020-06-29
> 21:16:10 +0100)
>
> are available in the Git repository at:
>
>
On 7/7/20 11:05 AM, Markus Armbruster wrote:
Mark a bad example more clearly. Fix the error_propagate_prepend()
example. Add a missing declaration and a second error pileup example.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
On Sun, 5 Jul 2020 at 21:46, Philippe Mathieu-Daudé wrote:
>
> The 'card is readonly' and 'card inserted' IRQs are not wired.
> Add a comment in case someone know where to wire them.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/versatilepb.c | 2 ++
> 1 file changed, 2 insertions(+)
Patchew URL:
https://patchew.org/QEMU/1594140062-23522-1-git-send-email-aleksandar.qemu.de...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1594140062-23522-1-git-send-email-aleksandar.qemu.de...@gmail.com
$PC is 16-bit wide. Other registers display addresses on a byte
granularity.
To have a coherent ouput, display $PC using byte granularity too.
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
From: Thomas Huth
The new section explains basic ways of using AVR target in QEMU.
Signed-off-by: Michael Rolnik
[thuth: Converted doc from texi to Sphinx syntax]
Signed-off-by: Thomas Huth
Message-Id: <20200705140315.260514-31-h...@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé
---
Since commit 1f5c00cfdb tlb_flush() is called from cpu_common_reset().
Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200707070021.10031-2-f4...@amsat.org>
---
target/avr/cpu.c | 2 --
1 file changed, 2
From: Michael Rolnik
This is a simple device of just one register, and whenever this
register is written to it calls qemu_set_irq function for each
of 8 bits/IRQs. It is used to implement AVR Power Reduction.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by:
While LOAD instructions use the target register as first
argument, STORE instructions use it as second argument:
LD Rd, X// Rd <- (X)
ST Y, Rd// (Y) <- Rr
Reported-by: Joaquin de Andres
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:
From: Michael Rolnik
Print out 'T' through serial port.
The Arduino Duemilanove is based on a AVR5 CPU, while the
Arduino MEGA2560 on a AVR6 CPU.
Signed-off-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
[rth: Squash Arduino adjustments from f4bug]
Tested-by: Richard Henderson
Add some AVR microcontrollers from the ATmega family:
- middle range: ATmega168 and ATmega328
- high range: ATmega1280 and ATmega2560
For product comparison:
https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM:
Add avr_load_firmware() function to load firmware in ELF or
raw binary format.
[AM: Corrected the type of the variable containing e_flags]
[AM: Moved definition of e_flags conversion function to boot.c]
Suggested-by: Aleksandar Markovic
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by:
From: Michael Rolnik
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Signed-off-by: Thomas Huth
Message-Id:
Arduino boards are build with AVR chipsets. Add some of these
boards:
- Arduino Duemilanove
- Arduino Uno
- Arduino Mega
For more information:
https://www.arduino.cc/en/Main/Products
https://store.arduino.cc/arduino-genuino/most-popular
[AM: Remove word 'Atmel' from filenames and all
From: Michael Rolnik
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
Signed-off-by:
From: Michael Rolnik
Add AVR related definitions into QEMU, make AVR support buildable.
[AM: Remove word 'Atmel' from filenames and all elements of code]
Suggested-by: Aleksandar Markovic
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
From: Michael Rolnik
These were designed to facilitate testing but should provide enough
function to be useful in other contexts. Only a subset of the functions
of each peripheral is implemented, mainly due to the lack of a standard
way to handle electrical connections (like GPIO pins).
[AM:
From: Michael Rolnik
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Michael Rolnik
Provide function disassembles executed instruction when '-d in_asm' is
provided.
Example:
$ qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf -d in_asm
...
IN:
0x014a: CALL 0x3808
IN: main
0x3808: CALL 0x4b4
IN:
From: Michael Rolnik
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
As the path name demonstrates, the FreeRTOS tests target a
From: Michael Rolnik
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by:
From: Michael Rolnik
Add helpers for instructions that need to interact with QEMU. Also,
add stubs for unimplemented instructions. Instructions SPM and WDR
are left unimplemented because they require emulation of complex
peripherals. The implementation of instruction SLEEP is very limited
due to
From: Michael Rolnik
Add the core of translation mechanism.
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar
From: Michael Rolnik
Add a single code line that will automatically provide
'machine none' test.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Reviewed-by: Thomas Huth
From: Michael Rolnik
Start implementation of instructions by adding register definitions.
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Michael Rolnik
This patch introduces enumeration "AVRFeature" that will be
used for defining various AVR core types.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Michael Rolnik
AVR core types are:
- avr5
- avr51
- avr6
Each core type covers multiple AVR MCUs, mentioned in the comments
before definition of particular AVR core type (part of this patch).
AVR core type defines shared features that are valid for all AVR
MCUs belonging in that
From: Michael Rolnik
Initialize TCG register variables.
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
From: Michael Rolnik
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Signed-off-by: Richard Henderson
Signed-off-by: Aleksandar Markovic
From: Michael Rolnik
This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Michael Rolnik
This patch introduces three memory-management-related functions
that will become part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
From: Michael Rolnik
This patch introduces functions avr_cpu_do_interrupt() and
avr_cpu_exec_interrupt() that are part of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by:
From: Michael Rolnik
Add migration-related functions of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah
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