On 19/04/2021 21.27, Klaus Jensen wrote:
From: Klaus Jensen
Get rid of the (reserved) double underscore use.
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 47 +++
1 file changed, 23 insertions(+),
On 19/04/2021 21.27, Klaus Jensen wrote:
From: Klaus Jensen
Get rid of the (reserved) double underscore use.
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On 19/04/2021 21.27, Klaus Jensen wrote:
From: Klaus Jensen
Get rid of the (reserved) double underscore use.
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
I think it
Result @blocked is true when and only when result @blocked-reasons is
present. It's always non-empty when present. @blocked is redundant.
It was introduced in commit 3af8554bd0 "migration: Add blocker
information", and has not been released. This gives us a chance to
fix the interface with
Result @blocked is true when and only when result @blocked-reasons is
present. It's always non-empty when present. @blocked is redundant.
It was introduced in commit 3af8554bd0 "migration: Add blocker
information", and has not been released. This gives us a chance to
fix the interface with
"Dr. David Alan Gilbert" writes:
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
>> On Mon, 19 Apr 2021 at 17:27, Markus Armbruster wrote:
>> >
>> > Result @blocked is true when and only when result @blocked-reasons is
>> > present. It's always non-empty when present. @blocked is
On Mon, Apr 19, 2021 at 10:33:07PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> A newer compiler is needed to build tests for Power10 instructions. As
> done for arm64 on c729a99d2701, a new '-test-cross' image is created for
> ppc64 and ppc64le. As done on 936fda4d771f,
Patchew URL:
https://patchew.org/QEMU/1618889702-13104-1-git-send-email-igor.druzhi...@citrix.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1618889702-13104-1-git-send-email-igor.druzhi...@citrix.com
Subject:
When we're replacing the existing mapping there is possibility of a race
on memory map with other threads doing mmap operations - the address being
unmapped/re-mapped could be occupied by another thread in between.
Linux mmap man page recommends keeping the existing mappings in place to
reserve
Overall, looking good. I'm pretty much happy to take it into 6.1. I
do have quite a few comments below, but they're basically all just
polish.
On Wed, Mar 31, 2021 at 01:53:08PM +1100, Alexey Kardashevskiy wrote:
> The PAPR platform which describes an OS environment that's presented by
Nit:
On Tue, Apr 20, 2021 at 02:08:44PM +1200, Kai Huang wrote:
> On Mon, 2021-04-19 at 18:01 +0800, Yang Zhong wrote:
> > From: Sean Christopherson
> >
> > KVM_CAP_SGX_ATTRIBUTE is a proposed capability for Intel SGX that can be
> > used by userspace to enable privileged attributes, e.g. access to
On Tue, Apr 20, 2021 at 10:56 AM Alistair Francis wrote:
>
> On Sat, Apr 17, 2021 at 12:48 AM Emmanuel Blot
> wrote:
> >
> > When no MMU is used and the guest code attempts to fetch an instruction
> > from an invalid memory location, the exception index defaults to a data
> > load access fault,
On 4/19/21 10:26 PM, John Snow wrote:
On 4/15/21 5:52 AM, Stefan Hajnoczi wrote:
Yeah, it seems very nice for allowing multiple event listeners that
don't steal each other's events. I like it.
qmp.event_listener() could take a sequence of QMP event names to trigger
on. If the sequence is empty
Public bug reported:
2021-04-20T01:26:36.662244Z qemu-system-x86_64: usbredirparser: bulk transfer
length exceeds limits 131072 > 65536
2021-04-20T01:26:36.662276Z qemu-system-x86_64: usbredirparser: error
usbredirparser_send_* call invalid params, please report!!
2021-04-20T01:26:57.670412Z
On 4/15/21 5:52 AM, Stefan Hajnoczi wrote:
Yeah, it seems very nice for allowing multiple event listeners that
don't steal each other's events. I like it.
qmp.event_listener() could take a sequence of QMP event names to trigger
on. If the sequence is empty then all QMP events will be reported.
On Mon, 2021-04-19 at 18:01 +0800, Yang Zhong wrote:
> From: Sean Christopherson
>
> KVM_CAP_SGX_ATTRIBUTE is a proposed capability for Intel SGX that can be
> used by userspace to enable privileged attributes, e.g. access to the
> PROVISIONKEY.
>
> Signed-off-by: Sean Christopherson
>
On 2021/4/20 上午7:30, Alistair Francis wrote:
On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote:
This patch set gives an implementation of "RISC-V Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
you can find the pdf format or the source code.
I take
From: Matheus Ferst
Tests for Byte-Reverse Halfword, Word and Doubleword
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64/Makefile.target | 7 +++
tests/tcg/ppc64le/Makefile.target | 7 +++
tests/tcg/ppc64le/byte_reverse.c | 22 ++
3 files changed, 36
From: Matheus Ferst
This series adds gcc-10 based images to enable the build of tests with Power10
instructions. Then, to put it to good use, a tests for the byte-reverse
instructions (implemented in 9d69cfa2faa7) is introduced.
Matheus Ferst (2):
tests/docker: gcc-10 based images for
From: Matheus Ferst
A newer compiler is needed to build tests for Power10 instructions. As
done for arm64 on c729a99d2701, a new '-test-cross' image is created for
ppc64 and ppc64le. As done on 936fda4d771f, a test for compiler support
is added to verify that the toolchain in use has
On Mon, Apr 12, 2021 at 04:27:43PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 3/31/21 11:37 PM, David Gibson wrote:
> > On Wed, Mar 31, 2021 at 09:04:37PM -0300, Daniel Henrique Barboza wrote:
> > > Commit 47c8c915b162 fixed a problem where multiple spapr_drc_detach()
> > > requests were
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
On Mon, Apr 19, 2021 at 02:40:35PM +, Bruno Piazera Larsen wrote:
> > > > * move gen_write_xer and gen_read_xer into cpu_init.c, as they're
> > > > used for some sprs, and whatever needs to be moved with it
> > >
> > > I'd leave them where they are currently. Instead what I think we should
> >
On Mon, Apr 19, 2021 at 11:28 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 4/18/21 10:56 PM, frank.ch...@sifive.com wrote:
> > +#elif defined(TARGET_RISCV)
> > +/*
> > + * For RISC-V, InvalidOp is set when multiplicands are Inf and zero
> > + * and returns default
Public bug reported:
It appears that running `fstrim` or similar is useless when the VM is on
a LUKS-encrypted device using QEMU's native LUKS support.
Looking at the source, it seems that block/crypto.c lacks an
implementation for bdrv_co_pdiscard, which probably needs to delegate to
a
On 2021/4/20 上午7:25, Alistair Francis wrote:
On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote:
The Core-Local Interrupt Controller (CLIC) provides low-latency,
vectored, pre-emptive interrupts for RISC-V systems.
The CLIC also supports a new Selective Hardware Vectoring feature
that allow
On Sat, Apr 17, 2021 at 12:48 AM Emmanuel Blot wrote:
>
> When no MMU is used and the guest code attempts to fetch an instruction
> from an invalid memory location, the exception index defaults to a data
> load access fault, rather an instruction access fault.
>
> Signed-off-by: Emmanuel Blot
On 2021/4/20 上午7:23, Alistair Francis wrote:
On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote:
CSR mintstatus holds the active interrupt level for each supported
privilege mode. sintstatus, and user, uintstatus, provide restricted
views of mintstatus.
Signed-off-by: LIU Zhiwei
---
On Mon, Apr 19, 2021 at 07:04:34PM +, Lucas Mateus Martins Araujo e Castro
wrote:
>
>
> >> spapr_hcall.c:
> >> function h_enter call ppc_hash64_hpte_page_shift_noslb,
> >> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
> >> function remove_hpte call ppc_hash64_map_hptes,
On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote:
>
> This patch set gives an implementation of "RISC-V Core-Local Interrupt
> Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
> you can find the pdf format or the source code.
>
> I take over the job from Michael Clark, who
On Fri, Apr 9, 2021 at 5:56 PM LIU Zhiwei wrote:
>
> The Core-Local Interrupt Controller (CLIC) provides low-latency,
> vectored, pre-emptive interrupts for RISC-V systems.
>
> The CLIC also supports a new Selective Hardware Vectoring feature
> that allow users to optimize each interrupt for
On Fri, Apr 9, 2021 at 5:52 PM LIU Zhiwei wrote:
>
> CSR mintstatus holds the active interrupt level for each supported
> privilege mode. sintstatus, and user, uintstatus, provide restricted
> views of mintstatus.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/cpu.h | 2 ++
>
On Mon, Apr 19, 2021 at 4:16 PM Alistair Francis
wrote:
>
> This series adds support for ePMP v0.9.1 to the QEMU RISC-V target.
>
> This is based on previous patches, but has been rebased on the latest
> master and updated for the latest spec.
>
> The spec is avaliable at:
>
There's a request for a backport of this fix to be made to Ubuntu 20.04
in duplicate bug 1924231, so I'm adding a task for that.
** Also affects: qemu (Ubuntu Focal)
Importance: Undecided
Status: New
** Changed in: qemu (Ubuntu Focal)
Status: New => Confirmed
** Changed in:
Hi,
On 4/19/21 3:35 PM, Cleber Rosa wrote:
On Mon, Apr 19, 2021 at 12:25:44PM -0300, Wainer dos Santos Moschetta wrote:
Hi,
On 4/14/21 7:14 PM, Cleber Rosa wrote:
Instead of having, by default, the checksum in the tests, and the
definition of tests in the framework, let's keep them together.
On Mon, Apr 19, 2021 at 04:18:25PM -0400, Eduardo Habkost wrote:
> On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote:
> > Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
> > CPUX86State.xmm_regs[] has already been extended to 512bit to support
> > AVX512.
> > Also,
On Wed, Apr 07, 2021 at 04:34:57PM +0200, Greg Kurz wrote:
> Now that virtio-scsi-pci and virtio-blk-pci map 1 virtqueue per vCPU,
> a serious slow down may be observed on setups with a big enough number
> of vCPUs.
>
> Exemple with a pseries guest on a bi-POWER9 socket system (128 HW threads):
>
On Tue, Apr 20, 2021 at 7:26 AM Alexander Wagner
wrote:
>
> Hi,
>
> I just wanted to check if the patch [1] is missing anything to be
> merged? If so, please let me know.
Thanks for the ping!
You have done everything correctly, I just forgot to apply the patch.
Do you mind re-sending the patch
Hi,
I just wanted to check if the patch [1] is missing anything to be
merged? If so, please let me know.
Regards
Alex
[1]
https://patchew.org/QEMU/20210310221208.167990-1-alexander.wag...@ulal.de/
On Mon, Apr 19, 2021 at 10:58 PM Philippe Mathieu-Daudé wrote:
> On 4/19/21 10:13 PM, Mark Cave-Ayland wrote:
> > On 17/04/2021 15:02, Philippe Mathieu-Daudé wrote:
> >
> >> Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
> >> regions"), all newly created regions are assigned with
On 4/19/21 9:27 PM, Richard Henderson wrote:
> On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
>> Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined
>> and use it in cpu.c and op_helper.c.
>
> Why "error_pc"? The usage in mips_cpu_set_pc certainly isn't in
> response to any kind
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2a82dbbd6d..95897e63af 100644
--- a/target/arm/translate-a64.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1b0951c45b..29fbbb84b2 100644
--- a/target/arm/translate.c
+++
This is the only caller. Adjust some commentary to talk
about SCTLR_B instead of the vanishing function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 37 -
1 file changed, 16 insertions(+), 21 deletions(-)
diff
Using cpu_abort takes care of things like unregistering a
SIGABRT handler for user-only.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4aa7650d3a..8275eb2e65
Hi Mark,
On 4/19/21 10:13 PM, Mark Cave-Ayland wrote:
> On 17/04/2021 15:02, Philippe Mathieu-Daudé wrote:
>
>> Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
>> regions"), all newly created regions are assigned with
>> unassigned_mem_ops (which might be then overwritten).
>>
>>
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3bda16ecd..2a82dbbd6d 100644
---
On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
+#define STUB_HELPER(NAME, ...) \
+static inline void gen_helper_##NAME(__VA_ARGS__) \
+{ qemu_build_not_reached(); }
Does this really work when optimization is on? I suspect you need additional
cleanups before you can use
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c.inc | 48 -
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index e706c37c80..a02b8369a1
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 584c4d047c..864ed669c4 100644
--- a/target/arm/translate-sve.c
+++
On Mon, Apr 19, 2021 at 02:21:11PM -0500, Connor Kuehl wrote:
> On 4/19/21 2:07 PM, Vivek Goyal wrote:
> >> This is a helpful note, but it doesn't tell the whole story. I think
> >> it'd be helpful to add one last note to this option which is to
> >> recommend reading the virtiofsd(1) man-page for
In the case of gpr load, merge the size and is_signed arguments;
otherwise, simply convert size to memop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 78 --
1 file changed, 33 insertions(+), 45 deletions(-)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b90d6880e7..ac60dcf760 100644
---
On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 4
target/mips/tcg/tcg-internal.h | 9 +
2 files changed, 9 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f58ac4f018..2cdf58daa1 100644
--- a/target/arm/translate.c
+++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ac60dcf760..d3bda16ecd 100644
---
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 2 ++
For 128-bit load/store, use 16-byte alignment. This
requires that we perform the two operations in the
correct order so that we generate the alignment fault
before modifying memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 42
Now that these bits have been moved out of tb->flags,
where TBFLAG_ANY was filling from the top, move AM32
to fill from the top, and A32 and M32 to fill from the
bottom. This means fewer changes when adding new bits.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-neon.c.inc | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 9c2b076027..e706c37c80 100644
From: Klaus Jensen
With the introduction of the nvme-subsystem device we are really
cluttering up the hw/block directory.
As suggested by Philippe previously, move the nvme emulation to hw/nvme.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Klaus Jensen
---
meson.build
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v5: Adjust assert_hflags_rebuild_correctly.
---
target/arm/cpu.h | 49
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Fix alignment for n in {2, 4}.
---
target/arm/translate.h | 1 +
target/arm/translate.c | 15 +
target/arm/translate-neon.c.inc | 37 +
3 files changed, 44
On Mon, Mar 29, 2021 at 03:41:34PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 29.03.2021 14:48, Daniel P. Berrangé wrote:
[...]
> > > > There's feels like there's a lot of conceptual overlap with the
> > > > query-cpu-model-expansion command. That reports in a arch independant
> > > > format,
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 10766f210c..f50afb23e7 100644
---
In preparation for splitting tb->flags across multiple
fields, introduce a structure to hold the value(s).
So far this only migrates the one uint32_t and fixes
all of the places that require adjustment to match.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-vfp.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index f50afb23e7..e20d9c7ba6 100644
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 29fbbb84b2..f58ac4f018 100644
--- a/target/arm/translate.c
+++
From: Klaus Jensen
The NvmeCtrl num_namespaces member is just an indirection for the
NVME_MAX_NAMESPACES constant.
Remove the indirection.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 1 -
hw/block/nvme.c | 30 +++---
2 files changed, 15 insertions(+), 16
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2cdf58daa1..4decb2610e 100644
--- a/target/arm/translate.c
+++
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.
This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes. Thus we
retain an "internal"
Create a finalize_memop function that computes alignment and
endianness and returns the final MemOp for the operation.
Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special
handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32
so that s->be_data is not added by the
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell
From: Klaus Jensen
Validation of the max_active and max_open zoned parameters are
independent of any other state, so move them to the early
nvme_ns_check_constraints parameter checks.
Signed-off-by: Klaus Jensen
---
hw/block/nvme-ns.c | 52 +-
1
On Mon, Apr 19, 2021 at 07:47:34PM +0100, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > On Mon, Apr 19, 2021 at 06:15:56PM +0100, Daniel P. Berrangé wrote:
> > > On Mon, Apr 19, 2021 at 06:11:47PM +0100, Dr. David Alan Gilbert wrote:
> > > > * Eduardo
We're about to split tbflags into two parts. These macros
will ensure that the correct part is used with the correct
set of bits.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 22 +-
target/arm/helper-a64.c| 2 +-
target/arm/helper.c
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h
On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
Currently cpu_mips_translate_address() calls raise_mmu_exception(),
and do_translate_address() calls cpu_loop_exit_restore().
This API split is dangerous, we could call cpu_mips_translate_address
without returning to the main loop.
As there is
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So PSTATE_SS -> PSTATE__SS in the uses, and document it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So SCTLR_B -> SCTLR__B in the 3 uses, and document it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field. This error was hidden
by what should have been unnecessary masking in translate.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/neon-ls.decode | 4 ++--
From: Klaus Jensen
Remove non-shared defines from the shared header.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h| 2 --
hw/block/nvme-ns.c | 1 +
hw/block/nvme.c| 1 +
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index
Based-on: 20210416183106.1516563-1-richard.hender...@linaro.org
("[PATCH v5 for-6.1 0/9] target/arm mte fixes")
Changes for v5:
* Address review issues.
* Use cpu_abort in assert_hflags_rebuild_correctly
The only patch lacking review is the new one:
On Thu, Apr 15, 2021 at 6:52 PM Cleber Rosa wrote:
>
> Because s390x targets it can not currently migrate without a guest
> running.
>
> Future work may provide a proper guest, but for now, it's safer to
> cancel the test.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/migration.py | 6
From: Klaus Jensen
Add an nvme_moff() helper.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 7 ++-
hw/block/nvme-dif.c | 4 ++--
hw/block/nvme-ns.c | 2 +-
hw/block/nvme.c | 12 ++--
4 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/block/nvme.h
On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote:
> Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
> CPUX86State.xmm_regs[] has already been extended to 512bit to support
> AVX512.
> Also, other qemu level supports for AVX512 registers are there for
> years.
> But
From: Klaus Jensen
In preparation for moving the nvme device into its own subtree, merge
the header files into one.
Also add missing copyright notice and add list of authors with
substantial contributions.
Signed-off-by: Klaus Jensen
---
hw/block/nvme-dif.h| 63 ---
Patchew URL: https://patchew.org/QEMU/20210419191823.1555482-1-f4...@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210419191823.1555482-1-f4...@amsat.org
Subject: [PATCH v3 00/30] target/mips: Re-org to
On 17/04/2021 15:02, Philippe Mathieu-Daudé wrote:
Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
regions"), all newly created regions are assigned with
unassigned_mem_ops (which might be then overwritten).
When using aliased container regions, and there is no region mapped
at
From: Klaus Jensen
It is not an error to report more active/open zones supported than the
number of zones in the namespace.
Signed-off-by: Klaus Jensen
---
hw/block/nvme-ns.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
index
From: Klaus Jensen
Get rid of the (reserved) double underscore use.
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 47 +++
1 file changed, 23 insertions(+), 24 deletions(-)
diff --git
From: Klaus Jensen
There is no need to look up the lba size and metadata size in the LBA
Format structure everytime we want to use it. And we use it a lot.
Cache the values in the NvmeNamespace and update them if the namespace
is formatted.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h
Hi Richard,
Could you review this patch series again please?
I've fixed several issues recently, and am interested to know if it's
ready to commit or would need further changes.
--
Rebecca Cran
On 4/14/2021 2:32 PM, Rebecca Cran wrote:
ARMv8.4 adds the mandatory FEAT_TLBIOS and
From: Klaus Jensen
The inline nvme_ns_status() helper only has a single call site. Remove
it from the header file and inline it for real.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.h | 5 -
hw/block/nvme.c | 15 ---
2 files changed, 8 insertions(+), 12 deletions(-)
diff
On 15:53 Sat 10 Apr , Philippe Mathieu-Daudé wrote:
> Hi Luc,
>
> On 4/10/21 3:19 PM, Luc Michel wrote:
> > On 08:23 Fri 09 Apr , Philippe Mathieu-Daudé wrote:
> >> I've been debugging some odd issue with the clocks:
> >> a clock created in the machine (IOW, not a qdev clock) isn't
> >>
From: Klaus Jensen
Get rid of the (reserved) double underscore use.
Cc: Philippe Mathieu-Daudé
Cc: Thomas Huth
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index
On 19/04/2021 18:02, Cornelia Huck wrote:
That patch seems to be our best candidate so far, but the intermittent
nature of the failures make it hard to pin down... I don't see anything
obviously wrong with the patch, maybe some linux-user experts have a
better idea?
FWIW, I tried reproducing
On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined
and use it in cpu.c and op_helper.c.
Why "error_pc"? The usage in mips_cpu_set_pc certainly isn't in response to
any kind of error...
r~
On 4/19/21 12:18 PM, Philippe Mathieu-Daudé wrote:
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.
Move the opcode definitions to tcg/sysemu_helper.h.inc.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/helper.h | 166
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