Re: [PATCH v2 01/11] hw/arm/aspeed: Do not directly map ram container onto main address bus

On 4/20/21 8:28 PM, Peter Xu wrote: > On Sat, Apr 17, 2021 at 12:30:18PM +0200, Philippe Mathieu-Daudé wrote: >> The RAM container is exposed as an AddressSpace. > > I didn't see where did ram_container got exposed as an address space. > > I see it's added as one subregion of

Re: [PATCH qemu v18] spapr: Implement Open Firmware client interface

On Tue, Apr 20, 2021 at 07:16:35PM +1000, Alexey Kardashevskiy wrote: > > > On 20/04/2021 13:14, David Gibson wrote: > > > > Overall, looking good. I'm pretty much happy to take it into 6.1. I > > do have quite a few comments below, but they're basically all just > > polish. > > > > On Wed,

Re: [PATCH v3] hw/block/nvme: align with existing style

On Apr 16 07:28, Klaus Jensen wrote: On Apr 16 09:22, Gollu Appalanaidu wrote: Use lower case hexadecimal format for the constants and in comments use the same format as used in Spec. ("h") Signed-off-by: Gollu Appalanaidu --- -v3: Add Suggestions (Philippe) Describe the NVMe

Re: [RFC-PATCH] ppc/spapr: Add support for H_SCM_PERFORMANCE_STATS hcall

On Tue, Apr 20, 2021 at 03:06:18PM +0530, Vaibhav Jain wrote: > Thanks for looking into this patch David, > > David Gibson writes: > > > On Thu, Apr 15, 2021 at 01:23:43PM +0530, Vaibhav Jain wrote: > >> Add support for H_SCM_PERFORMANCE_STATS described at [1] for > >> spapr nvdimms. This

Re: [PATCH v2 1/1] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()

On Tue, Apr 20, 2021 at 01:51:00PM -0300, Daniel Henrique Barboza wrote: > At this moment, PAPR does not provide a way to report errors during a > device removal operation. This led the pSeries machine to implement > extra mechanisms to try to fallback and recover from an error that might > have

Re: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

On Tue, Apr 20, 2021 at 07:02:36PM +, Bruno Piazera Larsen wrote: > > > What I was doing was to only register the spr once, and use the > > > accel-specific functions to set the relevant attributes, so spr_common > > > wouldn't need to where (and if) spr_read_* exists or not. > > > Would this

Re: [PATCH] hw/block/nvme: function formatting fix

On Apr 21 00:52, Gollu Appalanaidu wrote: nvme_map_addr_pmr function arguments not aligned, fix that. Signed-off-by: Gollu Appalanaidu --- hw/block/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 624a1431d0..63ceeb47bd 100644

[Bug 603872] Re: [Feature request] qemu-img image conversion does not show percentage

Progress printing had been added here: https://gitlab.com/qemu-project/qemu/-/commit/6b837bc4a4d So I think it should be fine to close this ticket now. ** Changed in: qemu Status: New => Fix Released -- You received this bug notification because you are a member of qemu- devel-ml, which

[PATCH] hw/block/nvme: function formatting fix

nvme_map_addr_pmr function arguments not aligned, fix that. Signed-off-by: Gollu Appalanaidu --- hw/block/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 624a1431d0..63ceeb47bd 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c

[PATCH v5 14/17] target/riscv: rvb: address calculation

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 +++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 23 ++

[PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 24 target/riscv/translate.c| 6 ++ 3 files

[PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option

From: Frank Chang Default b-ext version is v0.93. Signed-off-by: Frank Chang --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8464a152d14..b76c3c07c5f 100644 ---

[PATCH v5 13/17] target/riscv: rvb: generalized or-combine

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c | 31 + target/riscv/helper.h | 2 ++ target/riscv/insn32-64.decode | 2 ++ target/riscv/insn32.decode |

[PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line

From: Kito Cheng B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 2 ++ 2 files

[PATCH v5 10/17] target/riscv: rvb: shift ones

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvb.c.inc | 48 +

[PATCH v5 07/17] target/riscv: rvb: sign-extend instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvb.c.inc | 12 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn32.decode

[PATCH v5 12/17] target/riscv: rvb: generalized reverse

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c | 71 + target/riscv/helper.h | 7 +++ target/riscv/insn32-64.decode | 2 + target/riscv/insn32.decode |

[PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions

From: Frank Chang Add gen_shifti() and gen_shiftiw() helper functions to reuse the same interfaces for immediate shift instructions. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 54 ++--- target/riscv/translate.c

[PATCH v5 06/17] target/riscv: rvb: min/max instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc | 24 2 files changed, 28 insertions(+) diff --git

[PATCH v5 03/17] target/riscv: rvb: count bits set

From: Frank Chang Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32-64.decode | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvb.c.inc | 12 target/riscv/translate.c

[PATCH v5 11/17] target/riscv: rvb: rotate (left/right)

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 +++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 36 +

[PATCH v5 05/17] target/riscv: rvb: pack two words into one register

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvb.c.inc | 30 +++

[PATCH v5 04/17] target/riscv: rvb: logic-with-negate

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc | 18 ++ 2 files changed, 22 insertions(+) diff --git

[PATCH v5 09/17] target/riscv: rvb: single-bit instructions

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 8 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvb.c.inc | 90 +

[PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn32.decode

[PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 4 +++ target/riscv/insn32.decode | 7 +++- target/riscv/insn_trans/trans_rvb.c.inc | 47 +

[PATCH v5 00/17] support subsets of bitmanip extension

From: Frank Chang This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and Zbs subset instructions. Some Zbp instructions are also implemented as they have similar behavior with their Zba-, Zbb- and Zbs-family instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).

Re: target/ppc: sPAPR invalid function calls when compiling without TCG

On Tue, Apr 20, 2021 at 06:27:38PM +, Lucas Mateus Martins Araujo e Castro wrote: > > > > > > >> spapr_hcall.c: > >> function h_enter call ppc_hash64_hpte_page_shift_noslb, > >> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes > >> function

Re: [PATCH v1] tests/migration: introduce multifd into guestperf

在 2021/3/24 9:18, Hyman Huang 写道: cc th...@redhat.com and berra...@redhat.com Please review, thanks 在 2021/3/20 1:04, huang...@chinatelecom.cn 写道: From: Hyman Guestperf tool does not cover the multifd-enabled migration currently, it is worth supporting so that developers can analysis the

Re: [PATCH 4/5] target/mips: Use check_cp0_enabled() returned value

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: @@ -14809,14 +14811,15 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) } break; case 0x05: +if (!check_cp0_enabled(ctx)) { +break; +} switch

Re: [RFC PATCH 5/5] target/mips: Restrict EVA opcodes to system emulation

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: Enhanced Virtual Address (EVA) instructions are restricted to Kernel execution mode, thus not available on user emulation. Signed-off-by: Philippe Mathieu-Daudé --- RFC because I'd rather not use such #ifdef'ry again. TODO: have the compiler

Re: [PATCH v1] migration/dirtyrate: make sample page count configurable

在 2021/4/15 1:23, huang...@chinatelecom.cn 写道: From: Hyman Huang(黄勇) introduce optional sample-pages argument in calc-dirty-rate, making sample page count per GB configurable so that more accurate dirtyrate can be calculated. Signed-off-by: Hyman Huang(黄勇) --- migration/dirtyrate.c | 32

Re: [PATCH 1/5] target/mips: Remove duplicated check_cp0_enabled() calls in gen_cp0()

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: We already check for CP0 enabled at the beginning of gen_cp0(), no need to check it again after. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 2 -- 1 file changed, 2 deletions(-) Having noticed the default case for

Re: [PATCH 3/5] target/mips: Make check_cp0_enabled() return a boolean

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.h | 7

Re: [PATCH 2/5] target/mips: Simplify CP0 check in nanoMIPS P.LS.E0 EVA pool

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: The nanoMIPS P.LS.E0 pool contains the EVA instructions, which are privileged. Simplify by moving the CP0 check at the top of the pool swich case. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 16 +--- 1

Re: [PATCH 1/5] target/mips: Remove duplicated check_cp0_enabled() calls in gen_cp0()

On 4/20/21 12:34 PM, Philippe Mathieu-Daudé wrote: We already check for CP0 enabled at the beginning of gen_cp0(), no need to check it again after. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 2 -- 1 file changed, 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

On 4/20/21 10:54 AM, Philippe Mathieu-Daudé wrote: The CACHEE opcode "requires CP0 privilege". The pseudocode checks in the ISA manual is: if is_eva and not C0.Config5.EVA: raise exception('RI') if not IsCoprocessor0Enabled(): raise coprocessor_exception(0) Add the

Re: [PATCH v4 16/19] qapi/expr.py: Add docstrings

On 4/17/21 9:18 AM, Markus Armbruster wrote: John Snow writes: On 4/14/21 11:04 AM, Markus Armbruster wrote: John Snow writes: Thanks for taking this on. I realize it's a slog. (Update: much later: AUUUGH WHY DID I DECIDE TO WRITE DOCS. MY HUBRIS) LOL! Signed-off-by: John Snow

Re: [PATCH] tests/migration: fix unix socket migration

在 2021/3/10 0:55, Philippe Mathieu-Daudé 写道: On 3/9/21 5:00 PM, huang...@chinatelecom.cn wrote: From: Hyman The test aborts and error message as the following be throwed: "No such file or directory: '/var/tmp/qemu-migrate-{pid}.migrate", when the unix socket migration test nearly done. The

[PATCH] tcg/ppc: Fix building with Clang

Fix building with Clang. At the moment Clang does not define _CALL_SYSV as GCC does. From clang/lib/Basic/Targets/PPC.cpp in getTargetDefines().. // FIXME: The following are not yet generated here by Clang, but are //generated by GCC: // // _SOFT_FLOAT_ //

tcg/ppc: Fix building with Clang

Fix building with Clang. At the moment Clang does not define _CALL_SYSV as GCC does. From clang/lib/Basic/Targets/PPC.cpp in getTargetDefines().. // FIXME: The following are not yet generated here by Clang, but are //generated by GCC: // // _SOFT_FLOAT_ //

Re: [Virtio-fs] [PATCH v2 1/7] virtiofsd: Changed allocations of fuse_req to GLib functions

On Tue, Apr 20, 2021 at 9:03 PM Vivek Goyal wrote: > On Tue, Apr 20, 2021 at 05:46:36PM +0200, Mahmoud Mandour wrote: > > Replaced the allocation and deallocation of fuse_req structs > > using calloc()/free() call pairs to a GLib's g_try_new0() > > and g_free(). > > Hi, > > What's the context of

Re: [PATCH v2] hw/riscv: Fix OT IBEX reset vector

On Tue, Apr 20, 2021 at 6:01 PM Alexander Wagner wrote: > > The IBEX documentation [1] specifies the reset vector to be "the most > significant 3 bytes of the boot address and the reset value (0x80) as > the least significant byte". > > [1] >

RE: [PATCH v2] Revert "target/mips: Deprecate nanoMIPS ISA"

On 4/20/21 6:06 PM, Aleksandar Rikalo wrote: > Hi Philippe, > >> The plan is to drop the nanoMIPS disassembler because it is broken >> since more than 2 years and nobody ever cared to fix it after >> Stefan's attempt in Nov 2018: >>

[Bug 1923689] Re: sig-abort / coredump observed from aio_ctx_finalize

Thanks to Stefan for the help -- IRL we debugged this to the following assert failure: assert(QSIMPLEQ_EMPTY(>bh_slice_list)); This has been resolved upstream in https://github.com/qemu/qemu/commit/c81219a7dd36a815bd85beed9932fc973d4f5d51 ** Changed in: qemu Status: New => Confirmed

[PATCH v2] target/riscv: fix wfi exception behavior

The wfi exception trigger behavior should take into account user mode, hstatus.vtw, and the fact the an wfi might raise different types of exceptions depending on various factors: If supervisor mode is not present: - an illegal instruction exception should be generated if user mode executes and

[ANNOUNCE] QEMU 6.0.0-rc4 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the fifth release candidate for the QEMU 6.0 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-6.0.0-rc4.tar.xz

Re: [PATCH v4] memory: Directly dispatch alias accesses on origin memory region

On Sun, Apr 18, 2021 at 07:57:08AM +0200, Philippe Mathieu-Daudé wrote: > Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all > regions"), all newly created regions are assigned with > unassigned_mem_ops (which might be then overwritten). > > When using aliased container regions, and

Re: [PATCH v3] memory: Directly dispatch alias accesses on origin memory region

On Tue, Apr 20, 2021 at 11:10:26AM +0200, Philippe Mathieu-Daudé wrote: > On 4/20/21 9:00 AM, Mark Cave-Ayland wrote: > > On 19/04/2021 21:58, Philippe Mathieu-Daudé wrote: > > > >> Hi Mark, > >> > >> On 4/19/21 10:13 PM, Mark Cave-Ayland wrote: > >>> On 17/04/2021 15:02, Philippe Mathieu-Daudé

Re: [PATCH] hw/block/nvme: fix io-command set profile feature

On Apr 19 16:18, Gollu Appalanaidu wrote: Currently IO Command Set Profile feaure is supported, but feature support flag not set and this feature is changable add support for that. Remove filling default value of feature in CQE CDW0 with zero, since it fallbacks to default case and it is zero

Re: [PATCH 1/2] hw/block/nvme: consider metadata read aio return value in compare

On Apr 16 12:52, Gollu Appalanaidu wrote: Currently in compare command metadata aio read blk_aio_preadv return value ignored, consider it and complete the block accounting. Signed-off-by: Gollu Appalanaidu --- hw/block/nvme.c | 11 +++ 1 file changed, 11 insertions(+) diff --git

Re: [PATCH v3] hw/block/nvme: fix lbaf formats initialization

On Apr 16 17:29, Gollu Appalanaidu wrote: Currently LBAF formats are being intialized based on metadata size if and only if nvme-ns "ms" parameter is non-zero value. Since FormatNVM command being supported device parameter "ms" may not be the criteria to initialize the supported LBAFs.

[RFC PATCH 5/5] target/mips: Restrict EVA opcodes to system emulation

Enhanced Virtual Address (EVA) instructions are restricted to Kernel execution mode, thus not available on user emulation. Signed-off-by: Philippe Mathieu-Daudé --- RFC because I'd rather not use such #ifdef'ry again. TODO: have the compiler elide this code. target/mips/translate.c | 14

[PATCH 3/5] target/mips: Make check_cp0_enabled() return a boolean

To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.h | 7 ++- target/mips/translate.c | 4 +++- 2 files

[PATCH 4/5] target/mips: Use check_cp0_enabled() returned value

If CP0 is disabled, it is pointless to emit more code, since the 'coprocessor unusable' exception will be raised. Use the returned value from check_cp0_enabled() to return early. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 144

[PATCH 2/5] target/mips: Simplify CP0 check in nanoMIPS P.LS.E0 EVA pool

The nanoMIPS P.LS.E0 pool contains the EVA instructions, which are privileged. Simplify by moving the CP0 check at the top of the pool swich case. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 16 +--- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git

[PATCH 1/5] target/mips: Remove duplicated check_cp0_enabled() calls in gen_cp0()

We already check for CP0 enabled at the beginning of gen_cp0(), no need to check it again after. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index

[PATCH 0/5] target/mips: Make check_cp0_enabled() return a boolean

Address the following remark from Richard: (1) check_cp0_enabled must return a boolean, so that the caller can avoid emitting dead code after the exception is emitted. https://www.mail-archive.com/qemu-devel@nongnu.org/msg800114.html Based-on:

Re: [PATCH v2 00/11] memory: Forbid mapping AddressSpace root MemoryRegion

On Sat, Apr 17, 2021 at 12:30:17PM +0200, Philippe Mathieu-Daudé wrote: > AddressSpace are physical address view and shouldn't be using > non-zero base address. The correct way to map a MR used as AS > root is to use a MR alias. Today when I rethink this, I figured another way (maybe easier?) to

Re: [Virtio-fs] [PATCH v2 1/7] virtiofsd: Changed allocations of fuse_req to GLib functions

On Tue, Apr 20, 2021 at 05:46:36PM +0200, Mahmoud Mandour wrote: > Replaced the allocation and deallocation of fuse_req structs > using calloc()/free() call pairs to a GLib's g_try_new0() > and g_free(). Hi, What's the context of these patches. I see all of them are switching to glib functions.

RE: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

> > What I was doing was to only register the spr once, and use the > > accel-specific functions to set the relevant attributes, so spr_common > > wouldn't need to where (and if) spr_read_* exists or not. > > Would this work? > > > > Just ignoring the read and write functions means we still need >

Re: [Virtio-fs] [for-6.1 2/2] virtiofsd: Add support for FUSE_SYNCFS request

On Mon, Apr 19, 2021 at 05:11:42PM +0200, Greg Kurz wrote: > Honor the expected behavior of syncfs() to synchronously flush all > data and metadata on linux systems. Like the ->sync_fs() superblock > operation in the linux kernel, FUSE_SYNCFS has a 'wait' argument that > tells whether the server

Re: [PATCH v2 01/11] hw/arm/aspeed: Do not directly map ram container onto main address bus

On Sat, Apr 17, 2021 at 12:30:18PM +0200, Philippe Mathieu-Daudé wrote: > The RAM container is exposed as an AddressSpace. I didn't see where did ram_container got exposed as an address space. I see it's added as one subregion of get_system_memory(), which looks okay? -- Peter Xu

Re: target/ppc: sPAPR invalid function calls when compiling without TCG

>> spapr_hcall.c: >> function h_enter call ppc_hash64_hpte_page_shift_noslb, >> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes >> function remove_hpte call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes >> and ppc_hash64_tlb_flush_hpte >> function

[PATCH] Fix typo in CFI build documentation

Signed-off-by: serge-sans-paille --- docs/devel/control-flow-integrity.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/devel/control-flow-integrity.rst b/docs/devel/control-flow-integrity.rst index d89d707..e6b73a4 100644 ---

Re: [PATCH v4 02/19] flake8: Enforce shorter line length for comments and docstrings

On 4/17/21 6:52 AM, Markus Armbruster wrote: John Snow writes: On 4/16/21 8:44 AM, Markus Armbruster wrote: John Snow writes: It will be an eventual thing, though: I think we need to agree on a style guide document and in that same series, fix up the instances of defying that guide. I

[PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

The CACHEE opcode "requires CP0 privilege". The pseudocode checks in the ISA manual is: if is_eva and not C0.Config5.EVA: raise exception('RI') if not IsCoprocessor0Enabled(): raise coprocessor_exception(0) Add the missing checks. Inspired-by: Richard Henderson

Re: [PATCH 0/2] i386: Fix interrupt based Async PF enablement

On Thu, Apr 15, 2021 at 08:14:30PM +0100, Dr. David Alan Gilbert wrote: > * Paolo Bonzini (pbonz...@redhat.com) wrote: > > On 06/04/21 13:42, Vitaly Kuznetsov wrote: > > > older machine types are still available (I disable it for <= 5.1 but we > > > can consider disabling it for 5.2 too). The

[Bug 1808928] Re: Bitmap Extra data is not supported

my patches went in, ultimately, and my focus was since shifted elsewhere. I just tried this by *manually* adding some extra data to a bitmap by hand. qemu-img create -f qcow2 foo.qcow2 64m qemu-img bitmap --add foo.qcow2 mybitmap This creates a bitmap extension header like this (starting at

[Bug 1808928] Re: Bitmap Extra data is not supported

Sorry, that formatted *terribly*... please see the attachment for a raw text version with arbitrarily long columns that looks nicer. :( ** Attachment added: "Raw text for comment #7 with better formatting (?)" https://bugs.launchpad.net/qemu/+bug/1808928/+attachment/5490362/+files/bztemp --

Re: [PATCH 00/14] hw(/block/)nvme: spring cleaning

On Mon, Apr 19, 2021 at 09:27:47PM +0200, Klaus Jensen wrote: > From: Klaus Jensen > > This series consists of various clean up patches. > > The final patch moves nvme emulation from hw/block to hw/nvme. Series looks good to me. Reviewed-by: Keith Busch

Re: [PATCH 0/4] DEVICE_NOT_DELETED/DEVICE_UNPLUG_ERROR QAPI events

Hello, Quick update about this work: - the hotunplug timeout was reverted in the pSeries machine for 6.0.0. This means that we have no use for a DEVICE_NOT_DELETED event or similar. I'll drop it for the next version of the series. - there is a good chance that the pSeries kernel will introduce

Re: [PATCH v6] qapi: introduce 'query-cpu-model-cpuid' action

On Tue, Apr 20, 2021 at 07:19:40PM +0300, Valeriy Vdovin wrote: [...] > +## > +# @query-cpu-model-cpuid: > +# > +# Returns description of a virtual CPU model, created by QEMU after cpu > +# initialization routines. The resulting information is a reflection of a > parsed > +# '-cpu' command line

Re: [PATCH v6] qapi: introduce 'query-cpu-model-cpuid' action

20.04.2021 19:19, Valeriy Vdovin wrote: Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to get virtualized cpu model info generated by QEMU during VM initialization in the form of cpuid representation. [..] +CpuModelCpuidDescription

Re: [PATCH 1/2] tests/docker: gcc-10 based images for ppc64{, le} tests

"Matheus K. Ferst" writes: > On 20/04/2021 09:20, Alex Bennée wrote: >> David Gibson writes: >> >>> On Mon, Apr 19, 2021 at 10:33:07PM -0300, matheus.fe...@eldorado.org.br >>> wrote: From: Matheus Ferst A newer compiler is needed to build tests for Power10 instructions. As

Re: [RFC PATCH 2/2] qemu-img convert: Fix sparseness detection

20.04.2021 18:04, Kevin Wolf wrote: Am 20.04.2021 um 16:31 hat Vladimir Sementsov-Ogievskiy geschrieben: 15.04.2021 18:22, Kevin Wolf wrote: In order to avoid RMW cycles, is_allocated_sectors() treats zeroed areas like non-zero data if the end of the checked area isn't aligned. This can

[PATCH v2 1/1] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()

At this moment, PAPR does not provide a way to report errors during a device removal operation. This led the pSeries machine to implement extra mechanisms to try to fallback and recover from an error that might have happened during the hotunplug in the guest side. This started to change a bit with

[PATCH v2 0/1] pSeries: handle hotunplug errors in drc_unisolate_logical()

Changes from v1: - added more context in the commit message - added David's R-b v1 link: https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg03145.html Hi, This is the QEMU side of a kernel change being proposed in [1], where an attempt to implement a CPU hotunplug error report mechanism

Re: [PATCH v2] Revert "target/mips: Deprecate nanoMIPS ISA"

On 4/20/21 6:06 PM, Aleksandar Rikalo wrote: > Hi Philippe, > >> The plan is to drop the nanoMIPS disassembler because it is broken >> since more than 2 years and nobody ever cared to fix it after Stefan's >> attempt in Nov 2018: >>

Re: [PATCH v6] qapi: introduce 'query-cpu-model-cpuid' action

Patchew URL: https://patchew.org/QEMU/20210420161940.24306-1-valeriy.vdo...@virtuozzo.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210420161940.24306-1-valeriy.vdo...@virtuozzo.com Subject: [PATCH v6] qapi:

[PATCH v6] qapi: introduce 'query-cpu-model-cpuid' action

Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to get virtualized cpu model info generated by QEMU during VM initialization in the form of cpuid representation. Diving into more details about virtual cpu generation: QEMU first parses '-cpu' command line option. From

Re: [PATCH v2] i386: Add ratelimit for bus locks acquired in guest

Hello, Thanks for the patch. Comments below: On Tue, Apr 20, 2021 at 05:37:36PM +0800, Chenyi Qiang wrote: > Virtual Machines can exploit bus locks to degrade the performance of > system. To address this kind of performance DOS attack, bus lock VM exit > is introduced in KVM and it will report

[Bug 1819182] Re: info does not recognize file format of vpc with subformat=fixed

@smoser : fixed-size VHD images don't have a header, and there is AFAIK currently no way for probing a footer in the QEMU code, so relying on the extension seems to be the only way right now, as far as I can tell. -- You received this bug notification because you are a member of qemu- devel-ml,

[Bug 304636] Re: -hda FAT:. limited to 504MBytes

** Tags added: block -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/304636 Title: -hda FAT:. limited to 504MBytes Status in QEMU: Confirmed Status in qemu package in Ubuntu: Won't Fix Bug

Re: [PATCH v2] Revert "target/mips: Deprecate nanoMIPS ISA"

Hi Philippe, > The plan is to drop the nanoMIPS disassembler because it is broken > since more than 2 years and nobody ever cared to fix it after Stefan's > attempt in Nov 2018: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg576504.html > So it is certainly unused. Unused unmaintained

[PATCH v2 6/7] virtiofsd/passthrough_ll.c: Changed local allocations to GLib functions

Changed the allocations of some local variables to GLib's allocation functions, such as g_try_malloc0(), and annotated those variables as g_autofree. Subsequently, I was able to remove the calls to free(). Signed-off-by: Mahmoud Mandour Reviewed-by: Stefan Hajnoczi ---

[PATCH v2 5/7] virtiofsd: Changed allocations of fv_VuDev & its internals to GLib functions

Changed the allocations of fv_VuDev structs, VuDev structs, and fv_QueueInfo strcuts from using calloc()/realloc() & free() to using the equivalent functions from GLib. In instances, removed the pair of allocation and assertion for non-NULL checking with a GLib function that aborts on error.

[PATCH v2 7/7] virtiofsd/fuse_virtio.c: Changed allocations of locals to GLib

Replaced the allocation of local variables from malloc() to GLib allocation functions. In one instance, dropped the usage to an assert after a malloc() call and used g_malloc() instead. Signed-off-by: Mahmoud Mandour Reviewed-by: Stefan Hajnoczi --- tools/virtiofsd/fuse_virtio.c | 9 -

[PATCH v2 4/7] virtiofsd: Changed allocation of lo_map_elems to GLib's functions

Replaced (re)allocation of lo_map_elem structs from realloc() to GLib's g_try_realloc_n() and replaced the respective free() call with a g_free(). Signed-off-by: Mahmoud Mandour Reviewed-by: Stefan Hajnoczi --- tools/virtiofsd/passthrough_ll.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH v2 3/7] virtiofsd: Changed allocations of fuse_session to GLib's functions

Replaced the allocation and deallocation of fuse_session structs from calloc() and free() calls to g_try_new0() and g_free(). Signed-off-by: Mahmoud Mandour Reviewed-by: Stefan Hajnoczi --- tools/virtiofsd/fuse_lowlevel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH v2 2/7] virtiofds: Changed allocations of iovec to GLib's functions

Replaced the calls to malloc()/calloc() and their respective calls to free() of iovec structs with GLib's allocation and deallocation functions. Also, in one instance, used g_new0() instead of a calloc() call plus a null-checking assertion. iovec structs were created locally and freed as the

[PATCH v2 1/7] virtiofsd: Changed allocations of fuse_req to GLib functions

Replaced the allocation and deallocation of fuse_req structs using calloc()/free() call pairs to a GLib's g_try_new0() and g_free(). Signed-off-by: Mahmoud Mandour Reviewed-by: Stefan Hajnoczi --- tools/virtiofsd/fuse_lowlevel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH v2 0/7] virtiofsd: Changed various allocations to GLib functions

Replaced allocations done using malloc(), calloc(), and realloc() to their equivalent functions in GLib. Memory that is allocated locally and freed when the function exits are annotated g_autofree so that the deallocation is automatically handled. Subsequently, I could remove a bunch of free()

Re: [PATCH 2/2] tests/tcg/ppc64le: tests for brh/brw/brd

On 20/04/2021 11:58, Richard Henderson wrote: On 4/19/21 6:33 PM, matheus.fe...@eldorado.org.br wrote: +    var = 0xFEDCBA9876543210; +    asm("brh %0, %0" : "=r"(var)); +    assert(var == 0xDCFE98BA54761032); Incorrect inline assembly, you are not declaring an input. Use "+r" for in/out

Re: [PATCH 1/2] tests/docker: gcc-10 based images for ppc64{, le} tests

On 20/04/2021 09:35, Philippe Mathieu-Daudé wrote: On 4/20/21 2:20 PM, Alex Bennée wrote: David Gibson writes: On Mon, Apr 19, 2021 at 10:33:07PM -0300, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst A newer compiler is needed to build tests for Power10 instructions. As done for

Re: [PATCH for-6.0?] qga: fix guest-get-disks regression

marcandre.lur...@redhat.com writes: > From: Marc-André Lureau > > Commit 54aa3de72 ("qapi: Use QAPI_LIST_PREPEND() where possible") > inadvertently removed the has_dependencies from the partition disk > info, resulting in empty list being returned. > > Fixes:

Re: [PATCH 2/2] tests/tcg/ppc64le: tests for brh/brw/brd

On 4/19/21 6:33 PM, matheus.fe...@eldorado.org.br wrote: +#include +#include + +int main(void) +{ Oh, also, there's nothing in here that requires stdio.h. r~

Re: [RFC PATCH 2/2] qemu-img convert: Fix sparseness detection

Am 20.04.2021 um 16:31 hat Vladimir Sementsov-Ogievskiy geschrieben: > 15.04.2021 18:22, Kevin Wolf wrote: > > In order to avoid RMW cycles, is_allocated_sectors() treats zeroed areas > > like non-zero data if the end of the checked area isn't aligned. This > > can improve the efficiency of the

Re: [PATCH for-6.0?] qga: fix guest-get-disks regression

On Tue, 20 Apr 2021 at 16:03, Markus Armbruster wrote: > > marcandre.lur...@redhat.com writes: > > > From: Marc-André Lureau > > > > Commit 54aa3de72 ("qapi: Use QAPI_LIST_PREPEND() where possible") > > inadvertently removed the has_dependencies from the partition disk > > info, resulting in

[PATCH V6 6/6] net/net.c: Add handler for COLO passthrough connection

Use connection protocol,src port,dst port,src ip,dst ip as the key to bypass certain network traffic in COLO compare. Signed-off-by: Zhang Chen --- net/net.c | 160 +- 1 file changed, 158 insertions(+), 2 deletions(-) diff --git a/net/net.c

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