Re: [PATCH 12/24] bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Copy of the signal trampoline code for arm, as well as setup_sigtramp to > write it to the stack. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch_sigtramp.h | 52 + >

Re: [PATCH 10/24] bsd-user/arm/target_arch_reg.h: Implement core dump register copying

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Implement the register copying routines to extract registers from the > cpu for core dump generation. > > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- > bsd-user/arm/target_arch_reg.h | 60

Re: [PATCH 08/24] bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions

On Tue, Oct 19, 2021 at 11:45 AM Warner Losh wrote: > > Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data > exceptions cause a SIGSEGV. > > Signed-off-by: Klye Evans > Signed-off-by: Olivier Houchard > Signed-off-by: Stacey Son > Signed-off-by: Warner Losh > --- >

Re: [PATCH 1/9] qapi: New special feature flag "unstable"

John Snow writes: > On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote: > >> By convention, names starting with "x-" are experimental. The parts >> of external interfaces so named may be withdrawn or changed >> incompatibly in future releases. >> >> Drawback: promoting something from

Re: [PATCH v3 00/22] QEMU RISC-V AIA support

Hi Alistair, On Sat, Oct 23, 2021 at 2:17 PM Anup Patel wrote: > > The advanced interrupt architecture (AIA) extends the per-HART local > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > and Advanced PLIC (wired interrupt controller). > > The latest AIA draft

Re: [RFC PATCH v4 20/20] vdpa: Add custom IOTLB translations to SVQ

On Wed, Oct 20, 2021 at 7:57 PM Eugenio Perez Martin wrote: > > On Wed, Oct 20, 2021 at 11:03 AM Jason Wang wrote: > > > > On Wed, Oct 20, 2021 at 2:52 PM Eugenio Perez Martin > > wrote: > > > > > > On Wed, Oct 20, 2021 at 4:07 AM Jason Wang wrote: > > > > > > > > On Wed, Oct 20, 2021 at 10:02

Re: [RFC PATCH v4 18/20] vhost: Add VhostIOVATree

On Thu, Oct 21, 2021 at 10:34 PM Eugenio Perez Martin wrote: > > On Thu, Oct 21, 2021 at 10:12 AM Jason Wang wrote: > > > > On Thu, Oct 21, 2021 at 3:03 PM Eugenio Perez Martin > > wrote: > > > > > > On Thu, Oct 21, 2021 at 4:34 AM Jason Wang wrote: > > > > > > > > On Wed, Oct 20, 2021 at 8:07

[PATCH v3 2/2] tests/unit: Add an unit test for smp parsing

Now that we have a generic parser smp_parse(), let's add an unit test for the code. All possible valid/invalid SMP configurations that the user can specify are covered. Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones --- MAINTAINERS | 1 + tests/unit/meson.build |

[PATCH v3 1/2] hw/core/machine: Split out the smp parsing code

We are going to introduce an unit test for the parser smp_parse() in hw/core/machine.c, but now machine.c is only built in softmmu. In order to solve the build dependency on the smp parsing code and avoid building unrelated stuff for the unit tests, move the tested code from machine.c into a

[PATCH v3 0/2] hw/core/machine: Add an unit test for smp_parse

Hi, This is v3 which introduces an unit test for generic smp_parse. We have had enough discussions about what kind of SMP configurations by the user should be considered valid and what should be invalid. Since we have finished optimizing the SMP parsing code, then this test normatively listed

Re: [PATCH v2 2/2] tests/unit: Add an unit test for smp parsing

On 2021/10/13 15:41, Yanan Wang wrote: Now that we have a generic parser smp_parse(), let's add an unit test for the code. All possible valid/invalid SMP configurations that the user can specify are covered. Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones --- MAINTAINERS

Re: Commit abb0cd93494 breaks -singlestep -d in_asm,cpu with qemu-system-sh4

On 10/25/21 2:16 PM, BALATON Zoltan wrote: Hello, Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a delay slot. Since that commit I get: pc=0xac80003e sr=0x50f1 pr=0x fpscr=0x00040001

[PATCH v5 06/26] arm: qemu: Add a devicetree file for qemu_arm64

Add this file, generated from qemu, so there is a reference devicetree in the U-Boot tree. Signed-off-by: Simon Glass --- (no changes since v1) arch/arm/dts/Makefile| 2 +- arch/arm/dts/qemu-arm64.dts | 381 +++ configs/qemu_arm64_defconfig | 1 +

[PATCH v5 07/26] riscv: qemu: Add devicetree files for qemu_riscv32/64

Add these files, generated from qemu, so there is a reference devicetree in the U-Boot tree. Split the existing qemu-virt into two, since we need a different devicetree for 32- and 64-bit machines. Signed-off-by: Simon Glass --- (no changes since v1) arch/riscv/dts/Makefile |

[PATCH v5 04/26] arm: riscv: qemu: Explain how to extract the generated dt

QEMU currently generates a devicetree for use with U-Boot. Explain how to obtain it. Also explain how to merge it to produce a devicetree with the U-Boot features included. Signed-off-by: Simon Glass --- Changes in v5: - Merge RISC-V and ARM patches since they are similar

[PATCH v5 05/26] arm: qemu: Add a devicetree file for qemu_arm

Add this file, generated from qemu, so there is a reference devicetree in the U-Boot tree. Signed-off-by: Simon Glass --- (no changes since v1) arch/arm/dts/Makefile | 2 + arch/arm/dts/qemu-arm.dts | 402 + configs/qemu_arm_defconfig | 1 + 3

[PATCH v5 00/26] fdt: Make OF_BOARD a boolean option

With Ilias' efforts we have dropped OF_PRIOR_STAGE and OF_HOSTFILE so there are only three ways to obtain a devicetree: - OF_SEPARATE - the normal way, where the devicetree is built and appended to U-Boot - OF_EMBED - for development purposes, the devicetree is embedded in the

[PATCH v5 03/26] arm: qemu: Mention -nographic in the docs

Without this option QEMU appears to hang. Add it to avoid confusion. Signed-off-by: Simon Glass --- (no changes since v1) doc/board/emulation/qemu-arm.rst | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/board/emulation/qemu-arm.rst

Re: [PATCH] hvf: arm: Ignore cache operations on MMIO

On 10/25/21 12:13 PM, Alexander Graf wrote: +/* + * We ran into an instruction that traps for data, but is not + * hardware predecoded. This should not ever happen for well + * behaved guests. Let's try to see if we can somehow rescue + * the situation. + */ + +

[PATCH] hw/arm/virt: Expose empty NUMA nodes through ACPI

The empty NUMA nodes, where no memory resides, aren't exposed through ACPI SRAT table. It's not user preferred behaviour because the corresponding memory node devices are missed from the guest kernel as the following example shows, and memory can't be hot added to these empty NUMA nodes at later

Re: [RFC 0/2] tls: add macros for coroutine-safe TLS variables

On Mon, Oct 25, 2021 at 10:18 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 10/25/21 7:07 AM, Stefan Hajnoczi wrote: > > This is a preview of how we can solve the coroutines TLS problem. > Coroutines > > re-entered from another thread sometimes see stale TLS values. This >

Re: Commit abb0cd93494 breaks -singlestep -d in_asm,cpu with qemu-system-sh4

On Mon, 25 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/25/21 23:16, BALATON Zoltan wrote: Hello, Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a delay slot. [...] However I still don't understand how

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

On Tue, 26 Oct 2021, John Paul Adrian Glaubitz wrote: Hi Zoltan! On 10/23/21 15:22, BALATON Zoltan wrote: You either need to strip the kernel with "strip vmlinux" or use the image from arch/sh/ boot/zImage. I've actually used that kernel but looked at the wrong uncompressed size, it's

Re: [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses

On Mon, Oct 25, 2021 at 2:16 PM Bin Meng wrote: > > On Mon, Oct 25, 2021 at 12:07 PM Alistair Francis > wrote: > > > > From: Alistair Francis > > > > Fixup the PLIC context address to correctly support the threshold and > > claim register. > > > > Fixes: ef63100648 ("hw/riscv: opentitan: Update

Re: [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs

On Tue, Oct 26, 2021 at 3:36 AM Alexey Baturo wrote: > > Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6b767a4a0b..16fac64806

Re: Looking for advise on debugging a non-boot kernel on qemu-system-sh4

Hi Zoltan! On 10/23/21 15:22, BALATON Zoltan wrote: >> You either need to strip the kernel with "strip vmlinux" or use the image >> from arch/sh/ >> boot/zImage. > > I've actually used that kernel but looked at the wrong uncompressed size, > it's indeed just > 9.2MB when stripped so that

Re: Commit abb0cd93494 breaks -singlestep -d in_asm,cpu with qemu-system-sh4

On 10/25/21 23:16, BALATON Zoltan wrote: > Hello, > > Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have > broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a > delay slot. [...] > However I still don't understand how the delayed branch ends up at > 0x8c800964

Commit abb0cd93494 breaks -singlestep -d in_asm,cpu with qemu-system-sh4

Hello, Commit abb0cd93494 (accel/tcg: Split out log_cpu_exec) seems to have broken -singlestep -d in_asm,cpu output with qemu-system-sh4 after a delay slot. Since that commit I get: pc=0xac80003e sr=0x50f1 pr=0x fpscr=0x00040001 spc=0x ssr=0x gbr=0x

Re: [PATCH v2] hw/i386: Rename default_bus_bypass_iommu

On Mon, Oct 25, 2021 at 11:47:38AM +0100, Jean-Philippe Brucker wrote: > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine > parameter definitions cannot use underscores, because keyval_dashify() > transforms them to dashes and the parser doesn't find the parameter. > > This

Re: [PATCH] hvf: arm: Ignore cache operations on MMIO

On 10/25/21 21:13, Alexander Graf wrote: > Apple's Hypervisor.Framework forwards cache operations as MMIO traps > into user space. For MMIO however, these have no meaning: There is no > cache attached to them. > > So let's filter SYS instructions for DATA exits out and treat them as nops. > >

[ PATCH v3 08/10] target/riscv: Add sscofpmf extension support

The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension.

[ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented

[ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function

The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Signed-off-by: Atish Patra --- target/riscv/csr.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c

Re: [PATCH 6/9] qapi: Generalize command policy checking

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > The code to check command policy can see special feature flag > 'deprecated' as command flag QCO_DEPRECATED. I want to make feature > flag 'unstable' visible there as well, so I can add policy for it. > > To let me make it visible, add

Re: [PATCH v4 04/19] host-utils: add unit tests for divu128/divs128

On 10/25/21 12:11 PM, Luis Pires wrote: Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c

Re: [PATCH 5/9] qapi: Generalize struct member policy checking

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > The generated visitor functions call visit_deprecated_accept() and > visit_deprecated() when visiting a struct member with special feature > flag 'deprecated'. This makes the feature flag visible to the actual > visitors. I want to

[PATCH v4 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Move the following instructions to decodetree: ddedpd: DFP Decode DPD To BCD ddedpdq: DFP Decode DPD To BCD Quad denbcd: DFP Encode BCD To DPD denbcdq: DFP Encode BCD To DPD Quad dscli: DFP Shift Significand Left Immediate dscliq: DFP Shift Significand Left Immediate Quad dscri: DFP Shift

Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations

On 10/25/21 8:47 AM, Philippe Mathieu-Daudé wrote: On 10/25/21 14:28, Frédéric Pétrot wrote: Addition of not, xor, div and rem on 128-bit integers, used in particular within div/rem and csr helpers for computations on 128-bit registers in the 128-bit riscv target. Signed-off-by: Frédéric

Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO

On 10/25/21 5:28 AM, Frédéric Pétrot wrote: -MO_LEQ = MO_LE | MO_Q, +MO_LEQ = MO_LE | MO_UQ, Again, I mentioned that this would require renaming as well... -MO_BEQ = MO_BE | MO_Q, +MO_BEQ = MO_BE | MO_UQ, ... and this... +MO_TEUQ = MO_TE | MO_UQ,

[PATCH v4 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Move the following instructions to decodetree: dctdp: DFP Convert To DFP Long dctqpq: DFP Convert To DFP Extended drsp:DFP Round To DFP Short drdpq: DFP Round To DFP Long dcffix: DFP Convert From Fixed dcffixq: DFP Convert From Fixed Quad dctfix: DFP Convert To Fixed dctfixq: DFP

[ PATCH v3 09/10] target/riscv: Add few cache related PMU events

Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26 ++ 1 file changed, 26

[ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 target/riscv/csr.c | 25 + target/riscv/machine.c | 5 +++--

[PATCH v4 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 8 ++---

[ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu

The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM architecture as well. Signed-off-by:

[ PATCH v3 00/10] Improve PMU support

The latest version of the SBI specification includes a Performance Monitoring Unit(PMU) extension[1] which allows the supervisor to start/stop/configure various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode

[ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents

With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 12 ++ target/riscv/csr.c | 468

[ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation

mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic

[ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for

Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Signed-off-by: Atish Patra ---

[PATCH v4 11/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 52 + target/ppc/helper.h | 1 +

Re: [PATCH v4] isa-applesmc: provide OSK forwarding on Apple hosts

On 25.10.21 17:10, Daniel P. Berrangé wrote: On Mon, Oct 25, 2021 at 04:53:57PM +0200, Alexander Graf wrote: On 25.10.21 16:47, Daniel P. Berrangé wrote: On Mon, Oct 25, 2021 at 04:42:22PM +0200, Alexander Graf wrote: On 25.10.21 16:22, Daniel P. Berrangé wrote: On Mon, Oct 25, 2021 at

[PATCH v4 10/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c | 95

Re: [PATCH 9/9] qapi: Extend -compat to set policy for unstable interfaces

On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote: > New option parameters unstable-input and unstable-output set policy > for unstable interfaces just like deprecated-input and > deprecated-output set policy for deprecated interfaces (see commit > 6dd75472d5 "qemu-options: New -compat to

[PATCH v4 09/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index a3a7ced78d..ca979dc6cc 100644 ---

Re: [PATCH 8/9] qapi: Factor out compat_policy_input_ok()

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > The code to check policy for handling deprecated input is triplicated. > Factor it out into compat_policy_input_ok() before I mess with it in > the next commit. > > Signed-off-by: Markus Armbruster > (Skipping C-only patches for quick

Re: [PATCH 7/9] qapi: Generalize enum member policy checking

On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote: > The code to check enumeration value policy can see special feature > flag 'deprecated' in QEnumLookup member flags[value]. I want to make > feature flag 'unstable' visible there as well, so I can add policy for > it. > > Instead of

[PATCH v4 07/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2fafebd1c..48a484eef6 100644 ---

Re: [PATCH 4/9] qapi: Tools for sets of special feature flags in generated code

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > New enum QapiSpecialFeature enumerates the special feature flags. > > New helper gen_special_features() returns code to represent a > collection of special feature flags as a bitset. > > The next few commits will put them to use. > >

[PATCH v4 06/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v4 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Move the following instructions to decodetree: dcmpu:DFP Compare Unordered dcmpuq: DFP Compare Unordered Quad dcmpo:DFP Compare Ordered dcmpoq: DFP Compare Ordered Quad dtstex: DFP Test Exponent dtstexq: DFP Test Exponent Quad dtstsf: DFP Test Significance dtstsfq: DFP Test

[PATCH v4 16/19] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Move the following instructions to decodetree: dquai: DFP Quantize Immediate dquaiq: DFP Quantize Immediate Quad drintx: DFP Round to FP Integer With Inexact drintxq: DFP Round to FP Integer With Inexact Quad drintn: DFP Round to FP Integer Without Inexact drintnq: DFP Round to FP Integer

[PATCH v4 05/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git

[PATCH v4 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

Move the following instructions to decodetree: dadd: DFP Add daddq: DFP Add Quad dsub: DFP Subtract dsubq: DFP Subtract Quad dmul: DFP Multiply dmulq: DFP Multiply Quad ddiv: DFP Divide ddivq: DFP Divide Quad diex: DFP Insert Biased Exponent diexq: DFP Insert Biased Exponent Quad

[PATCH] hvf: arm: Ignore cache operations on MMIO

Apple's Hypervisor.Framework forwards cache operations as MMIO traps into user space. For MMIO however, these have no meaning: There is no cache attached to them. So let's filter SYS instructions for DATA exits out and treat them as nops. This fixes OpenBSD booting as guest. Signed-off-by:

[PATCH v4 12/19] target/ppc: Do not update nip on DFP instructions

Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires --- target/ppc/translate/dfp-impl.c.inc | 8 1 file changed, 8 deletions(-) diff --git a/target/ppc/translate/dfp-impl.c.inc

[PATCH v4 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v4 04/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build

[PATCH v4 01/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v4 03/19] host-utils: add 128-bit quotient support to divu128/divs128

These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h

[PATCH v4 08/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 target/ppc/helper.h | 1 + target/ppc/insn32.decode

[PATCH v4 02/19] host-utils: move udiv_qrnnd() to host-utils

Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/fpu/softfloat-macros.h | 82 -- include/qemu/host-utils.h | 81

[PATCH v4 00/19] target/ppc: DFP instructions using decodetree

This series moves all existing DFP instructions to decodetree and implements the 2 new instructions (dcffixqq and dctfixqq) from Power ISA 3.1. In order to implement dcffixqq, divu128/divs128 were modified to support 128-bit quotients (previously, they were limited to 64-bit quotients), along

Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers

On 10/25/21 5:28 AM, Frédéric Pétrot wrote: The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas --- target/riscv/cpu.h | 2 ++

Re: [PATCH] hvf: Avoid mapping regions < PAGE_SIZE as ram

On 25.10.21 19:11, Paolo Bonzini wrote: On 25/10/21 10:25, Alexander Graf wrote: HVF has generic memory listener code that adds all RAM regions as HVF RAM regions. However, HVF can only handle page aligned, page granule regions. So let's ignore regions that are not page aligned and sized.

Re: [PATCH 3/9] qapi: Eliminate QCO_NO_OPTIONS for a slight simplification

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > Signed-off-by: Markus Armbruster > --- > include/qapi/qmp/dispatch.h | 1 - > monitor/misc.c | 3 +-- > scripts/qapi/commands.py| 5 + > 3 files changed, 2 insertions(+), 7 deletions(-) > > diff --git

Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers

On 10/25/21 5:28 AM, Frédéric Pétrot wrote: Introduction of a gen_logic function for bitwise logic to implement instructions in which not propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien

Re: [PATCH 2/9] qapi: Mark unstable QMP parts with feature 'unstable'

On Mon, Oct 25, 2021 at 1:25 AM Markus Armbruster wrote: > Add special feature 'unstable' everywhere the name starts with 'x-', > except for InputBarrierProperties member x-origin and > MemoryBackendProperties member x-use-canonical-path-for-ramblock-id, > because these two are actually stable.

Re: [PATCH v3 0/3] plugins: add a drcov plugin

NDNF writes: > These patches adds the ability to generate files in drcov format. > Primary goal this scripts is to have coverage > logfiles thatwork in Lighthouse. Queued with some fixes to plugins/next, thanks. -- Alex Bennée

Re: [PATCH 1/9] qapi: New special feature flag "unstable"

On Mon, Oct 25, 2021 at 1:26 AM Markus Armbruster wrote: > By convention, names starting with "x-" are experimental. The parts > of external interfaces so named may be withdrawn or changed > incompatibly in future releases. > > Drawback: promoting something from experimental to stable involves

RE: [PATCH v3 07/22] host-utils: add 128-bit quotient support to divu128/divs128

From: Richard Henderson > > A new argument, prem, was added to divu128/divs128 to receive the > > remainder, freeing up phigh to receive the high 64 bits of the > > quotient. > > > > Signed-off-by: Luis Pires > > Why not return the remainder? That would avoid the need for an extra > argument,

RE: [PATCH v3 16/22] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

From: Richard Henderson > On 9/10/21 4:26 AM, Luis Pires wrote: > > +_bf_fra bf fra dm > > +@Z22_bf_fra .. bf:3 .. fra:5 dm:6 . . _bf_fra > > + > > +%z22_frap 17:4 !function=times_2 > > +@Z22_bf_frap.. bf:3 .. 0 dm:6 . . _bf_fra >

RE: [PATCH v3 15/22] target/ppc: Implement DCTFIXQQ

From: Richard Henderson > > +static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src) { > > +dst->VsrD(0) = src->VsrD(0); > > +dst->VsrD(1) = src->VsrD(1); > > +} > > Given that these two are typedef of one another, I would think this is > unnecessary and you should just write *dst

Re: [PATCH] virtiofsd: Error on bad socket group name

* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote: > From: "Dr. David Alan Gilbert" > > Make the '--socket-group=' option fail if the group name is unknown: > > ./tools/virtiofsd/virtiofsd --socket-group=zaphod > vhost socket: unable to find group 'zaphod' > > Reported-by:

Re: [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

On 10/25/21 10:36 AM, Alexey Baturo wrote: +/* User Pointer Masking */ +[CSR_UMTE]={ "umte",pointer_masking, read_umte,write_umte }, +[CSR_UPMMASK] ={ "upmmask", pointer_masking, read_upmmask, write_upmmask }, +[CSR_UPMBASE] ={ "upmbase",

Re: [Virtio-fs] [PATCH] virtiofsd: Error on bad socket group name

* Vivek Goyal (vgo...@redhat.com) wrote: > On Thu, Oct 14, 2021 at 01:25:54PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > Make the '--socket-group=' option fail if the group name is unknown: > > > > ./tools/virtiofsd/virtiofsd --socket-group=zaphod

Re: [PATCH v3 34/48] tcg/optimize: Split out fold_to_not

On 10/25/21 11:13 AM, Luis Fernando Fujita Pires wrote: From: Richard Henderson static bool fold_eqv(OptContext *ctx, TCGOp *op) { -return fold_const2(ctx, op); +if (fold_const2(ctx, op) || +fold_xi_to_not(ctx, op, 0)) { Should be fold_ix_to_not (not fold xi_to_not).

RE: [PATCH v3 34/48] tcg/optimize: Split out fold_to_not

From: Richard Henderson > >> static bool fold_eqv(OptContext *ctx, TCGOp *op) { > >> -return fold_const2(ctx, op); > >> +if (fold_const2(ctx, op) || > >> +fold_xi_to_not(ctx, op, 0)) { > > > > Should be fold_ix_to_not (not fold xi_to_not). > > No, because for eqv we expect

Re: [PATCH 00/13] virtiofsd: Support notification queue and

* Vivek Goyal (vgo...@redhat.com) wrote: > Hi, > > Here are the patches to support notification queue and blocking > posix locks. One of the biggest change since las time has been > creation of custom thread pool for handling locking requests. > Thanks to Ioannis for doing most of the work on

Re: [PATCH] virtiofsd: xattr mapping add a new type "unsupported"

* Vivek Goyal (vgo...@redhat.com) wrote: > Right now for xattr remapping, we support types of "prefix", "ok" or "bad". > Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For > getxattr, mapping code returns -EPERM but getxattr code converts it to > -ENODATA. > > I need a new

[PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ target/riscv/translate.c | 39 +-- 3 files

[PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 285 + 3 files changed, 298 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c

Re: [PATCH v3 36/48] tcg/optimize: Split out fold_xi_to_x

On 10/25/21 7:26 AM, Luis Fernando Fujita Pires wrote: You missed adding 'fold_xi_to_x(ctx, op, -1)' to fold_orc() in this commit. It ended up being added in patch 42, but it should be here. Oops, yes. And should we use fold_xi_to_x() to optimize multiply and divide when i==1, too? A good

[PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 96 + 1 file changed, 96 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index cffcd3a5df..aa0bce4e06 100644 ---

[PATCH v17 4/8] target/riscv: Add J extension state description

Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/machine.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index f64b2a96c1..7b4c739564 100644 --- a/target/riscv/machine.c +++

[PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++

[PATCH v17 1/8] target/riscv: Add J-extension into RISC-V

Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h +++

[PATCH v17 0/8] RISC-V Pointer Masking implementation

v16: Rebased against the latest tree v15: Renamed pm into pointer_masking in machine state. v14: Addressed Richard's comments from previous series. v13: Rebased QEMU and addressed Richard's comment. v12: Updated function for adjusting address with pointer masking to allocate and use temp

[PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b767a4a0b..16fac64806 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -271,6 +271,13 @@ static void

Re: [PATCH v3 34/48] tcg/optimize: Split out fold_to_not

On 10/25/21 7:17 AM, Luis Fernando Fujita Pires wrote: From: Richard Henderson Split out the conditional conversion from a more complex logical operation to a simple NOT. Create a couple more helpers to make this easy for the outer-most logical operations. Signed-off-by: Richard Henderson

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