Changes for v6:
* Fix rebase error wrt xn bit extract.
Changes for v5:
* Rebase, including 12 patches.
* Add regime_is_stage2, which I should have done ages ago.
* Reorg attribute extraction/merging vs descriptor modifications.
Patches lacking review:
On Sat, Oct 22, 2022 at 8:41 AM Richard Henderson
wrote:
>
> On Sat, 22 Oct 2022, 08:33 Laurent Vivier, wrote:
>>
>> Le 17/10/2022 à 22:29, Jason A. Donenfeld a écrit :
>>
>>
>> Notes:
>> - don't send your patch as a reply to a previous version
>> - add an history:
>>
>> v4: replace (void
On 22/10/22 17:04, Bernhard Beschow wrote:
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Guohuai Shi
At present there is no Windows support for 9p file system.
This commit adds initial Windows support for 9p file system.
'local' file system backend driver is supported on Windows,
including open, read, write, close, rename, remove, etc.
All security models are supported. The
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Eric Auger
Reviewed-by: Cornelia Huck
Tested-by:
On 22/10/22 17:04, Bernhard Beschow wrote:
This commit marks the finalization of the PIIX3 preparations
to be merged with PIIX4. In particular, PIIXState is prepared
to be reused in piix4.c.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c| 58
On Mon, Oct 17, 2022 at 3:52 PM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> This patch series implements a `FIELDx_1CLEAR()` macro and implements it
> in the `hw/ssi/ibex_spi.c` model.
>
> *** Changelog ***
> Since v2:
> - change the macro arguments name to
Am 18. Oktober 2022 21:01:39 UTC schrieb Bernhard Beschow :
>Cover letter:
>
>~
>
>
>
>This series adds support for -pflash and direct SD card access to the
>
>PPC e500 boards. The idea is to increase compatibility with "real" firmware
>
>images where only the bare minimum of drivers
Le 23/09/2022 à 14:00, Markus Armbruster a écrit :
Signed-off-by: Markus Armbruster
---
bsd-user/elfload.c | 2 +-
contrib/plugins/cache.c | 8
contrib/vhost-user-blk/vhost-user-blk.c | 2 +-
hw/core/qdev-clock.c| 2 +-
Having a common base class allows for substituting PIIX3 with PIIX4
and vice versa. Moreover, it makes PIIX4 implement the
acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix.c | 53 +++
1 file changed, 24 insertions(+), 29
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is disabled by developer by
toggling
Rename macro name to more transparent one and refactor
it to expression.
Signed-off-by: Nikita Ivanov
---
chardev/char-fd.c | 2 +-
chardev/char-pipe.c| 8 +---
include/qemu/osdep.h | 8 +++-
net/tap-bsd.c | 6 +++---
net/tap-linux.c| 2 +-
net/tap-solaris.c
Leave the upper and lower attributes in the place they originate
from in the descriptor. Shifting them around is confusing, since
one cannot read the bit numbers out of the manual. Also, new
attributes have been added which would alter the shifts.
Reviewed-by: Peter Maydell
Signed-off-by:
On Fri, Oct 21, 2022 at 5:05 PM Eugenio Perez Martin
wrote:
>
> On Fri, Oct 21, 2022 at 5:02 AM Jason Wang wrote:
> >
> > On Thu, Oct 20, 2022 at 3:01 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Thu, Oct 20, 2022 at 6:35 AM Jason Wang wrote:
> > > >
> > > > On Wed, Oct 19, 2022 at 8:52
From: Guohuai Shi
We don't plan to support 'proxy' file system driver for 9pfs on
Windows. Disable it for Windows build.
Signed-off-by: Guohuai Shi
Signed-off-by: Bin Meng
---
fsdev/qemu-fsdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/fsdev/qemu-fsdev.c b/fsdev/qemu-fsdev.c
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performing it only once.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 71
Introduce an opaque type to represent a file in the 9pfs. This is
file descriptor on POSIX systems. In the upcoming patches, we can
extend it to support Windows.
With this new opaque type, it significantly reduces the number of
deviated code paths when adding Windows support.
Signed-off-by: Bin
On 22/10/22 17:04, Bernhard Beschow wrote:
While at it, move the assignments closer to where they are used.
Signed-off-by: Bernhard Beschow
---
hw/mips/malta.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
At present there is no Windows support for 9p file system.
This series adds initial Windows support for 9p file system.
'local' file system backend driver is supported on Windows,
including open, read, write, close, rename, remove, etc.
All security models are supported. The mapped (mapped-xattr)
From: Guohuai Shi
Windows POSIX API and MinGW library do not provide the NO_FOLLOW
flag, and do not allow opening a directory by POSIX open(). This
causes all xxx_at() functions cannot work directly. However, we
can provide Windows handle based functions to emulate xxx_at()
functions (e.g.:
This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by:
Hi team,
I am an outreachy applicant and I would like to know how I can make my
first contribution and what the contribution should be.
Best Regards,
Wilberforce
From: Guohuai Shi
Enable virtfs configuration option for Windows host.
Signed-off-by: Guohuai Shi
Signed-off-by: Bin Meng
---
meson.build | 10 +-
fsdev/meson.build | 1 +
hw/9pfs/meson.build | 8 +---
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git
On Windows P9_FILE_ID points to a file handle.
Signed-off-by: Bin Meng
---
hw/9pfs/9p-file-id.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/9pfs/9p-file-id.h b/hw/9pfs/9p-file-id.h
index 60cbfbf4dd..00903048e6 100644
--- a/hw/9pfs/9p-file-id.h
+++
At the moment, TFR() macro has a vague name and is not used
where it possibly could be. In order to make it more transparent
and useful, it was decided to refactor it to make it closer to
the similar one in glibc: TEMP_FAILURE_RETRY(). Now, macro
evaluates into an expression and is named
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is likely to be disabled by
code by
On Tue, 2022-10-18 at 16:41 +0800, Sam Li wrote:
> Dmitry Fomichev 于2022年10月17日周一 08:57写道：
> >
> > On Sun, 2022-10-16 at 22:51 +0800, Sam Li wrote:
> > > We have added new block layer APIs of zoned block devices.
> > > Test it with:
> > > Create a null_blk device, run each zone operation on it
On Wed, Oct 12, 2022 at 4:01 PM LIU Zhiwei wrote:
>
> Only the pmp index that be checked by pmp_hart_has_privs can be used
> by pmp_get_tlb_size to avoid an error pmp index.
>
> Before modification, we may use an error pmp index. For example,
> we check address 0x4fc, and the size 0x4 in
On Sun, Oct 23, 2022 at 10:46 PM Cindy Lu wrote:
>
> On Thu, 20 Oct 2022 at 10:15, Jason Wang wrote:
> >
> > On Wed, Oct 19, 2022 at 2:39 PM Cindy Lu wrote:
> > >
> > > Add support for vIOMMU. Register a memory listener to dma_as in
> > > dev_start
> > > - during region_add register a specific
On Sat, Oct 22, 2022 at 22:15 Michael S. Tsirkin wrote:
> On Fri, Oct 21, 2022 at 09:47:04PM +0530, Ani Sinha wrote:
> >
> >
> > On Fri, Oct 21, 2022 at 21:36 Alex Bennée
> wrote:
> >
> >
> > Ani Sinha writes:
> >
> >
> > >
> > > We have added a mirror of biosbits to the QEMU
On 10/21/22 21:09, BALATON Zoltan wrote:
On Fri, 21 Oct 2022, Daniel Henrique Barboza wrote:
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
new file mode 100644
index 00..b49a7ed60a
--- /dev/null
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -0,0 +1,348 @@
+/*
+ * DDR2 SDRAM controller:
Rather than poking directly into RAM, add the bootinfo block as a proper
ROM, so that it's restored when rebooting the system. This way, if the
guest corrupts any of the bootinfo items, but then tries to reboot,
it'll still be restored back to normal as expected.
Then, since the RNG seed needs to
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 3 ++-
hw/ide/piix.c | 5 +++--
hw/isa/piix4.c| 3 ++-
include/hw/ide/piix.h | 7 +++
4 files changed, 14 insertions(+), 4 deletions(-)
create mode 100644 include/hw/ide/piix.h
diff
On 10/24/22 01:36, tobias.roeh...@rwth-aachen.de wrote:
From: Tobias Röhmel
Typo "implement" in subject.
@@ -8038,6 +8035,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa64_tid1,
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
On Mon, Oct 17, 2022 at 3:55 PM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> use the `FIELD32_1CLEAR` macro to implement register
> `rw1c` functionality to `ibex_spi`.
>
> This change was tested by running the `SPI_HOST` from TockOS.
>
> Signed-off-by: Wilfred Mallawa
Reviewed-by:
More closely follow the default linker script for nios2.
This magically fixes a problem resolving .got relocs from
the toolchain's libgcc.a.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258
Signed-off-by: Richard Henderson
---
tests/tcg/nios2/10m50-ghrd.ld | 14 +-
1
Le 17/10/2022 à 15:20, Bin Meng a écrit :
From: Bin Meng
When tmpfs is NULL, a build warning is seen with GCC 9.3.0.
It's strange that GCC 11.2.0 on Ubuntu 22.04 does not catch this,
neither did the QEMU CI.
While we are here, improve the error message as well.
Reported-by: Shengjiang Wu
Use the newly introduced i8259 proxy "isa-pic" which allows for wiring
up devices in the southbridge where the virtualization technology used
(KVM, TCG, Xen) is not yet known.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 15 +--
hw/isa/Kconfig|
Typo "calculation" in subject.
On 22/10/22 08:12, Qi Hu wrote:
In sequence:
---
lock negl -0x14(%rbp)
pushf
pop%rax
---
%rax will obtain the wrong value becasue the "lock neg" caculates the
wrong eflags. The "s->T0" is updated by the wrong value.
You can use this to do some test:
---
In the ACPI specification [1], the 'unarmed' bit is set when a device
cannot accept a persistent write. This means that when a memdev is
read-only, the 'unarmed' flag must be turned on. The logic is correct,
just changing the error message.
[1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM
On Wed, Oct 12, 2022 at 4:01 PM LIU Zhiwei wrote:
>
> Only the pmp index that be checked by pmp_hart_has_privs can be used
> by pmp_get_tlb_size to avoid an error pmp index.
>
> Before modification, we may use an error pmp index. For example,
> we check address 0x4fc, and the size 0x4 in
These 3 high memory regions are usually enabled by default, but
they may be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't
needed by GICv2. This leads to waste in the PA space.
Add properties to allow users selectively disable them if needed:
"highmem-redists", "highmem-ecam", "highmem-mmio".
On Sat, Oct 22, 2022 at 22:11 Michael S. Tsirkin wrote:
> On Fri, Oct 21, 2022 at 05:12:07PM +0530, Ani Sinha wrote:
> >
> >
> > On Fri, Oct 21, 2022 at 13:50 Michael S. Tsirkin wrote:
> >
> > On Fri, Oct 21, 2022 at 05:10:43AM +0530, Ani Sinha wrote:
> > >
> > >
> > > On Fri,
The next patches will need to take advantage of it.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
---
hw/i386/pc_piix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 7a55b9ca8e..5caef9bfc9 100644
---
On Sat, Oct 22, 2022 at 22:05 Michael S. Tsirkin wrote:
> On Sat, Oct 22, 2022 at 06:28:32AM +0530, Ani Sinha wrote:
> >
> >
> > On Fri, Oct 21, 2022 at 21:32 Alex Bennée
> wrote:
> >
> >
> > Ani Sinha writes:
> >
> > > On Fri, 21 Oct, 2022, 5:52 pm Ani Sinha, wrote:
> > >
> >
On Fri, Oct 21, 2022 at 4:15 PM Michael S. Tsirkin wrote:
>
> On Fri, Oct 21, 2022 at 09:45:14AM +0200, Eugenio Perez Martin wrote:
> > On Fri, Oct 21, 2022 at 5:40 AM Jason Wang wrote:
> > >
> > > On Thu, Oct 20, 2022 at 11:53 PM Eugenio Pérez
> > > wrote:
> > > >
> > > > Actually use the new
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 10/21/22 11:21, Matheus Ferst wrote:
This version fixes the problems found by Daniel with e500 tests and
rebases on ppc-next.
Based-on: https://gitlab.com/danielhb/qemu/-/tree/ppc-next
Matheus Ferst (3):
target/ppc:
There is a defined RETRY_ON_EINTR() macro in qemu/osdep.h
which handles the same while loop.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/415
Signed-off-by: Nikita Ivanov
---
block/file-posix.c| 37 -
chardev/char-pty.c| 4 +---
Le 20/10/2022 à 14:12, Markus Armbruster a écrit :
Could this go via qemu-trivial now?
Yes, sorry for the delay.
I think there is a problem with PATCH 3.
Thanks,
Laurent
Now that PIIX4 also uses the "isa-pic" proxy, both implementations
can share the same struct.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 61 --
1 file changed, 19 insertions(+), 42 deletions(-)
diff --git a/hw/isa/piix4.c
Both implementations are the same and will be shared upon merging.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index a7d52c5294..2f5b6fc934 100644
--- a/hw/isa/piix4.c
+++
Aligns the code with PIIX3 such that PIIXState can be used in PIIX4,
too.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 28 ++--
hw/mips/malta.c | 11 +--
2 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
This aligns PIIX4 with PIIX3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 44
hw/mips/malta.c | 6 --
2 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index a7389ff193..fc698c23be 100644
From: Tobias Röhmel
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel
---
target/arm/cpu.c| 6 +-
target/arm/helper.c | 23
On Fri, Oct 21, 2022 at 09:47:04PM +0530, Ani Sinha wrote:
>
>
> On Fri, Oct 21, 2022 at 21:36 Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
>
> >
> > We have added a mirror of biosbits to the QEMU project so there is no
> > reason why we can't track changes and
When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.
Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the register usage clear.
Set
Fixes the "extra-semi" clang-tidy check.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 44a9998752..04895ce2e5
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 8dbf22eaab..5214a75891 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -156,7 +156,7 @@ static void
On 22/10/22 17:04, Bernhard Beschow wrote:
Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Le 28/09/2022 à 11:03, dinglimin a écrit :
Jump statements, such as return and continue let you
change the default flow of program execution,
but jump statements that direct the control flow to
the original direction are just a waste of keystrokes.
Signed-off-by: dinglimin
---
On 21/10/22 17:51, Alex Bennée wrote:
We used to rely on QEMU_CFLAGS to expose the debug flags but now this
is synthesised by meson and only available to the main build. Add our
own flags if we detect the build has been enabled with
CONFIG_DEBUG_TCG (which is the default for --enable-debug
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c| 8
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git
Dmitry Fomichev 于2022年10月23日周日 10:08写道：
>
> On Tue, 2022-10-18 at 16:56 +0800, Sam Li wrote:
> > Dmitry Fomichev 于2022年10月17日周一 09:01写道：
> > >
> > > On Sun, 2022-10-16 at 23:05 +0800, Sam Li wrote:
> > > > This patch extends virtio-blk emulation to handle zoned device commands
> > > > by calling
'make check-avocado' will download any images that aren't present in the
cache via 'get-vm-images' in tests/Makefile.include. The target that
downloads fedora 31 images, get-vm-image-fedora-31, will use 'avocado
vmimage get --distro=fedora --distro-version=31 --arch=(...)' to
download the image
I agree. Here is the corrected patch.
Signed-off-by: Christopher Wrogg
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1251
---
target/mips/tcg/octeon.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
This commit marks the finalization of the PIIX3 preparations
to be merged with PIIX4. In particular, PIIXState is prepared
to be reused in piix4.c.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c| 58 +--
include/hw/southbridge/piix.h | 4 +--
On 10/23/22 22:41, LIU Zhiwei wrote:
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-tcg_out_ext32u(s, base, addr_regl);
-addr_regl = base;
+tcg_out_ext32u(s, addr_regl, addr_regl);
}
Incorrect. You may not modify input registers.
r~
Having an i8259 proxy allows for ISA PICs to be created and wired up in
southbridges. This is especially interesting for PIIX3 for two reasons:
First, the southbridge doesn't need to care about the virtualization
technology used (KVM, TCG, Xen) due to in-IRQs (where devices get
attached) and
Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 59599558a1..aa32f43e4a 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -32,7 +32,6 @@
Hi!
Thanks for clarification! Corrected it in v4.
On Wed, Oct 19, 2022 at 6:24 PM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Tuesday, October 18, 2022 10:43:41 AM CEST Nikita Ivanov wrote:
> > There is a defined RETRY_ON_EINTR() macro in qemu/osdep.h
> > which handles the same
Rather than registering the reset handler via a function which
appends the handler to a global list, prefer to implement it as
a virtual method - PIIX4 does the same already.
Note that this means that piix3_reset can now also be called writing to
the relevant configuration space register on a PCI
On 21/10/22 18:34, Peter Maydell wrote:
Commit a82fd5a4ec24d was intended to be a code cleanup, but
unfortunately it has a bug. It moves the initialization of the
TCG cflags from the "start a new vcpu" function to the
thread handler; this is fine when each vcpu has its own thread,
but when we
Test if the audio subsystem can handle extreme up- and down-
sampling ratios like 44100/1 and 1/44100. For some time these
used to trigger QEMU aborts. The test was taken from
https://gitlab.com/qemu-project/qemu/-/issues/71 where it was
used to demonstrate a very different issue.
Suggested-by:
Prefixing with "piix4_" makes the method distinguishable from its
PIIX3 counterpart upon merging and also complies more with QEMU
conventions.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c
Resolving the PIIX ISA bridge rather than the PIIX ACPI controller mirrors
the ICH9 code one line below.
Signed-off-by: Bernhard Beschow
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index
PIIX4 will get the same optimizations which are already implemented for
PIIX3.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index
The Malta board, which is the only user of PIIX4, doesn't connect to the
exported interrupt lines.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 57b0b98bef..d65f486008 100644
---
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 9de7287589..8dbf22eaab 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -381,7 +381,7 @@ static void pci_piix3_init(Object *obj)
Now that the PIIX3 and PIIX4 device models are sufficiently consolidated
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 6 +-
configs/devices/mips-softmmu/common.mak | 2 +-
hw/i386/Kconfig | 2 +-
hw/isa/Kconfig
Speeds up PIIX4 which resolves an old TODO.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix.c | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 446105a7a1..4ced9995f9 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
Le 23/09/2022 à 14:00, Markus Armbruster a écrit :
Signed-off-by: Markus Armbruster
---
hw/core/sysbus-fdt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c
index edb0c49b19..eebcd28f9a 100644
--- a/hw/core/sysbus-fdt.c
+++
PIIX3 clears its reset control register, so do the same in PIIX4.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 83b50c3a9b..4b8dece257 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -140,6
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 1 -
hw/isa/Kconfig | 6 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/configs/devices/mips-softmmu/common.mak
b/configs/devices/mips-softmmu/common.mak
index
From: Tobias Röhmel
Add PMSAv8r translation.
Signed-off-by: Tobias Röhmel
---
target/arm/ptw.c | 130 +++
1 file changed, 110 insertions(+), 20 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4bd7389fa9..a5d890c09a 100644
---
From: Tobias Röhmel
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2
tests/vm: update openbsd to release 7.2
Signed-off-by: Brad Smith
---
tests/vm/openbsd | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index 6f1b6f5b98..eaeb201e91 100755
--- a/tests/vm/openbsd
+++ b/tests/vm/openbsd
@@ -22,8 +22,8
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges and is an extended version of [1]. The motivation is to share as much
code as possible and to bring both device models to feature parity such that
perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc
Le 23/09/2022 à 14:00, Markus Armbruster a écrit :
These memory allocation functions return void *, and casting to
another pointer type is useless clutter. Drop these casts.
If you really want another pointer type, consider g_new().
Signed-off-by: Markus Armbruster
---
hw/arm/nseries.c
Hi!
Thanks for mentioning the issue. Corrected it in v4.
On Wed, Oct 19, 2022 at 6:40 PM Christian Schoenebeck <
qemu_...@crudebyte.com> wrote:
> On Dienstag, 18. Oktober 2022 10:43:40 CEST Nikita Ivanov wrote:
> > Rename macro name to more transparent one and refactor
> > it to expression.
> >
On Tue, 2022-10-18 at 16:56 +0800, Sam Li wrote:
> Dmitry Fomichev 于2022年10月17日周一 09:01写道：
> >
> > On Sun, 2022-10-16 at 23:05 +0800, Sam Li wrote:
> > > This patch extends virtio-blk emulation to handle zoned device commands
> > > by calling the new block layer APIs to perform zoned device I/O
Le 17/10/2022 à 15:20, Bin Meng a écrit :
From: Bin Meng
When tmpfs is NULL, a build warning is seen with GCC 9.3.0.
It's strange that GCC 11.2.0 on Ubuntu 22.04 does not catch this,
neither did the QEMU CI.
While we are here, improve the error message as well.
Reported-by: Shengjiang Wu
On 2022/10/22 17:58, Richard Henderson wrote:
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
---
PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to
allow the reset
Now that the RTC is created as part of the southbridges it doesn't need
to be an out-parameter any longer.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
---
hw/i386/pc.c | 12 ++--
hw/i386/pc_piix.c| 2 +-
hw/i386/pc_q35.c | 2 +-
include/hw/i386/pc.h |
Just like in the real hardware (and in PIIX4), create the RTC
controllers in the south bridges.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc.c | 12 +++-
hw/i386/pc_piix.c | 8
hw/i386/pc_q35.c | 1 +
hw/isa/Kconfig|
According to the PIIX3 datasheet, the reset control register is one byte in
size.
Moreover, PIIX4 has it, so add it to PIIX3 as well.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow
---
There is no need for having different names here. Having the same name
further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index
While at it, move the assignments closer to where they are used.
Signed-off-by: Bernhard Beschow
---
hw/mips/malta.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 0e932988e0..0ec2ac2eaf 100644
--- a/hw/mips/malta.c
+++
Le 07/10/2022 à 04:01, luzhipeng a écrit :
From: lu zhipeng
The 'kdgb' is allocating memory in get_kdbg(), but it is not freed in
error path. So fix that.
Signed-off-by: lu zhipeng
---
contrib/elf2dmp/main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/contrib/elf2dmp/main.c
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