On 24/01/2023 19.01, Alex Bennée wrote:
This affects both system and user mode emulation so we should probably
list it up front.
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- HPs -> HP's
- MIPs-like -> MIPS-like
---
docs/about/emulation.rst | 103
On 24/01/2023 19.01, Alex Bennée wrote:
Drop the frankly misleading quickstart section for a more rounded
introduction section. This new section gives an overview of the
accelerators as well as a high level introduction to some of the key
features of the emulator. We also expand on a general
On 24/01/2023 19.01, Alex Bennée wrote:
The up-coming upgrade to Fedora 37 will bring in libtcmalloc as a
dependency of libglusterfs which confuses our fuzz run. Rather than
disable the build lets use LSAN's suppression mechanism to prevent the
job from failing.
Signed-off-by: Alex Bennée
Cc:
On 2023/01/25 1:12, Peter Maydell wrote:
On Thu, 1 Dec 2022 at 10:33, Akihiko Odaki wrote:
Before this change, write_kvmstate_to_list() and
write_list_to_kvmstate() tolerated even if it failed to access some
register, and returned a bool indicating whether one of the register
accesses failed.
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 513
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 2 +-
target/hexagon/op_helper.h
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/Makefile.target
b/tests/tcg/hexagon/Makefile.target
index 18e6a5969e..f753b39d91
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 20
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git
Extend the analyze_ functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
We create a new generator that creates an analyze_ function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_ function for
each instruction in the
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew Predicated false (new value)
Signed-off-by:
The idef-parser skips the change-of-flow (COF) instructions, so add
overrides
Changes in v2
Add a new generator for analyze_ instructions. Pouplate the
DisasContext ahead of generating code.
Changes in v3
Cleanup of analysis code
Added test updates enabled by new toolchain
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4 ++
target/hexagon/genptr.c | 79
2 files changed, 83 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 9e8f3373ad..6267f51ccc 100644
---
The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
Reduce the cases where gen_log_vreg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
Here is a simple
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly
handle -0. Previously we would negate the input operand by subtracting
from zero. Instead, we negate by changing the sign bit.
Test case added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
---
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/preg_alias.c
From: Maksim Davydov
Current 256KB is not enough for some real cases. As a possible solution
limit can be chosen to be the same as libvirt (10MB)
Signed-off-by: Maksim Davydov
Reviewed-by: John Snow
Message-id: 20230112152805.33109-3-davydov-...@yandex-team.ru
Signed-off-by: John Snow
---
From: Marc-André Lureau
When no monitor address is given, establish the QMP communication through
a socketpair() (API is also supported on Windows since Python 3.5)
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-id: 20230111080101.969151-4-marcandre.lur...@redhat.com
From: Vladimir Sementsov-Ogievskiy
I've spent much time trying to debug hanging pipeline in gitlab. I
started from and idea that I have problem in code in my series (which
has some timeouts). Finally I found that the problem is that I've used
QEMUMachine class directly to avoid qtest, and didn't
From: Marc-André Lureau
Teach QEMUMonitorProtocol to accept an exisiting socket.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-id: 20230111080101.969151-3-marcandre.lur...@redhat.com
Signed-off-by: John Snow
---
python/qemu/qmp/legacy.py | 18 +++---
1
From: Marc-André Lureau
Instead of listening for incoming connections with a SocketAddr, add a
new method open_with_socket() that accepts an existing socket.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-id: 20230111080101.969151-2-marcandre.lur...@redhat.com
From: Peter Delevoryas
On macOS, private $TMPDIR's are the default. These $TMPDIR's are
generated from a user's unix UID and UUID [1], which can create a
relatively long path:
/var/folders/d7/rz20f6hd709c1ty8f6_6y_z4gn/T/
QEMU's avocado tests create a temporary directory prefixed by
From: Dongdong Zhang
Fix some typos in 'python' directory.
Signed-off-by: Dongdong Zhang
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221130015358.6998-2-zhangdongd...@eswincomputing.com
[Fixed additional typo spotted by Max Filippov. --js]
Reviewed-by: John Snow
Signed-off-by: John
The following changes since commit 13356edb87506c148b163b8c7eb0695647d00c2a:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2023-01-24 09:45:33 +)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/python-pull-request
for
+ qemu-devel
On Tue, 24 Jan 2023 at 15:22, Naresh Kamboju wrote:
>
> On Mon, 23 Jan 2023 at 15:22, Greg Kroah-Hartman
> wrote:
> >
> > This is the start of the stable review cycle for the 5.10.165 release.
> > There are 98 patches in this series, all will be posted as a response
> > to this
On 24/1/23 19:39, Siddhi Katage wrote:
From: Siddhi Katage
An old running QEMU will try to load modules with new build-id first, this
will fail as expected, then QEMU will fallback to load the old modules that
You corrected the comma/space typo :)
matches its build-id from /var/run/qemu/
On Tue, Jan 24, 2023, Liam Merwick wrote:
> On 14/01/2023 00:37, Sean Christopherson wrote:
> > On Fri, Dec 02, 2022, Chao Peng wrote:
> > > This patch series implements KVM guest private memory for confidential
> > > computing scenarios like Intel TDX[1]. If a TDX host accesses
> > >
On 17/1/23 23:08, Peter Xu wrote:
Without it, we never have CONFIG_LINUX defined even if on linux, so
linux/mman.h is never really included.
Signed-off-by: Peter Xu
---
util/mmap-alloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 25/1/23 00:20, Richard Henderson wrote:
Use the macro instead of two explicit string literals.
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 3 ++-
hw/arm/virt.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/1/23 03:36, Richard Henderson wrote:
This enables allocation of i128. The type is not yet
usable, as we have not yet added data movement ops.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 32 +
tcg/tcg.c | 60
On 8/1/23 03:36, Richard Henderson wrote:
We are about to allow passing Int128 to/from tcg helper functions,
but libffi doesn't support __int128_t, so use the structure.
In order for atomic128.h to continue working, we must provide
a mechanism to frob between real __int128_t and the structure.
On 8/1/23 03:36, Richard Henderson wrote:
Begin staging in support for TCGv_i128 with Int128.
Define the type enumerator, the typedef, and the
helper-head.h macros.
This cannot yet be used, because you can't allocate
temporaries of this new type.
Signed-off-by: Richard Henderson
---
Use the macro instead of two explicit string literals.
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 3 ++-
hw/arm/virt.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 4bb444684f..8378441dbb 100644
---
On 1/24/23 07:19, Markus Armbruster wrote:
Signed-off-by: Markus Armbruster
Reviewed-by: Stefan Berger
On 1/24/23 07:19, Markus Armbruster wrote:
This moves these commands from MAINTAINERS section "Human
Monitor (HMP)" to "TPM".
Signed-off-by: Markus Armbruster
Reviewed-by: Stefan Berger
---
MAINTAINERS| 2 +-
monitor/hmp-cmds.c | 54
On Tue, Jan 24, 2023 at 04:36:20PM -0500, Peter Xu wrote:
> On Tue, Jan 24, 2023 at 01:20:37PM +, Dr. David Alan Gilbert wrote:
> > > @@ -3970,7 +3984,8 @@ int ram_load_postcopy(QEMUFile *f, int channel)
> > > break;
> > > }
> > >
On 1/7/23 16:36, Richard Henderson wrote:
Patches requiring review:
01-tcg-Define-TCG_TYPE_I128-and-related-helper-macro.patch
02-tcg-Handle-dh_typecode_i128-with-TCG_CALL_-RET-AR.patch
03-tcg-Allocate-objects-contiguously-in-temp_allocat.patch
On 1/10/23 13:12, Mark Cave-Ayland wrote:
Now that the TCG documentation is more visible, would it be possible to add a patch to
update the relevant parts of docs/devel/tcg-ops.rst to reflect the new Int128 support?
For avoidance of doubt, this document covers the intermediate representation
On Tue, Jan 24, 2023 at 01:20:37PM +, Dr. David Alan Gilbert wrote:
> > @@ -3970,7 +3984,8 @@ int ram_load_postcopy(QEMUFile *f, int channel)
> > break;
> > }
> > tmp_page->target_pages++;
> > -matches_target_page_size = block->page_size
On 1/24/23 09:59, Christoph Muellner wrote:
+++ b/target/riscv/cpu.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "qemu/int128.h"
#include "cpu_bits.h"
+#include "cpu_vendorid.h"
I don't see that this ID is required for all users of riscv/cpu.h.
This include should be limited to
Hi,
These are the last 3 patches from the series
"[PATCH v3 0/7] riscv: fdt related cleanups"
That can be sent in separate from the fdt work. Patches are all acked.
Changes from v3:
- patches 1,2,3:
- former patches 5, 6 and 7 from "[PATCH v3 0/7] riscv: fdt related cleanups"
- v3 link:
Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instances where we're calling it 'mc'.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/spike.c | 18
riscv_socket_count() returns either ms->numa_state->num_nodes or 1
depending on NUMA support. In any case the value can be retrieved only
once and used in the rest of the function.
This will also alleviate the rename we're going to do next by reducing
the instances of MachineState 'mc' inside
We have a convention in other QEMU boards/archs to name MachineState
pointers as either 'machine' or 'ms'. MachineClass pointers are usually
called 'mc'.
The 'virt' RISC-V machine has a lot of instances where MachineState
pointers are named 'mc'. There is nothing wrong with that, but we gain
more
On 1/24/23 09:59, Christoph Muellner wrote:
+/* XTheadMemIdx */
+
+/*
+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the load address is rs1.
+ * If preinc, then the load address is rs1 + (imm5) << imm2).
+ */
+static bool gen_load_inc(DisasContext
On Tue, Jan 24, 2023 at 12:45:38PM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > Add a new cap to allow mapping hugetlbfs backed RAMs in small page sizes.
> >
> > Signed-off-by: Peter Xu
>
>
> Reviewed-by: Dr. David Alan Gilbert
Thanks.
>
> although, I'm
> On Jan 4, 2023, at 2:59 PM, BALATON Zoltan wrote:
>
> Setting emulated machine type with a property called "via" is
> confusing users so deprecate the "via" option in favour of newly added
> explicit machine types. The default via=cuda option is not a valid
> config (no real Mac has this
On Thu, Dec 22, 2022 at 6:29 PM Mauro Matteo Cascella
wrote:
>
> Local variable "name" is allocated through strdup_printf and should be
> freed with g_free() to avoid memory leak.
>
> Fixes: 3616f424 ("nubus-device: add romfile property for loading declaration
> ROMs")
> Signed-off-by: Mauro
On Tue, Jan 24, 2023 at 10:06:48AM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > Add a helper to do mmap() for a ramblock based on the cached informations.
> >
> > A trivial thing to mention is we need to move ramblock->fd setup to be
> > earlier, before the
On 1/24/23 09:59, Christoph Muellner wrote:
+static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+int shamt)
+{
+TCGv rd1 = dest_gpr(ctx, a->rd1);
+TCGv rd2 = dest_gpr(ctx, a->rd2);
+TCGv addr1 = tcg_temp_new();
+TCGv addr2 =
Hi Christoph,
On Wed, Feb 16, 2022 at 04:48:37PM +0100, Christoph Muellner wrote:
> The RISC-V base cache management operation ISA extension has been
> ratified [1]. This patchset adds support for the defined instructions.
>
> As the exception behavior of these instructions depend on the PMP
>
On Mon, Jan 23, 2023 at 06:51:51PM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > We do proper page size alignment for file backed mmap()s for ramblocks.
> > Even if it's as simple as that, cache the value because it'll be used in
> > multiple places.
> >
> >
On 1/24/23 09:59, Christoph Muellner wrote:
+static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
+{
+(void) a;
+REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+REQUIRE_PRIV_MS(ctx);
+decode_save_opc(ctx);
+gen_helper_tlb_flush_all(cpu_env);
Why
This reinstates commit 52f0c1607671293afcdb2acc2f83e9bccbfa74bb:
While forcing the CPU to unrealize by hand does trigger the clean-up
code we never fully free resources because refcount never reaches
zero. This is because QOM automatically added objects without an
explicit parent to /unattached/,
From: Christoph Müllner
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add
From: Christoph Müllner
This patch adds support for the XTheadBb ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add
From: Christoph Müllner
This patch adds the T-Head C906 to the list of known CPUs.
Selecting this CPUs will automatically enable the available
ISA extensions of the CPUs (incl. vendor extensions).
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
From: Christoph Müllner
This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Fix
From: Christoph Müllner
The XThead* extensions are maintained by T-Head and VRULL.
Adding a point of contact from both companies.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff
From: Christoph Müllner
There are no differences for floating point instructions in priv version 1.11
and 1.12. There is also no dependency for Zfh to priv version 1.12.
Therefore allow Zfh to be enabled for priv version 1.11.
Acked-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
From: Christoph Müllner
This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c | 2 +
From: Christoph Müllner
This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use
From: Christoph Müllner
This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.
The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.
From: Christoph Müllner
This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use
From: Christoph Müllner
This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add
From: Christoph Müllner
This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use
From: Christoph Müllner
This series introduces support for the T-Head vendor extensions,
which are implemented e.g. in the XuanTie C906 and XuanTie C910:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
*
From: Christoph Müllner
This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.
The implementation does not
From: Christoph Müllner
This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use single
On Tue, Jan 24, 2023 at 6:31 PM Christoph Müllner <
christoph.muell...@vrull.eu> wrote:
>
>
> On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis
> wrote:
>
>> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner
>> wrote:
>> >
>> > From: Christoph Müllner
>> >
>> > This patch adds support for the
On 1/24/23 08:00, Alex Bennée wrote:
We were using quite and old runner on our machines and running into
issues with stalling jobs. Gitlab in the meantime now reliably provide
the latest packaged versions of the runner under a stable URL. This
update:
- creates a per-arch subdir for builds
On 1/24/23 08:01, Alex Bennée wrote:
From: Emilio Cota
Fixes: #1381
Signed-off-by: Emilio Cota
Message-Id:<20230108165107.62488-1-c...@braap.org>
[AJB: manually applied follow-up fix]
Signed-off-by: Alex Bennée
---
include/qemu/plugin.h | 4
accel/tcg/cpu-exec.c | 2 ++
2 files
On 1/24/23 08:01, Alex Bennée wrote:
From: Emilio Cota
There are actually a whole bunch of helpers that don't affect memory
that we shouldn't instrument. They are helpfully identified by the
TCG_CALL_NO_SIDE_EFFECTS flag which marks out lookup_tb_ptr as well as
a lot of the maths helpers. To
On 1/21/23 17:56, Bernhard Beschow wrote:
Am 6. Januar 2023 11:39:27 UTC schrieb Bernhard Beschow :
mv64361_pcihost_map_irq() is a reimplementation of
pci_swizzle_map_irq_fn(). Resolve this redundancy.
Signed-off-by: Bernhard Beschow
Ping
Patch is reviewed. Who will queue it? Daniel?
Hi
On Tue, Jan 24, 2023 at 7:08 PM Daniel P. Berrangé wrote:
>
> On Tue, Jan 24, 2023 at 03:43:25PM +0100, Thomas Huth wrote:
> > On 23/01/2023 17.23, Daniel P. Berrangé wrote:
> > > On Fri, Jan 20, 2023 at 05:57:29PM +0400, Marc-André Lureau wrote:
> > ...
> > > > > > On Thu, Jan 19, 2023 at
From: Siddhi Katage
An old running QEMU will try to load modules with new build-id first, this
will fail as expected, then QEMU will fallback to load the old modules that
matches its build-id from /var/run/qemu/ directory.
Make /var/run/qemu/ directory as first search path to load modules.
We are getting a lot of failures that are not related to changes so
this could be a flaky test.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
tests/tcg/multiarch/Makefile.target | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/tcg/multiarch/Makefile.target
From: Emilio Cota
Fixes this tsan crash, easy to reproduce with any large enough program:
$ tests/unit/test-qht
1..2
ThreadSanitizer: CHECK failed: sanitizer_deadlock_detector.h:67
"((n_all_locks_)) <
(((sizeof(all_locks_with_contexts_)/sizeof((all_locks_with_contexts_)[0]"
(0x40, 0x40)
From: Richard Henderson
linux-user blocks all signals while attempting to handle guest
signals (e.g. ABRT), which means that the default TERM sent by timeout
has no effect -- KILL instead.
Signed-off-by: Richard Henderson
Message-Id: <20230117035701.168514-2-richard.hender...@linaro.org>
[AJB:
This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Cc: Robert Henry
Cc: Aaron Lindsay
---
tests/tcg/aarch64/Makefile.softmmu-target | 7 +++
tests/tcg/aarch64/system/boot.S
From: Emilio Cota
We forgot to add this one in "a890643958 util/qht: atomically set b->hashes".
Detected with tsan.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Emilio Cota
Message-Id: <2023051628.320011-3-c...@braap.org>
From: Richard Henderson
Rather than iterate over all plugins for all events,
iterate over plugins that have registered a given event.
Signed-off-by: Richard Henderson
Message-Id: <20230117035701.168514-4-richard.hender...@linaro.org>
---
plugins/core.c | 7 ---
1 file changed, 4
From: Thomas Huth
tests/tcg/nios2/Makefile.target has accidentally been added
to the Microblaze section. Move it into the correct nios2
section instead - and while we're at it, it should also cover
the whole folder, and not only the Makefile.
Fixes: 67f80eb4d0 ("tests/tcg: enable
From: Emilio Cota
We were mistakenly checking tcg_ctx->plugin_insn as a canary to know
whether the TB had emitted helpers that might have accessed memory.
The problem is that tcg_ctx->plugin_insn gets updated on every
instruction in the TB, which results in us wrongly performing the
From: Emilio Cota
Fixes: #1381
Signed-off-by: Emilio Cota
Message-Id: <20230108165107.62488-1-c...@braap.org>
[AJB: manually applied follow-up fix]
Signed-off-by: Alex Bennée
---
include/qemu/plugin.h | 4
accel/tcg/cpu-exec.c | 2 ++
2 files changed, 6 insertions(+)
diff --git
From: Keith Packard
'lock_user' allocates a host buffer to shadow a target buffer,
'unlock_user' copies that host buffer back to the target and frees the
host memory. If the completion function uses the target buffer, it
must be called after unlock_user to ensure the data are present.
This
This affects both system and user mode emulation so we should probably
list it up front.
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v2
- HPs -> HP's
- MIPs-like -> MIPS-like
---
docs/about/emulation.rst | 103 ++
docs/about/index.rst
Make it easier to navigate the documentation.
Reviewed-by: Peter Maydell
Acked-by: Richard Henderson
Signed-off-by: Alex Bennée
---
docs/about/index.rst | 16
docs/system/index.rst | 2 ++
docs/tools/index.rst | 2 ++
docs/user/index.rst | 2 ++
4 files changed, 14
From: Emilio Cota
There are actually a whole bunch of helpers that don't affect memory
that we shouldn't instrument. They are helpfully identified by the
TCG_CALL_NO_SIDE_EFFECTS flag which marks out lookup_tb_ptr as well as
a lot of the maths helpers. To avoid the string compare we introduce a
From: Emilio Cota
Reviewed-by: Alex Bennée
Signed-off-by: Emilio Cota
Reviewed-by: Richard Henderson
Message-Id: <2023051628.320011-4-c...@braap.org>
Signed-off-by: Alex Bennée
---
include/qemu/thread.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
From: Emilio Cota
Related: #1381
Signed-off-by: Emilio Cota
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230108164731.61469-3-c...@braap.org>
Signed-off-by: Alex Bennée
---
accel/tcg/translator.c | 15 ++-
1 file changed, 10 insertions(+), 5
The main reason to do this is to document our O_BINARY implementation
decision somewhere. However I've also moved some of the implementation
details out of qemu-options and added links between the two. As a
bonus I've highlighted the scary warnings about host access with the
appropriate RST tags.
Instead of spewing the whole log to stdout lets just define them as
build artefacts so we can examine them later. Where we are running
check-tcg run it first as those tests are yet to be integrated into
meson. To avoid confusion we don't run multiple check-tcg tests at
once.
Reviewed-by: Thomas
From: Emilio Cota
To fix potential deadlocks as reported by tsan.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Emilio Cota
Message-Id: <2023051628.320011-6-c...@braap.org>
Signed-off-by: Alex Bennée
---
plugins/core.c | 16 +++-
1 file
From: Evgeny Iakovlev
Windows open(2) implementation opens files in text mode by default and
needs a Windows-only O_BINARY flag to open files as binary. QEMU already
knows about that flag in osdep and it is defined to 0 on non-Windows,
so we can just add it to the host_flags for better
From: Philippe Mathieu-Daudé
When flex is not available, binutils sources default to the
'missing' script, but the current script available is not in
the format expected by the 'configure' script:
$ ./configure
...
/usr/src/binutils/missing: Unknown `--run' option
Try
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
Message-Id: <20230110132700.833690-9-marcandre.lur...@redhat.com>
Signed-off-by: Alex Bennée
---
.gitlab-ci.d/cirrus/freebsd-12.vars | 2 +-
.gitlab-ci.d/cirrus/freebsd-13.vars
From: Mark Cave-Ayland
Suggested-by: Mark Cave-Ayland
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
---
.gitlab-ci.d/base.yml | 5 +
1 file changed, 5 insertions(+)
diff --git a/.gitlab-ci.d/base.yml b/.gitlab-ci.d/base.yml
index 69b36c148a..50fb59e147 100644
---
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