On Mon, Nov 27, 2023 at 07:58:28PM +0900, Hyeonggon Yoo wrote:
> Hi, this is a fixup for the recent patch series "QEMU: CXL mailbox rework and
> features (Part 1)" [1].
To clarify do you plan v2 of this?
> This fixes two problems:
>
>1. Media Status in memory device status register not
Het Gala writes:
> 'channel' and 'addr' in qmp_migrate() and qmp_migrate_incoming() are
> not auto-freed. migrate_uri_parse() allocates memory which is
> returned to 'channel', which is leaked because there is no code for
> freeing 'channel' or 'addr'.
> So, free addr and channel to avoid memory
Your commit message is all in one line. You need to format it like
migration: Plug memory leak
'channel' and 'addr' in qmp_migrate() are not auto-freed.
migrate_uri_parse() allocates memory which is returned to 'channel',
which is leaked because there is no code for freeing
On 11/28/23 02:47, Nicholas Piggin wrote:
On Tue Nov 28, 2023 at 2:37 AM AEST, Cédric Le Goater wrote:
I'm not sure, I don't think it's necessary if your minimal patch works.
I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
this as well.
I think this is a bit late for
On 27/11/23 05:05, Gavin Shan wrote:
Hi Phil,
On 11/24/23 05:35, Philippe Mathieu-Daudé wrote:
Unify the "kvm_arm.h" API: All functions related to ARM vCPUs
take a ARMCPU* argument. Use the CPU() QOM cast macro When
calling the generic vCPU API from "sysemu/kvm.h".
Signed-off-by: Philippe
Hi Gavin,
On 27/11/23 05:12, Gavin Shan wrote:
Hi Phil,
On 11/24/23 05:35, Philippe Mathieu-Daudé wrote:
Unify the "kvm_arm.h" API: All functions related to ARM vCPUs
take a ARMCPU* argument. Use the CPU() QOM cast macro When
calling the generic vCPU API from "sysemu/kvm.h".
Signed-off-by:
'channel' and 'addr' in qmp_migrate() and qmp_migrate_incoming() are
not auto-freed. migrate_uri_parse() allocates memory which is
returned to 'channel', which is leaked because there is no code for
freeing 'channel' or 'addr'.
So, free addr and channel to avoid memory leak. 'addr' does shallow
On 11/27/23 18:13, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
On 27/11/23 05:20, Gavin Shan wrote:
Hi Phil,
On 11/24/23 05:35, Philippe Mathieu-Daudé wrote:
Unify the "kvm_arm.h" API: All functions related to ARM vCPUs
take a ARMCPU* argument. Use the CPU() QOM cast macro When
calling the generic vCPU API from "sysemu/kvm.h".
Signed-off-by: Philippe
Fixes: 5994024f ("migration: Implement MigrateChannelList to qmp
migration flow")
Signed-off-by: Het Gala
---
migration/migration.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migration/migration.c b/migration/migration.c
index 28a34c9068..29efb51b62 100644
--- a/migration/migration.c
> On Nov 23, 2023, at 12:54 AM, Li Feng wrote:
>
> If the error occurs in vhost_dev_init, the value of s->connected is set to
> true
> in advance, and there is no chance to enter this function execution again
> in the future.
>
> Signed-off-by: Li Feng
Reviewed-by: Raphael Norwitz
> ---
> On Nov 23, 2023, at 12:54 AM, Li Feng wrote:
>
> Keep it the same to vhost-user-blk.
> At the same time, fix the vhost_reset_device.
>
> Signed-off-by: Li Feng
Reviewed-by: Raphael Norwitz
> ---
> hw/scsi/vhost-user-scsi.c | 16
> hw/virtio/virtio.c| 2 +-
> 2
On Tue, 28 Nov 2023, Hyeonggon Yoo wrote:
All of them make sense to me. I will adjust, thanks!
But I'm not confident enough to write a single description for all the
changes so will
split it into a few patches. May I add your Suggested-by (or
Signed-off-by) in v2
as it will contain some part
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> This part of the patchset connects the nest1 chiplet model to p10 chip.
>
> Signed-off-by: Chalapathi V
> ---
> include/hw/ppc/pnv_chip.h | 2 ++
> hw/ppc/pnv.c | 15 +++
> 2 files changed, 17 insertions(+)
>
>
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> The N1 chiplet handle the high speed i/o traffic over PCIe and others.
> The N1 chiplet consists of PowerBus Fabric controller,
> nest Memory Management Unit, chiplet control unit and more.
>
> This commit creates a N1 chiplet model and
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> are broadly divided into "core chiplets" (with the processor cores) and
> "nest chiplets" (with everything else). Each chiplet has an attachment
> to the pervasive
On Tue Nov 28, 2023 at 6:51 AM AEST, Miles Glenn wrote:
> On Wed, 2023-10-18 at 10:59 -0500, Miles Glenn wrote:
> > On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> > > On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > > > This is a series of patches for adding support for the
On Tue Nov 28, 2023 at 2:37 AM AEST, Cédric Le Goater wrote:
>
> > I'm not sure, I don't think it's necessary if your minimal patch works.
> >
> > I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
> > this as well.
>
> I think this is a bit late for 8.2 to change FW images,
The machine uses a modified U-Boot under GPL license but the sources
of it are lost with only a binary available so it cannot be included
in QEMU. Allow running without the firmware image which can be used
when calling a boot loader directly and thus simplifying booting
guests. We need a small
Hi David,
Thank you for the review
David Woodhouse writes:
> [[S/MIME Signed Part:Undecided]]
> On Fri, 2023-11-24 at 23:24 +, Volodymyr Babchuk wrote:
>> Xen PV devices in QEMU can be created in two ways: either by QEMU
>> itself, if they were passed via command line, or by Xen toolstack.
On Tue, Nov 28, 2023 at 5:27 AM Davidlohr Bueso wrote:
>
> On Mon, 27 Nov 2023, Hyeonggon Yoo wrote:
>
> >In the current mdev_reg_read() implementation, it consistently returns
> >that the Media Status is Ready (01b). This was fine until commit
> >25a52959f99d ("hw/cxl: Add support for device
On Tue, Nov 28, 2023 at 2:53 AM Davidlohr Bueso wrote:
>
> On Mon, 27 Nov 2023, Hyeonggon Yoo wrote:
>
> >commit 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background
> >completion") enables notifying background command completion via MSI-X
> >interrupt (vector number 9).
> >
> >However,
On Sun, 19 Nov 2023 18:31:10 +0530
wrote:
> From: Ankit Agrawal
>
> NVIDIA GPU's support MIG (Mult-Instance GPUs) feature [1], which allows
> partitioning of the GPU device resources (including device memory) into
> several (upto 8) isolated instances. Each of the partitioned memory needs
> a
On Sun, 19 Nov 2023 18:31:11 +0530
wrote:
> From: Ankit Agrawal
>
> ACPI spec provides a scheme to associate "Generic Initiators" [1]
> (e.g. heterogeneous processors and accelerators, GPUs, and I/O devices with
> integrated compute or DMA engines GPUs) with Proximity Domains. This is
>
On Mon, Nov 27, 2023 at 05:32:45PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Nov 27, 2023 at 12:52:38PM -0300, Fabiano Rosas wrote:
> >> >> @@ -118,6 +118,12 @@ void migrate_incoming_qmp(QTestState *to, const
> >> >> char *uri, const char *fmt, ...)
> >> >>
> >> >> rsp
On Wed, 2023-10-18 at 10:59 -0500, Miles Glenn wrote:
> On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> > On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > > This is a series of patches for adding support for the Branch
> > > History
> > > Rolling Buffer (BHRB) facility.
Peter Xu writes:
> On Mon, Nov 27, 2023 at 12:52:38PM -0300, Fabiano Rosas wrote:
>> >> @@ -118,6 +118,12 @@ void migrate_incoming_qmp(QTestState *to, const char
>> >> *uri, const char *fmt, ...)
>> >>
>> >> rsp = qtest_qmp(to, "{ 'execute': 'migrate-incoming', 'arguments':
>> >> %p}",
Allow multifd to use an fdset when migrating to a file. This is useful
for the scenario where the management layer wants to have control over
the migration file.
By receiving the file descriptors directly, QEMU can delegate some
high level operating system operations to the management layer (such
Currently multifd does not need to have knowledge of pages on the
receiving side because all the information needed is within the
packets that come in the stream.
We're about to add support to fixed-ram migration, which cannot use
packets because it expects the ramblock section in the migration
For the incoming fixed-ram migration we need to read the ramblock
headers, get the pages bitmap and send the host address of each
non-zero page to the multifd channel thread for writing.
To read from the migration file we need a preadv function that can
read into the iovs in segments of
The test is only allowed to run in systems that know and in
filesystems which support O_DIRECT.
Signed-off-by: Fabiano Rosas
---
- added ifdefs for O_DIRECT and a probing function
---
tests/qtest/migration-helpers.c | 39 +
tests/qtest/migration-helpers.h | 1 +
For the upcoming support to fixed-ram migration with multifd, we need
to be able to accept an iovec array with non-contiguous data.
Add a pwritev and preadv version that splits the array into contiguous
segments before writing. With that we can have the ram code continue
to add pages in any order
Add the direct-io migration parameter that tells the migration code to
use O_DIRECT when opening the migration stream file whenever possible.
This is currently only used with fixed-ram migration for the multifd
channels that transfer the RAM pages. Those channels only transfer the
pages and are
Add the necessary code to parse the format changes for the 'fixed-ram'
capability.
One of the more notable changes in behavior is that in the 'fixed-ram'
case ram pages are restored in one go rather than constantly looping
through the migration stream.
Signed-off-by: Nikolay Borisov
The only way for the channel backend to report an error to the multifd
core during creation is by setting the QIOTask error. We must allow
the channel backend to set the error even if the QIOChannel has failed
to be created, which means the QIOTask source object would be NULL.
At
The new fixed-ram stream format uses a file transport and puts ram
pages in the migration file at their respective offsets and can be
done in parallel by using the pwritev system call which takes iovecs
and an offset.
Add support to enabling the new format along with multifd to make use
of the
We're about to add one more condition to the flags comparison that
requires an ifdef. Move the code into a separate function now to make
it cleaner after the next patch.
Signed-off-by: Fabiano Rosas
---
monitor/fds.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff
For the upcoming support to the new 'fixed-ram' migration stream
format, we cannot use multifd packets because each write into the
ramblock section in the migration file is expected to contain only the
guest pages. They are written at their respective offsets relative to
the ramblock section
On Mon, 27 Nov 2023, Hyeonggon Yoo wrote:
In the current mdev_reg_read() implementation, it consistently returns
that the Media Status is Ready (01b). This was fine until commit
25a52959f99d ("hw/cxl: Add support for device sanitation") because the
media was presumed to be ready.
However, as
We're currently only removing an fd from the fdset if the VM is
running. This causes a QMP call to "remove-fd" to not actually remove
the fd if the VM happens to be stopped.
While the fd would eventually be removed when monitor_fdset_cleanup()
is called again, the user request should be honored
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 45
1 file changed, 45 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 96a6217af0..5c5725687c 100644
--- a/tests/qtest/migration-test.c
+++
Hi,
In this v3:
Added support for the "file:/dev/fdset/" syntax to receive multiple
file descriptors. This allows the management layer to open the
migration file beforehand and pass the file descriptors to QEMU. We
need more than one fd to be able to use O_DIRECT concurrently with
unaligned
Add a new migration capability 'fixed-ram'.
The core of the feature is to ensure that each RAM page has a specific
offset in the resulting migration stream. The reasons why we'd want
such behavior are:
- The resulting file will have a bounded size, since pages which are
dirtied multiple
Make sure the data is flushed to disk before closing file
channels. This will ensure data is on disk at the end of a migration
to file.
Signed-off-by: Fabiano Rosas
---
io/channel-file.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/io/channel-file.c b/io/channel-file.c
index
From: Nikolay Borisov
Introduce basic pwritev/preadv support in the generic channel layer.
Specific implementation will follow for the file channel as this is
required in order to support migration streams with fixed location of
each ram page.
Signed-off-by: Nikolay Borisov
Signed-off-by:
From: Nikolay Borisov
Add basic tests for 'fixed-ram' migration.
Signed-off-by: Nikolay Borisov
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 39
1 file changed, 39 insertions(+)
diff --git a/tests/qtest/migration-test.c
From: Nikolay Borisov
Add utility methods that will be needed when implementing 'fixed-ram'
migration capability.
qemu_file_is_seekable
qemu_put_buffer_at
qemu_get_buffer_at
qemu_set_offset
qemu_get_offset
Signed-off-by: Nikolay Borisov
Signed-off-by: Fabiano Rosas
Reviewed-by: Daniel P.
Some functionalities of multifd are incompatible with the 'fixed-ram'
migration format.
The MULTIFD_FLUSH flag in particular is not used because in fixed-ram
there is no sinchronicity between migration source and destination so
there is not need for a sync packet. In fact, fixed-ram disables
Add a multifd test for fixed-ram with passing of fds into QEMU. This
is how libvirt will consume the feature.
There are a couple of details to the fdset mechanism:
- multifd needs two distinct file descriptors (not duplicated with
dup()) on the outgoing side so it can enable O_DIRECT only on
We're about to enable the use of O_DIRECT in the migration code and
due to the alignment restrictions imposed by filesystems we need to
make sure the flag is only used when doing aligned IO.
The migration will do parallel IO to different regions of a file, so
we need to use more than one file
Allow multifd to open file-backed channels. This will be used when
enabling the fixed-ram migration stream format which expects a
seekable transport.
The QIOChannel read and write methods will use the preadv/pwritev
versions which don't update the file offset at each call so we can
reuse the fd
When adding the support for file migration with the file: transport,
we missed adding documentation for it.
Signed-off-by: Fabiano Rosas
---
docs/devel/migration.rst | 4
1 file changed, 4 insertions(+)
diff --git a/docs/devel/migration.rst b/docs/devel/migration.rst
index
Use a more specific name for the compression data so we can use the
generic for the multifd core code.
Signed-off-by: Fabiano Rosas
---
migration/multifd-zlib.c | 20 ++--
migration/multifd-zstd.c | 20 ++--
migration/multifd.h | 4 ++--
3 files changed, 22
From: Nikolay Borisov
The upcoming 'fixed-ram' feature will require qemu to write data to
(and restore from) specific offsets of the migration file.
Add a minimal implementation of pwritev/preadv and expose them via the
io_pwritev and io_preadv interfaces.
Signed-off-by: Nikolay Borisov
Next patch will abstract the type of data being received by the
channels, so do some cleanup now to remove references to pages and
dependency on 'normal_num'.
Signed-off-by: Fabiano Rosas
---
migration/multifd-zlib.c | 2 +-
migration/multifd-zstd.c | 2 +-
migration/multifd.c | 12
The fixed-ram migration format needs a channel that supports seeking
to be able to write each page to an arbitrary offset in the migration
stream.
Signed-off-by: Fabiano Rosas
Reviewed-by: Daniel P. Berrangé
---
- avoided overwriting errp in compatibility check
---
migration/migration.c | 16
On the receiving side we don't need to differentiate between main
channel and threads, so whichever channel is defined first gets to be
the main one. And since there are no packets, use the atomic channel
count to index into the params array.
Signed-off-by: Fabiano Rosas
---
- stop setting
From: Nikolay Borisov
Implement the outgoing migration side for the 'fixed-ram' capability.
A bitmap is introduced to track which pages have been written in the
migration file. Pages are written at a fixed location for every
ramblock. Zero pages are ignored as they'd be zero in the destination
From: Nikolay Borisov
Add a generic QIOChannel feature SEEKABLE which would be used by the
qemu_file* apis. For the time being this will be only implemented for
file channels.
Signed-off-by: Nikolay Borisov
Signed-off-by: Fabiano Rosas
Reviewed-by: Daniel P. Berrangé
---
On Mon, Nov 27, 2023 at 12:52:38PM -0300, Fabiano Rosas wrote:
> >> @@ -118,6 +118,12 @@ void migrate_incoming_qmp(QTestState *to, const char
> >> *uri, const char *fmt, ...)
> >>
> >> rsp = qtest_qmp(to, "{ 'execute': 'migrate-incoming', 'arguments':
> >> %p}",
> >>
On Mon, Nov 27, 2023 at 10:48:29AM -0600, Madhavan T. Venkataraman wrote:
> Apologies for the late reply. I was on vacation. Please see my response below:
>
> On 11/13/23 02:19, Peter Zijlstra wrote:
> > On Sun, Nov 12, 2023 at 09:23:24PM -0500, Mickaël Salaün wrote:
> >> From: Madhavan T.
On Mon, Nov 27, 2023 at 11:05:23AM -0600, Madhavan T. Venkataraman wrote:
> Apologies for the late reply. I was on vacation. Please see my response below:
>
> On 11/13/23 02:54, Peter Zijlstra wrote:
> > On Sun, Nov 12, 2023 at 09:23:25PM -0500, Mickaël Salaün wrote:
> >> From: Madhavan T.
To remove DPRINTF macros and use tracepoints
for logging.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1827
Signed-off-by: Jai Arora
---
accel/kvm/kvm-all.c| 32 ++--
accel/kvm/trace-events | 2 +-
2 files changed, 11 insertions(+), 23 deletions(-)
Hi Gihun,
On 27/11/23 03:54, Gihun Nam wrote:
The current implementation initializes the stack pointer of AVR devices
to 0. Although older AVR devices used to be like that, newer ones set
it to RAMEND.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525
Signed-off-by: Gihun Nam
---
On 27/11/23 17:02, Zhao Liu wrote:
From: Zhao Liu
In fact, type4-count, core-count, core-count2, thread-count and
thread-count2 are tested with KVM not TCG.
Rename these test functions to reflect KVM base instead of TCG.
Signed-off-by: Zhao Liu
---
tests/qtest/bios-tables-test.c | 20
On Thu, Nov 23, 2023 at 02:49:31PM -0500, Stefan Hajnoczi wrote:
> Commit abfcd2760b3e ("dma-helpers: prevent dma_blk_cb() vs
> dma_aio_cancel() race") acquired the AioContext lock inside dma_blk_cb()
> to avoid a race with scsi_device_purge_requests() running in the main
> loop thread.
>
> The
Am 25.11.2023 um 15:01 hat BALATON Zoltan geschrieben:
> Return default value in legacy mode for BAR4 when unset. This can't be
> set in reset method because BARs are cleared on reset so we return it
> instead when BARs are read in legacy mode.
>
> Signed-off-by: BALATON Zoltan
> ---
> This
Am 27.11.2023 um 16:18 hat Eric Blake geschrieben:
> On Fri, Nov 24, 2023 at 11:56:54AM +, Fam wrote:
> > From: Fam Zheng
> >
> > If the text description file is larger than DESC_SIZE, we force the last
> > byte in the buffer to be 0 and write it out.
> >
> > This results in a corruption.
>
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewed-by: Cédric Le Goater
Signed-off-by:
Allow external devices to drive pca9552 input pins by adding
input GPIO's to the model. This allows a device to connect
its output GPIO's to the pca9552 input GPIO's.
In order for an external device to set the state of a pca9552
pin, the pin must first be configured for high impedance (LED
is
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C controller from
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
---
No change from previous version
hw/ppc/pnv.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present.
Reviewed-by: Cédric Le Goater
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good" signal asserted
on one of pca9552 GPIO
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6). This is used by hypervisor code to
control PCIe slot power during hotplug events.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
detection of IBM CableCard devices. Both devices
The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins. A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage scenario. Existing
On Mon, 27 Nov 2023, Hyeonggon Yoo wrote:
commit 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background
completion") enables notifying background command completion via MSI-X
interrupt (vector number 9).
However, the commit uses vector number 9 but the maximum number of
entries is less
There is no architectural requirement that SME implies SVE, but
our implementation currently assumes it. (FEAT_SME_FA64 does
imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
you quickly run into an assert when the guest tries to write to
SMCR_EL1:
#6 0x74b38e96 in
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed as skiboot defines the
device-tree and QEMU should just follow it.
2. Renamed
In commit edac4d8a168 back in 2015 when we added support for
the virtual timer offset CNTVOFF_EL2, we didn't correctly update
the timer-recalculation code that figures out when the timer
interrupt is next going to change state. We got it wrong in
two ways:
* for the 0->1 transition, we didn't
From: Frederic Konrad
The spips, qspips, and zynqmp-qspips share the same realize function
(xilinx_spips_realize) and initialize their io memory region with different
mmio_ops passed through the class. The size of the memory region is set to
the largest area (0x200 bytes for zynqmp-qspips) thus
Hi Phil,
On 11/23/23 02:21, Philippe Mathieu-Daudé wrote:
Hi Patrick,
On 23/11/23 01:17, Patrick O'Neill wrote:
QEMU currently limits the max vlenb to 1024. GCC sets the upper bound
to 4096 [1]. There doesn't seem to be an upper bound set by the spec [2]
so this patch just changes QEMU to
From: Philippe Mathieu-Daudé
The VirtioPCIDeviceTypeInfo structure, added in commit a4ee4c8baa
("virtio: Helper for registering virtio device types") got extended
in commit 8ea90ee690 ("virtio: add class_size") with the @class_size
field. Do similarly with the @instance_finalize field.
From: Frederic Konrad
UG1087 states for the source channel that: if SIZE is programmed to 0, and the
DMA is started, the interrupts DONE and MEM_DONE will be asserted.
This implies that it is allowed for the guest to stop the source DMA by writing
a size of 0 to the SIZE register, so remove the
From: Philippe Mathieu-Daudé
Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format
Message Format
The same message format is used for RXFIFO, TXFIFO, and TXHPB.
Each message includes four words (16 bytes). Software must read
and write all four words regardless
From: Philippe Mathieu-Daudé
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 8077b8e549 added:
:18 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231127
for you to fetch changes up to 1ee80592bf24eabef77e2260a86d9358b54c08fd:
hw/dma/xlnx_csu_dma: don't throw guest errors when stopping the SRC DMA
(2023-11-27
From: Frederic Konrad
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
Message-id: 20231124143505.1493184-3-fkon...@amd.com
Signed-off-by: Peter Maydell
---
The syndrome register value always has an IL field at bit 25, which
is 0 for a trap on a 16 bit instruction, and 1 for a trap on a 32
bit instruction (or for exceptions which aren't traps on a known
instruction, like PC alignment faults). This means that our
syn_*() functions should always either
From: Philippe Mathieu-Daudé
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit a75f336b97 added:
From: Philippe Mathieu-Daudé
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 68fbcc344e added:
From: Philippe Mathieu-Daudé
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 9e4aa1fafe added:
From: Philippe Mathieu-Daudé
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 4fb013afcc added:
From: Philippe Mathieu-Daudé
Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format
Message Format
The same message format is used for RXFIFO, TXFIFO, and TXHPB.
Each message includes four words (16 bytes). Software must read
and write all four words regardless
Apologies for the late reply. I was on vacation. Please see my response below:
On 11/13/23 02:54, Peter Zijlstra wrote:
> On Sun, Nov 12, 2023 at 09:23:25PM -0500, Mickaël Salaün wrote:
>> From: Madhavan T. Venkataraman
>>
>> Implement a hypervisor function, kvm_protect_memory() that calls the
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