On Fri, Dec 1, 2023 at 11:37 PM Laurent Vivier wrote:
> On 12/1/23 16:21, Markus Armbruster wrote:
> > Laurent Vivier writes:
> >
> >> On 11/21/23 08:58, Markus Armbruster wrote:
> >>> Laurent, there's a question for you at the end.
> >>>
> >>> Yong Huang writes:
> >>>
> On Thu, Nov 16,
On Fri, 8 Dec 2023, Daniel P. Berrangé wrote:
> CC'ing the Xen folks
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error: ‘GUEST_VIRTIO_MMIO_SPI_LAST’
Commit b8002058 strengthened openat()'s /proc detection by calling
realpath(3) on the given path, which allows various paths and symlinks
that points to the /proc file system to be intercepted correctly.
Using realpath(3), though, has a side effect that it reads the symlinks
along the way, and
Since v2:
- More robust handling of `readlink()`
Since v1:
- Eliminate static buffers in do_guest_openat()
Shu-Chun Weng (2):
linux-user: Define TARGET_O_LARGEFILE for aarch64
linux-user: Fix openat() emulation to not modify atime
linux-user/aarch64/target_fcntl.h | 1 +
In 050a1ba, when moving the macros from preprocessor-guarding to
file-based definition, TARGET_O_LARGEFILE appeared to have been
accidentally left off.
This may have correctness implication, but so far I was only confused by
strace's output.
Fixes: 050a1ba69a ("linux-user: move arm/aarch64/m68k
+Stewart
On Fri, 8 Dec 2023, Mykyta Poturai wrote:
> Hello everyone,
>
> I am currently working on adding MSI support to virtio-pci on ARM with Xen.
Excellent!
> As far as I understand QEMU Xen ARM machine that is used for virtio-pci
> device emulation does not initialize any interrupt
On Mon, Dec 4, 2023 at 8:58 AM Daniel P. Berrangé
wrote:
> On Thu, Nov 30, 2023 at 07:21:40PM -0800, Shu-Chun Weng wrote:
> > Commit b8002058 strengthened openat()'s /proc detection by calling
> > realpath(3) on the given path, which allows various paths and symlinks
> > that points to the /proc
Since v1:
- Eliminate static buffers in do_guest_openat()
Shu-Chun Weng (2):
linux-user: Define TARGET_O_LARGEFILE for aarch64
linux-user: Fix openat() emulation to not modify atime
linux-user/aarch64/target_fcntl.h | 1 +
linux-user/syscall.c | 47
Commit b8002058 strengthened openat()'s /proc detection by calling
realpath(3) on the given path, which allows various paths and symlinks
that points to the /proc file system to be intercepted correctly.
Using realpath(3), though, has a side effect that it reads the symlinks
along the way, and
In 050a1ba, when moving the macros from preprocessor-guarding to
file-based definition, TARGET_O_LARGEFILE appeared to have been
accidentally left off.
This may have correctness implication, but so far I was only confused by
strace's output.
Fixes: 050a1ba69a ("linux-user: move arm/aarch64/m68k
On 12/8/23 09:07, Conor Dooley wrote:
From: Conor Dooley
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal
W dniu 8.12.2023 o 20:09, Cleber Rosa pisze:
The tests under machine_aarch64_virt.py do not need read-write access
to the ISOs. The ones under machine_aarch64_sbsaref.py, on the other
hand, will need read-write access, so let's give each test an unique
file.
And while at it, let's use a single
On 08/12/2023 17:42, Richard Henderson wrote:
On 12/7/23 18:06, LIU Zhiwei wrote:
For ram memory region the iotlb(which will be filled into the xlat_section
of CPUTLBEntryFull) is calculated as:
iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1) xlat here is the offset_within_region
This is a collection of improvements to a number of Avocado based
tests, but also fixes that will allow them to behave properly under
Avocado's upcoming new Long Term Stability release (LTS) version
103.0.
A pipeline with (pretty much) these changes can be seen at:
-
Avocado's fetchasset plugin runs before the actual Avocado job (and
any test). It analyses the test's code looking for occurrences of
"self.fetch_asset()" in the either the actual test or setUp() method.
It's not able to fully analyze all code, though.
The way these tests are written, make the
Some of these tests actually require the root filesystem image,
obtained through Avocado's asset feature and kept in a common cache
location, to be writable.
This makes a distinction between the tests that actually have this
requirement and those who don't. The goal is to be as safe as
possible,
The asset used in the mentioned test gets truncated before it's used
in the test. This means that the file gets modified, and thus the
asset's expected hash doesn't match anymore. This causes cache misses
and re-downloads every time the test is re-run.
Let's make a copy of the asset so that the
Because all tests share the same tags, it's possible to have all of
them at the class level.
Signed-off-by: Cleber Rosa
---
tests/avocado/boot_xen.py | 26 +-
1 file changed, 5 insertions(+), 21 deletions(-)
diff --git a/tests/avocado/boot_xen.py
The SSL certificate installed at mipsdistros.mips.com has expired:
0 s:CN = mipsdistros.mips.com
i:C = US, O = Amazon, OU = Server CA 1B, CN = Amazon
a:PKEY: rsaEncryption, 2048 (bit); sigalg: RSA-SHA256
v:NotBefore: Dec 23 00:00:00 2019 GMT; NotAfter: Jan 23 12:00:00 2021 GMT
Because this
Rather than defining a single use variable, let's just use the class
attribute directly.
Signed-off-by: Cleber Rosa
---
tests/avocado/boot_xen.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/avocado/boot_xen.py b/tests/avocado/boot_xen.py
index
Based on many runs, the average run time for these 4 tests is around
250 seconds, with 320 seconds being the ceiling. In any way, the
default 120 seconds timeout is inappropriate in my experience.
Let's increase the timeout so these tests get a chance to completion.
Signed-off-by: Cleber Rosa
While it's a good practice to have reusable base classes, in this
specific case there's no other user of the BootXenBase class.
By unifying the class used in this test, we can improve readability
and have the opportunity to add some future improvements in a clearer
fashion.
Signed-off-by: Cleber
The tests under machine_aarch64_virt.py do not need read-write access
to the ISOs. The ones under machine_aarch64_sbsaref.py, on the other
hand, will need read-write access, so let's give each test an unique
file.
And while at it, let's use a single code style and hash for the ISO
url.
Avocado's asset system will deposit files in a cache organized either
by their original location (the URI) or by their names. Because the
cache (and the "by_name" sub directory) is common across tests, it's a
good idea to make these names as distinct as possible.
This avoid name clashes, which
On 12/6/23 12:51, Peter Zijlstra wrote:
> On Wed, Dec 06, 2023 at 10:37:33AM -0600, Madhavan T. Venkataraman wrote:
>>
>>
>> On 11/30/23 05:33, Peter Zijlstra wrote:
>>> On Wed, Nov 29, 2023 at 03:07:15PM -0600, Madhavan T. Venkataraman wrote:
>>>
Kernel Lockdown
---
KVM_REG_RISCV_FP_F regs have u32 size according to the API, but by using
kvm_riscv_reg_id() in RISCV_FP_F_REG() we're returning u64 sizes when
running with TARGET_RISCV64. The most likely reason why no one noticed
this is because we're not implementing kvm_cpu_synchronize_state() in
RISC-V yet.
kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32
size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64.
Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll
be in line with the existing kvm_riscv_reg_id_() helpers.
Signed-off-by: Daniel
KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at
this moment we'll return u32 regs if we're running a RISCV32 target.
Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
---
Create a RISCV_CONFIG_REG() macro, similar to what other regs use, to
hide away some of the boilerplate.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git
KVM_REG_RISCV_FP_D regs are always u64 size. Using kvm_riscv_reg_id() in
RISCV_FP_D_REG() ends up encoding the wrong size if we're running with
TARGET_RISCV32.
Create a new helper that returns a KVM ID with u64 size and use it with
RISCV_FP_D_REG().
Reported-by: Andrew Jones
Signed-off-by:
Hi,
While working in a follow-up for the Vector KVM regs, where we would
read 'vlenb' and then all other vregs [1], Drew noticed that we're using
kvm_riscv_reg_id() in registers that are u32 and u64.
The helper is returning ulong regs for all cases, meaning that we return
the wrong size for u32
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 2 +-
include/sysemu/replay.h | 11 ---
stubs/icount.c | 19 ---
3 files changed, 9 insertions(+), 23 deletions(-)
Reviewed-by:
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/icount-common.c | 4 +++-
stubs/icount.c| 2 +-
util/async.c | 16 +---
3 files changed, 13 insertions(+), 9 deletions(-)
Reviewed-by: Richard
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.
PMU events are
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
We need to parse the accelerators first, to be able
to check whether TCG is enabled or not. Then we can
parse the -icount option.
This allows removing the icount_configure() stub.
Fixes: 7f8b6126e7 ("vl: move icount configuration earlier")
On 12/8/23 03:35, Philippe Mathieu-Daudé wrote:
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have icount_configure()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
On 12/7/23 18:06, LIU Zhiwei wrote:
For ram memory region the iotlb(which will be filled into the xlat_section
of CPUTLBEntryFull) is calculated as:
iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1) xlat here is the offset_within_region of a MemoryRegionSection, which maybe
not
On Fri, Oct 27, 2023 at 11:44 PM Louai Al-Khanji
wrote:
> Hi,
>
> I'm interested in having the guestfwd option work for udp. My
> understanding is that currently it's restricted to only tcp.
>
> I'm not familiar with libslirp internals. What would need to be changed to
> implement this? I'm
On 12/8/2023 11:37 AM, Fabiano Rosas wrote:
> Steve Sistare writes:
>
>> If the outgoing machine was previously suspended, propagate that to the
>> incoming side via global_state, so a subsequent vm_start restores the
>> suspended state. To maintain backward and forward compatibility, reclaim
Steve Sistare writes:
> Add a test case to verify that the suspended state is handled correctly
> during live migration precopy. The test suspends the src, migrates, then
> wakes the dest.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
Steve Sistare writes:
> If the outgoing machine was previously suspended, propagate that to the
> incoming side via global_state, so a subsequent vm_start restores the
> suspended state. To maintain backward and forward compatibility, reclaim
> some space from the runstate member.
>
>
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets
On Wed, 2023-12-06 at 11:42 -0600, Michael Roth wrote:
> On Wed, Dec 06, 2023 at 07:20:14PM +0200, Maxim Levitsky wrote:
> > On Tue, 2023-12-05 at 16:28 -0600, Michael Roth wrote:
> > > Commit 7191f24c7fcf ("accel/kvm/kvm-all: Handle register access errors")
> > > added error checking for
Hello,
Thank you for the review and suggestions on V7.
There are no major design/logic changes done in revision 8 from revision 7.
Addressed the minor comments.
The qom-tree looks like below.
(qemu) info qom-tree
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/n1-chiplet
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
Fabiano Rosas writes:
> We can run the migration tests with two different QEMU binaries to
> test migration compatibility between QEMU versions. This means we'll
> be running the tests with an older QEMU in either source or
> destination.
>
> We need to avoid trying to test functionality that is
This patch enables zoned ufs support.
By setting the LU parameter, each LU can be a host-managed zoned device.
This patch manages the zone condition and write pointer of each zone for
a zoned LU. It supports the report zones and reset write pointer commands
for Zoned LUs.
Signed-off-by: Daejun
This patch enables mode sense for zbc devices.
Signed-off-by: Daejun Park
---
hw/scsi/scsi-disk.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index 6691f5edb8..f1ecb77317 100644
--- a/hw/scsi/scsi-disk.c
+++
This patch includes the following tests
Test VPD page and report zones
Test write and unaligned write error
Signed-off-by: Daejun Park
---
tests/qtest/ufs-test.c | 178 +
1 file changed, 178 insertions(+)
diff --git a/tests/qtest/ufs-test.c
Hello everyone,
I am currently working on adding MSI support to virtio-pci on ARM with Xen.
As far as I understand QEMU Xen ARM machine that is used for virtio-pci device
emulation does not initialize any interrupt controllers. And that makes it
somewhat unclear what is the best approach to
This patch enables zoned support for UFS devices.
By applying this patch, a QEMU run can use parameters to configure whether
each LU of each UFS is zoned, and the capacity, size, and max open zones.
Zoned UFS is implemented by referencing ZBC2.
(https://www.t10.org/members/w_zbc2.htm)
Daejun
> On 08-Dec-2023, at 6:27 PM, Daniel P. Berrangé wrote:
>
> On Fri, Dec 08, 2023 at 05:56:11PM +0530, Ani Sinha wrote:
>> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
>> up to 4096 vCPUs")
>> Linux kernel can support upto a maximum number of 4096 vCPUS when
On 8/12/23 12:23, Philippe Mathieu-Daudé wrote:
Hi Peter,
On 8/12/23 11:59, Peter Maydell wrote:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé
wrote:
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the
On 8/12/23 12:35, Philippe Mathieu-Daudé wrote:
Rather than having to lookup for what the 0, 1, 2, ...
icount values are, use a enum definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 20 +---
accel/tcg/icount-common.c | 16 +++-
On Fri, Dec 08, 2023 at 05:56:11PM +0530, Ani Sinha wrote:
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow
> up to 4096 vCPUs")
> Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
> enabled in the kernel. So bump up the max_cpus value for
On 11/22/23 17:30, Gerd Hoffmann wrote:
> Hi,
>
>> - in general, we should filter out surrogate code points, for any use.
>> any UCS2 string from the guest that contains a surrogate code point
>> should be considered invalid, and the request should be rejected based
>> just on that.
>
>
The AioContext must be unlocked before calling blk_co_unref(), because
it takes the AioContext lock internally in blk_unref_bh(), which is
scheduled in the main thread. If we don't unlock, the AioContext is
locked twice and nested event loops such as in bdrv_graph_wrlock() will
deadlock.
Cc:
Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow up
to 4096 vCPUs")
Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
enabled in the kernel. So bump up the max_cpus value for q35 machines versions
8.3 and newer to 4096. Older q35 machines
From: Conor Dooley
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set
On 08.12.23 08:59, Xiaoyao Li wrote:
On 11/18/2023 5:03 AM, Isaku Yamahata wrote:
On Wed, Nov 15, 2023 at 02:14:18AM -0500,
Xiaoyao Li wrote:
It's used for discarding opposite memory after memory conversion, for
confidential guest.
When page is converted from shared to private, the original
Rather than having to lookup for what the 0, 1, 2, ...
icount values are, use a enum definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 20 +---
accel/tcg/icount-common.c | 16 +++-
stubs/icount.c | 2 +-
Slightly simplify non-TCG and user emulation code.
This series still adds assertions in ARM INST_RETIRED
PMU events, in order to bypass a linking failure. Better
would be to restrict ARM PMU events to TCG. Left for
another series.
Since v2:
- Have icount_configure() return bool
- Addressed rth's
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have icount_configure()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 10 --
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/cpu-timers.h | 2 +-
include/sysemu/replay.h | 11 ---
stubs/icount.c | 19 ---
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/include/sysemu/cpu-timers.h
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/icount-common.c | 4 +++-
stubs/icount.c| 2 +-
util/async.c | 16 +---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is enabled as ICOUNT_PRECISE.
PMU events are TCG-only, hardware accelerators handle them
We need to parse the accelerators first, to be able
to check whether TCG is enabled or not. Then we can
parse the -icount option.
This allows removing the icount_configure() stub.
Fixes: 7f8b6126e7 ("vl: move icount configuration earlier")
Reported-by: Richard Henderson
Signed-off-by: Philippe
On Fri, Dec 08, 2023 at 10:59:03AM +, Peter Maydell wrote:
> On Fri, 8 Dec 2023 at 09:25, Daniel P. Berrangé wrote:
> >
> > CC'ing the Xen folks
> >
> > On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > > diff --git a/include/hw/xen/xen_native.h b/include/hw/xen/xen_native.h
Hi Peter,
On 8/12/23 11:59, Peter Maydell wrote:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé wrote:
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED,
On 7/12/23 23:38, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
stubs/icount.c | 6 --
system/vl.c | 6 +-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/stubs/icount.c b/stubs/icount.c
index
Hi Richard,
On 8/12/23 01:35, Ilya Leoshkevich wrote:
v2: https://patchew.org/QEMU/20230630234230.596193-1-...@linux.ibm.com/
v2 -> v3: Rebased.
This series was lost and forgotten until Philippe reminded me
about it.
v1:
On Fri, 8 Dec 2023 at 10:36, Philippe Mathieu-Daudé wrote:
>
> On 7/12/23 23:12, Richard Henderson wrote:
> > On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
> >> pmu_init() register its event checking the pm_event::supported()
> >> handler. For INST_RETIRED, the event is only registered and the
On 8/12/23 01:35, Ilya Leoshkevich wrote:
Currently qemu_target_page_mask() is usable only from the softmmu
code. Make it possible to use it from the *-user code as well.
Make use of it in perf.c.
Signed-off-by: Ilya Leoshkevich
---
accel/tcg/perf.c | 3 ++-
system/physmem.c |
On Fri, 8 Dec 2023 at 09:25, Daniel P. Berrangé wrote:
>
> CC'ing the Xen folks
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > diff --git a/include/hw/xen/xen_native.h b/include/hw/xen/xen_native.h
> > index 6f09c48823..04b1ef4d34 100644
> > ---
On Fri, 2023-12-08 at 09:53 +, Alex Bennée wrote:
> Ilya Leoshkevich writes:
>
> > Preparation for moving perf.c to tcg/.
> >
> > This affects only profiling guest code, which has code in a non-0
> > based
> > segment, e.g., 16-bit code, which is not particularly important.
>
> I have no
On 7/12/23 23:12, Richard Henderson wrote:
On 12/7/23 07:45, Philippe Mathieu-Daudé wrote:
pmu_init() register its event checking the pm_event::supported()
handler. For INST_RETIRED, the event is only registered and the
bit enabled in the PMU Common Event Identification register when
icount is
On Fri, Dec 08, 2023 at 08:47:07AM +, Richard W.M. Jones wrote:
> (Adding Xen maintainers)
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error:
On Fri, Dec 08, 2023 at 08:47:07AM +, Richard W.M. Jones wrote:
> (Adding Xen maintainers)
>
> On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> > Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> > with errors like
> > ../hw/arm/xen_arm.c:74:5: error:
Ilya Leoshkevich writes:
> Preparation for moving perf.c to tcg/.
>
> This affects only profiling guest code, which has code in a non-0 based
> segment, e.g., 16-bit code, which is not particularly important.
I have no objection to removing the wart. Is it worth adding a note:: to
tcg.rst to
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 8.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.2.0-rc3.tar.xz
According to the specification, the th.dcache.cvall1 can be executed
under all priviledges.
The specification about xtheadcmo located in,
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc
Signed-off-by: LIU Zhiwei
---
aziz tlili writes:
> Do u guys have some free time to develop kext files "drivers" for VirtIO
> devices (like virtio-gpu-pci and virtio-blk-pci and
> virtio-net-pci) for PowerPC MacOS X Tiger (10.4.11) and later (till
> Leopard 10.5)? Please, I need them as soon as possible!
I don't think open
On Thu, Dec 07, 2023 at 11:47:35PM +0800, Hyman Huang wrote:
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized cryptographic
On Thu, Dec 07, 2023 at 11:30:45PM +0800, Hyman Huang wrote:
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized cryptographic
Pavel Dovgalyuk writes:
> On 05.12.2023 23:41, Alex Bennée wrote:
>> A lot of the hang I see are when we end up spinning in
>> rr_wait_io_event for an event that will never come in playback. As a
>> new check functions which can see if we are in PLAY mode and kick us
>> us the wait function so
CC'ing the Xen folks
On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> Builds of qemu-8.2.0rc2 with xen-4.18.0 are currently failing
> with errors like
> ../hw/arm/xen_arm.c:74:5: error: ‘GUEST_VIRTIO_MMIO_SPI_LAST’ undeclared
> (first use in this function)
>74 |
The right fdt memory node like [1], not [2]
[1]
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x1000>;
};
[2]
memory@0 {
device_type = "memory";
reg = <0x02 0x00 0x02 0x1000>;
};
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
drivers/irqchip/irq-loongson-eiointc.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 30 +-
include/hw/intc/loongarch_extioi.h | 1 +
2 files changed, 30
Add init_systab and set boot_info->a2
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 39 +
include/hw/loongarch/boot.h | 50 +
2 files changed, 89 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 29 +++--
include/hw/loongarch/boot.h | 9 +
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 60babe3a6e..991df2cc14 100644
---
Move some boot functions to boot.c and struct
loongarch_boot_info into struct LoongArchMachineState.
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 125
hw/loongarch/meson.build| 1 +
hw/loongarch/virt.c | 110
fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'.
See:
drivers/irqchip/irq-loongson-pch-msi.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 33 -
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 33 insertions(+), 1 deletion(-)
diff
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 31 +--
1 file changed, 1 insertion(+), 30 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 2f953e4a03..7dfad60368 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -415,34 +415,6
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 69 ++---
1 file changed, 65 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 915357ca71..2f953e4a03 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 45 +
hw/loongarch/virt.c | 11 ++---
include/hw/loongarch/boot.h | 27 ++
include/hw/loongarch/virt.h | 10 +
4 files changed, 84 insertions(+), 9 deletions(-)
uart node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 7dfad60368..bd1db2de4f 100644
--- a/hw/loongarch/virt.c
+++
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