On 13.12.2023 10:31, Marc-André Lureau wrote:
Hi
On Wed, Dec 13, 2023 at 11:08 AM Dmitry Frolov wrote:
Division by zero may occur in rare constellation of conditions if:
1. not TrueColor mode on the client side
tight_detect_smooth_image16() and tight_detect_smooth_image32(),
Hi
On Wed, Dec 13, 2023 at 11:08 AM Dmitry Frolov wrote:
>
> Division by zero may occur in rare constellation of conditions if:
> 1. not TrueColor mode on the client side
>tight_detect_smooth_image16() and tight_detect_smooth_image32(),
>defined by macro DEFINE_DETECT_FUNCTION()2, are
On 12/12/23 20:35, Richard Henderson wrote:
Reduce atomicity while emitting opcodes, instead of later
during code generation. This ensures that any helper called
also sees the reduced atomicity requirement.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2034
Signed-off-by: Richard
On Tue, Dec 12, 2023 at 5:33 AM Jason Wang wrote:
> On Mon, Dec 11, 2023 at 7:51 PM Yuri Benditovich
> wrote:
> >
> > Hello Jason,
> > Can you please let us know what happens with this series?
>
> It should be my bad, it is in V1 of the pull request but missed
> accidentally in V2 of the pull.
On Fri, Dec 8, 2023 at 10:44 AM LIU Zhiwei wrote:
>
> According to the specification, the th.dcache.cvall1 can be executed
> under all priviledges.
> The specification about xtheadcmo located in,
> https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc
>
>
Division by zero may occur in rare constellation of conditions if:
1. not TrueColor mode on the client side
tight_detect_smooth_image16() and tight_detect_smooth_image32(),
defined by macro DEFINE_DETECT_FUNCTION()2, are affected.
2. if all pixels on the screen are equal, then pixels ==
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
---
include/hw/core/cpu.h | 3 ++-
target/s390x/cpu.h | 2 --
gdbstub/gdbstub.c | 5 -
target/arm/cpu.c| 1 -
target/arm/cpu64.c | 1 -
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
target/ppc/cpu-qom.h | 1 +
target/ppc/cpu.h |
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
---
accel/tcg/plugin-helpers.h | 3 ++-
include/qemu/plugin.h | 1 +
accel/tcg/plugin-gen.c | 43 +++
plugins/api.c | 12 ++--
4
Based-on: <20231213-riscv-v7-0-a760156a3...@daynix.com>
("[PATCH v7 0/4] gdbstub and TCG plugin improvements")
I and other people in the University of Tokyo, where I research
processor design, found TCG plugins are very useful for processor design
exploration.
The feature we find missing is the
It is based on GDB protocol to ensure interface stability.
The timing of the vcpu init hook is also changed so that the hook will
get called after GDB features are initialized.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Signed-off-by: Akihiko Odaki
---
gdb_find_feature() and gdb_find_feature_register() find registers.
gdb_read_register() actually reads registers.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 29 +
gdbstub/gdbstub.c | 31 ++-
2 files changed, 59
This demonstrates how a register can be read from a plugin.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 10 +++-
contrib/plugins/execlog.c | 120 +
2 files changed, 97 insertions(+), 33 deletions(-)
diff --git
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
gdbstub/gdbstub.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
include/exec/gdbstub.h | 6 +++
gdbstub/gdbstub.c | 118
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 3 +++
gdbstub/gdbstub.c | 12 +---
This function is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
include/hw/core/cpu.h | 4
target/arm/cpu.h | 6 --
target/ppc/cpu.h | 1 -
target/arm/cpu.c | 1 -
target/arm/gdbstub.c | 18 --
target/ppc/cpu_init.c | 3
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Acked-by: Richard Henderson
---
target/arm/cpu.h | 21
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.h | 5 ++--
target/riscv/cpu.c | 4 +--
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by: Alex Bennée
---
On 2023/12/13 0:39, Stefan Hajnoczi wrote:
The Big QEMU Lock (BQL) has many names and they are confusing. The
actual QemuMutex variable is called qemu_global_mutex but it's commonly
referred to as the BQL in discussions and some code comments. The
locking APIs, however, are called
On 2023/12/13 0:38, Rene Engel wrote:
--- Ursprüngliche Nachricht ---
Von: Akihiko Odaki
Datum: 11.12.2023 06:39:35
An: Peter Maydell , Philippe Mathieu-Daudé ,
Gerd Hoffmann , Marc-André Lureau
Betreff: [PATCH v6] ui/cocoa: Use NSWindow's ability to resize
Tested-by:
Thanks for
Ping again.
On Tue, Dec 05, 2023 at 03:48:07PM +0800, Ethan Chen wrote:
> Ping.
> https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/
>
> On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote:
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
>
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.h | 4 +-
target/riscv/cpu.c | 118 +++--
target/riscv/gdbstub.c | 12 +++--
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 21 +
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
Acked-by: LIU Zhiwei
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 15 +++
The effective MXL value matters when booting.
Signed-off-by: Akihiko Odaki
---
hw/riscv/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0ffca05189f0..bc67c0bd1890 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,7
There are two interface pairs for MemoryRegionOps, read/write and
read_with_attrs/write_with_attrs. The later is better for ipi device
emulation since initial cpu can be parsed from attrs.requester_id.
And requester_id can be overrided for IOCSR_IPI_SEND and mail_send
function when it is to
On LoongArch system, there is iocsr address space simliar system io
address space on x86. And each cpu has its separate iocsr address space now,
with this patch, iocsr address space is changed with per-board, and
MemTxAttrs.requester_id is used to differentiate cpu cores.
Bibo Mao (2):
LoongArch system has iocsr address space, most iocsr registers are
per-board, however some iocsr register spaces banked for percpu such
as ipi mailbox and extioi interrupt status. For banked iocsr space,
each cpu has the same iocsr space, but separate data.
This patch changes iocsr address space
All tests using pxa2xx_mmc to access mmc cards on pxa2xx platforms
such as borzoi fail starting with commit a2e1753b80 ("memory: prevent
dma-reentracy issues"). Disable reentrancy guard to fix the problem.
Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues")
Signed-off-by: Guenter Roeck
在 2023/12/12 下午8:39, Peter Maydell 写道:
On Wed, 25 Oct 2023 at 10:29, Song Gao wrote:
The result of the LSX instruction is in the low 128 bits
of the vreg register. We use clean_lsx_result() to clean up
the high 128 bits of the vreg register.
Signed-off-by: Song Gao
---
loongarch64.risu
On Wed, Nov 22, 2023 at 4:38 AM Markus Armbruster wrote:
>
> John Snow writes:
>
> > On Tue, Nov 21, 2023, 8:33 AM Markus Armbruster wrote:
> >
> >> John Snow writes:
> >>
> >> > It simplifies typing to mandate that entities will always have a name;
> >> > to achieve this we can occasionally
On Tue, 12 Dec 2023, Peter Maydell wrote:
On Tue, 12 Dec 2023 at 18:46, BALATON Zoltan wrote:
On Tue, 12 Dec 2023, Marek Glogowski wrote:
Additionally, how can I use this message on qemu-devel.
It has a post for people who use Macos or Asahi Linux. Verify random qemu
sessions under Macos
In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
Failure to do so results in incorrect memory exceptions to the guest.
Before 732d548732ed, this was implicitly done via truncation to
target_ulong but only in qemu-system-i386, not qemu-system-x86_64.
To fix this, we must add
Reduce atomicity while emitting opcodes, instead of later
during code generation. This ensures that any helper called
also sees the reduced atomicity requirement.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2034
Signed-off-by: Richard Henderson
Tested-by: Alex Bennée
Message-Id:
The following changes since commit 9c74490bff6c8886a922008d0c9ce6cae70dd17e:
Update version for v8.2.0-rc3 release (2023-12-06 14:34:20 -0500)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20231212
for you to fetch changes up
On Tue, 12 Dec 2023 at 18:46, BALATON Zoltan wrote:
>
> On Tue, 12 Dec 2023, Marek Glogowski wrote:
> > Additionally, how can I use this message on qemu-devel.
> > It has a post for people who use Macos or Asahi Linux. Verify random qemu
> > sessions under Macos .Some are faster others are slow.
On Tue, Dec 12, 2023 at 10:22 PM Richard Henderson
wrote:
> > Looks good, but perhaps you could also squash the following?
> >
> > diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> > index 2c6a12c8350..83ee89579b8 100644
> > --- a/target/i386/tcg/tcg-cpu.c
> > +++
On 12/12/23 13:08, Paolo Bonzini wrote:
On Tue, Dec 12, 2023 at 6:25 PM Richard Henderson
wrote:
In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
Failure to do so results in incorrect memory exceptions to the guest.
Before 732d548732ed, this was implicitly done via truncation
On Tue, Dec 12, 2023 at 6:25 PM Richard Henderson
wrote:
>
> In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
> Failure to do so results in incorrect memory exceptions to the guest.
> Before 732d548732ed, this was implicitly done via truncation to
> target_ulong but only in
I am waiting for review comments before tagging v8.2.0-rc4. There are
already other patches queued for -rc4 so we definitely need another
week before the final release anyway.
Stefan
Richard Henderson writes:
> Reduce atomicity while emitting opcodes, instead of later
> during code generation. This ensures that any helper called
> also sees the reduced atomicity requirement.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2034
> Signed-off-by: Richard Henderson
Reduce atomicity while emitting opcodes, instead of later
during code generation. This ensures that any helper called
also sees the reduced atomicity requirement.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2034
Signed-off-by: Richard Henderson
---
tcg/tcg-op-ldst.c | 28
Hao Xiang writes:
> * Create a dedicated thread for DSA task completion.
> * DSA completion thread runs a loop and poll for completed tasks.
> * Start and stop DSA completion thread during DSA device start stop.
>
> User space application can directly submit task to Intel DSA
> accelerator by
On Tue, 12 Dec 2023, Marek Glogowski wrote:
Additionally, how can I use this message on qemu-devel.
It has a post for people who use Macos or Asahi Linux. Verify random qemu
sessions under Macos .Some are faster others are slow.
The topic is posted on qemu-disc...@nongnu.org (I don't know if
On Tue, 5 Dec 2023 at 09:52, Sai Pavan Boddu wrote:
>
> This property allows users to change flash model on command line as
> below.
>
>ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/arm/xlnx-versal-virt.c | 31 ++-
In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
Failure to do so results in incorrect memory exceptions to the guest.
Before 732d548732ed, this was implicitly done via truncation to
target_ulong but only in qemu-system-i386, not qemu-system-x86_64.
To fix this, we must add
On Thu, 23 Nov 2023 at 14:39, Philippe Mathieu-Daudé wrote:
>
> Cast the CPU to DeviceState once.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 23 Nov 2023 at 14:39, Philippe Mathieu-Daudé wrote:
>
> First run the code that can return errors, then on success
> run what alters the instance state.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/bcm2836.c | 14 +++---
> 1 file changed, 7 insertions(+), 7
On Thu, 23 Nov 2023 at 14:39, Philippe Mathieu-Daudé wrote:
>
> Simplify few qdev_prop_set_bit("start-powered-off") and re-indent.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 23 Nov 2023 at 14:38, Philippe Mathieu-Daudé wrote:
>
> The QOM API is lower level than the QDev one. When an instance is
> QDev and setting the property can not fail (using _abort),
> prefer qdev_prop_set_bit() over object_property_set_bool().
>
> Mechanical transformation using the
If a vcpu with an apic-id that is not supported by the legacy
interface (>255) is hot-plugged, the legacy code will dynamically switch
to the modern interface. However, the hotplug event is not forwarded to
the new interface resulting in the vcpu not being fully/properly added
to the machine
On Thu, 23 Nov 2023 at 14:38, Philippe Mathieu-Daudé wrote:
>
> The 'start-powered-off' property has been added to ARM CPUs in
> commit 5de164304a ("arm: Allow secondary KVM CPUs to be booted
> via PSCI"), then eventually got generalized to all CPUs in commit
> c1b701587e ("target/arm: Move
On Thu, 23 Nov 2023 at 14:38, Philippe Mathieu-Daudé wrote:
>
> The 'mp-affinity' property is present since commit 15a21fe028
> ("target-arm: Add mp-affinity property for ARM CPU class").
> Use it and remove a /* TODO */ comment. Since all ARM CPUs
> have this property, use _abort, because this
On Thu, 23 Nov 2023 at 14:38, Philippe Mathieu-Daudé wrote:
>
> bcm2836_realize() is called by
>
> - bcm2836_class_init() which sets:
>
> bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7")
>
> - bcm2837_class_init() which sets:
>
> bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53")
>
> Both
On Tue, 5 Dec 2023 at 10:08, Sai Pavan Boddu wrote:
>
> The OSPI DMA reads flash data through the OSPI linear address space (the
> iomem_dac region), because of this the reentrancy guard introduced in
> commit a2e1753b ("memory: prevent dma-reentracy issues") is disabled for
> the memory region.
Now that all boards set the "cpu-type" property,
the legacy code can be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/a9mpcore.c | 8 +++-
hw/cpu/cortex_mpcore.c | 8 +---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/cpu/a9mpcore.c
Set the properties on the a7mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx6ul.h | 4
hw/arm/fsl-imx6ul.c | 24 ++--
hw/arm/mcimx6ul-evk.c | 3 ++-
3 files
Set the properties on the a9mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx6.h | 4
hw/arm/fsl-imx6.c | 47 +++
hw/arm/sabrelite.c| 4
Set the properties on the mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/vexpress.c | 51 ++-
1 file changed, 6 insertions(+), 45 deletions(-)
diff --git
All callers access the 'num-cores' property.
Signed-off-by: Philippe Mathieu-Daudé
---
Better to squash earlier and replace in place, so no need for alias?
---
hw/cpu/arm11mpcore.c | 1 -
hw/cpu/cortex_mpcore.c | 2 --
hw/cpu/realview_mpcore.c | 1 -
3 files changed, 4 deletions(-)
diff
Add support for creating the MPCore CPU cluster in the
abstract TYPE_CORTEX_MPCORE_PRIV parent realize() handler.
Only do so if the 'cpu-type' property is set, so current
behavior is not modified. Boards will be converted by
setting this property.
Signed-off-by: Philippe Mathieu-Daudé
---
Set the properties on the a7mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx7.h | 4 ---
hw/arm/fsl-imx7.c | 62 +--
hw/arm/mcimx7d-sabre.c| 3 +-
A15MPPrivState doesn't contain anything else but its parent,
CortexMPPrivState. Remove it in favor of the parent.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/aspeed_soc.h| 2 +-
include/hw/arm/fsl-imx6ul.h| 2 +-
include/hw/arm/fsl-imx7.h | 2 +-
Previous commits (in particular "Create CPUs once in MPCore parent")
allowed creating the MPCore private container vCPUs within the
container. We don't need to call qemu_get_cpu(), which is unsafe in
hegerogeneous context.
Directly access the CortexMPPrivState::cpu array.
Signed-off-by: Philippe
Set the properties on the mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/highbank.c | 53 +++
1 file changed, 8 insertions(+), 45 deletions(-)
diff --git
Set the properties on the a7mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/aspeed_soc.h | 1 -
hw/arm/aspeed_ast2600.c | 58 -
2 files changed, 18 insertions(+),
Set the properties on the a9mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/exynos4210.h | 4 +--
hw/arm/exynos4210.c | 62 +
hw/arm/exynos4_boards.c | 6
Set the properties on the mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/xilinx_zynq.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c
Merge Cortex-A{9,15} MPCore devices in the same header.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 3 +-
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/arm/exynos4210.h | 2 +-
include/hw/arm/fsl-imx6.h
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/a15mpcore.c | 21 +
This type will be common to A9MPCORE/A15MPCORE devices.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 21 +
hw/cpu/cortex_mpcore.c | 22 ++
hw/arm/Kconfig | 3 +++
hw/cpu/meson.build | 1 +
ARM MPCore Kconfig are defined in hw/arm/Kconfig.
hw/cpu/Kconfig is never used, remove it.
Fixes: 82f5181777 ("kconfig: introduce kconfig files")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/Kconfig | 8
1 file changed, 8 deletions(-)
delete mode 100644 hw/cpu/Kconfig
diff --git
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/cortex_mpcore.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c
index c9ba254818..75324268fa 100644
--- a/hw/cpu/cortex_mpcore.c
+++ b/hw/cpu/cortex_mpcore.c
@@ -43,6 +43,13 @@ static void
Set the properties on the mpcore object to let it create and
wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/npcm7xx.h | 1 -
hw/arm/npcm7xx.c | 48 ++--
2 files changed, 12 insertions(+), 37
For QEMU modelling, the only difference between the A15 and A7
MPCore is the latter can have up to 480 SPIs.
In particular, since commit b151de69f6 ("hw/arm: ast2600: Set
AST2600_MAX_IRQ to value from datasheet") the AST2600 machine
initializes its GIC with 256 SPIs, which is more than the 224
Move the GIC instance creation to the abstract QOM parent.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 31 +--
hw/cpu/a15mpcore.c | 56 --
hw/cpu/a9mpcore.c | 43 +-
TYPE_CORTEX_MPCORE_PRIV becomes the common parent to
TYPE_A9MPCORE_PRIV and TYPE_A15MPCORE_PRIV.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 6 --
hw/cpu/a15mpcore.c | 14 --
hw/cpu/a9mpcore.c | 13 +++--
No need to duplicate and forward the 'num-cpu' property from
TYPE_ARM11MPCORE_PRIV to TYPE_REALVIEW_MPCORE, alias it with
QOM object_property_add_alias().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/realview_mpcore.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git
Move the 'num-irq' property to the abstract QOM parent.
Rename it as 'gic-irq', keeping it aliased as 'num-irq'.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 13 +
hw/cpu/a15mpcore.c | 28 +---
hw/cpu/a9mpcore.c
Move the 'has_el2' and 'has_el3' properties to the abstract
QOM parent.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 5 +
hw/arm/exynos4210.c| 10 --
hw/arm/vexpress.c | 6 ++
hw/arm/xilinx_zynq.c | 6 ++
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h
index 4697fd47c7..73627bc415 100644
--- a/include/hw/cpu/cortex_mpcore.h
+++
The A7MPCore forward the IRQs from its internal GIC.
To make the code clearer, add a 'gic' variable.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/fsl-imx7.c | 38 +-
1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/hw/arm/fsl-imx7.c
Move the 'num_cpu' property to the abstract QOM parent.
Rename it as 'num_cores', keeping it aliased as 'num_cpu'.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 9 +++--
hw/arm/aspeed_ast2600.c| 2 +-
hw/arm/exynos4210.c| 2 +-
Move the memory region container creation to the abstract QOM
parent. Children set the region size via the class 'container_size'
field.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cpu/cortex_mpcore.h | 10 --
hw/cpu/a15mpcore.c | 17 -
'busdev' is the internal GIC as SysBus device.
Since we already have a 'gicdev' variable for the GIC as QDev,
rename 'busdev' as 'gicsbd' to make it clear we access the IRQ
lines from the GIC.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/a15mpcore.c | 16
1 file changed, 8
On Tue, 12 Dec 2023 at 11:02, Volodymyr Babchuk
wrote:
>
>
> Hi Stefan,
>
> Stefan Hajnoczi writes:
>
> > On Tue, 12 Dec 2023 at 10:36, Volodymyr Babchuk
> > wrote:
> >>
> >> Hi Anthony
> >>
> >> Anthony PERARD writes:
> >>
> >> > On Fri, Dec 08, 2023 at 02:49:27PM -0800, Stefano Stabellini
In heterogeneous setup the first vCPU might not be
the one expected, better pass it explicitly.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/boot.h | 4 +++-
hw/arm/boot.c | 11 ++-
hw/arm/virt.c | 2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
The A7MPCore forward the IRQs from its internal GIC.
To make the code clearer, add a 'gic' variable.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/fsl-imx6ul.c | 38 ++
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/hw/arm/fsl-imx6ul.c
The A9MPCore forward the IRQs from its internal GIC.
To make the code clearer, add a 'gic' variable.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/fsl-imx6.c | 37 +
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/hw/arm/fsl-imx6.c
Hi,
When a MPCore cluster is used, the Cortex-A cores belong the the
cluster container, not to the board/soc layer. This series move
the creation of vCPUs to the MPCore private container.
Doing so we consolidate the QOM model, moving common code in a
central place (abstract MPCore parent).
This
We don't currently document the syntax of .hx files anywhere
except in a few comments at the top of individual .hx files.
We don't even have somewhere in the developer docs where we
could do this.
Add a new files docs/devel/docs.rst which can be a place to
document how our docs build process
Hao Xiang writes:
> * Use a safe thread queue for DSA task enqueue/dequeue.
> * Implement DSA task submission.
> * Implement DSA batch task submission.
>
> Signed-off-by: Hao Xiang
> ---
> include/qemu/dsa.h | 35
> util/dsa.c | 196
Hi Stefan,
Stefan Hajnoczi writes:
> On Tue, 12 Dec 2023 at 10:36, Volodymyr Babchuk
> wrote:
>>
>> Hi Anthony
>>
>> Anthony PERARD writes:
>>
>> > On Fri, Dec 08, 2023 at 02:49:27PM -0800, Stefano Stabellini wrote:
>> >> On Fri, 8 Dec 2023, Daniel P. Berrangé wrote:
>> >> > On Thu, Dec 07,
Stefano Stabellini writes:
> +Stewart
>
> On Fri, 8 Dec 2023, Mykyta Poturai wrote:
>> Hello everyone,
>>
>> I am currently working on adding MSI support to virtio-pci on ARM with Xen.
>
> Excellent!
>
>
>> As far as I understand QEMU Xen ARM machine that is used for
>> virtio-pci device
On Tue, Dec 12, 2023 at 03:35:50PM +, Volodymyr Babchuk wrote:
> Hi Anthony
>
> Anthony PERARD writes:
>
> > On Fri, Dec 08, 2023 at 02:49:27PM -0800, Stefano Stabellini wrote:
> >> On Fri, 8 Dec 2023, Daniel P. Berrangé wrote:
> >> > On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young
On Tue, 12 Dec 2023 at 10:36, Volodymyr Babchuk
wrote:
>
> Hi Anthony
>
> Anthony PERARD writes:
>
> > On Fri, Dec 08, 2023 at 02:49:27PM -0800, Stefano Stabellini wrote:
> >> On Fri, 8 Dec 2023, Daniel P. Berrangé wrote:
> >> > On Thu, Dec 07, 2023 at 11:12:48PM +, Michael Young wrote:
> >>
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