Re: [Qemu-devel] [PATCH 4/4] arm: Add an RX8900 RTC to the ASpeed board

On Wed, 2016-11-23 at 09:48 +0100, Cédric Le Goater wrote: > On 11/23/2016 01:46 AM, Alastair D'Silva wrote: > > On Tue, 2016-11-22 at 17:56 +0100, Cédric Le Goater wrote: > > > On 11/17/2016 05:36 AM, Alastair D'Silva wrote: > > > > > > > > > > > > From: Alastair D'Silva >

Re: [Qemu-devel] [PATCH 2/4] hw/misc: add a TMP42{1, 2, 3} device model

On Mon, 2016-11-14 at 08:14 +0100, Cédric Le Goater wrote: > > Given the starting point of the tmp105 code the patch looks okay, but I > > was a bit thrown by the use of the 'len' member as what I'd consider an > > index. For instance we reset len to zero in tmp421_event() after > > populating

Re: [Qemu-devel] [PATCH 6/6] aspeed: add support for the SMC segment registers

es a certain number of checks before doing > so. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/ssi/aspeed_smc.c | 135 > ++-- >  1 file changed, 130 inser

Re: [Qemu-devel] [PATCH 5/6] aspeed: create mapping regions for the maximum number of slaves

e controller. > > Also rewrite a bit the comments in the code on this topic. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/ssi/aspeed_smc.c | 16 +--- >  1 file changed, 13 insertion

Re: [Qemu-devel] [PATCH 4/6] aspeed: add support for the AST2500 SoC SMC controllers

BMC SPI controller and add a new > SPI controller for the host. We also have to introduce new type names > to handle the differences in the flash modules memory mappping. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and..

Re: [Qemu-devel] [PATCH 3/6] aspeed: extend the number of host SPI controllers

On Tue, 2016-09-27 at 13:57 +0200, Cédric Le Goater wrote: > The AST2500 SoC has two. Let's prepare ground for the next changes > which will add the required definitions for the second host SPI > controller. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Review

Re: [Qemu-devel] [PATCH 2/6] aspeed: move the flash module mapping address under the controller definition

ic Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed_soc.c |  9 - >  hw/ssi/aspeed_smc.c | 15 +++ >  include/hw/ssi/aspeed_smc.h |  3 ++- >  3 files changed, 17 insertions(+), 10 deletions(

Re: [Qemu-devel] [PATCH 1/6] aspeed: rename the smc object to fmc

AST2500 SoC and the SMC, which was still available > on the AST2400 SoC, was removed. > > The Aspeed SoC does not provide support for the legacy SMC > controller. So, let's rename the 'smc' object to 'fmc' to clarify its > nature. > > Signed-off-by: Cédric Le Goater <c...@ka

Re: [Qemu-devel] [PATCH v5 14/14] aspeed: allocate RAM after the memory controller has checked the size

On Fri, 2016-09-09 at 18:22 +0200, Cédric Le Goater wrote: > If the RAM size is invalid, the memory controller will use a default > value. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed.c | 1

Re: [Qemu-devel] [PATCH v5 13/14] aspeed: add a ram_size property to the memory controller

On Fri, 2016-09-09 at 18:22 +0200, Cédric Le Goater wrote: > Configure the size of the RAM of the SOC using a property to propagate > the value down to the memory controller from the board level. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffer

Re: [Qemu-devel] [PATCH v5 12/14] aspeed: use error_report instead of LOG_GUEST_ERROR

On Fri, 2016-09-09 at 18:22 +0200, Cédric Le Goater wrote: > Also change the default value used in case of an error. The minimum > size is a bit severe, so let's just use an average RAM size. I'm not sure we should be switching the default value in this patch, but I'm not sure it's worth any

Re: [Qemu-devel] [PATCH v5 11/14] aspeed: calculate the RAM size bits at realize time

On Fri, 2016-09-09 at 18:22 +0200, Cédric Le Goater wrote: > There is no need to do this at each reset as the RAM size will not > change. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/m

Re: [Qemu-devel] [PATCH v3 10/10] palmetto-bmc: remove extra no_sdcard assignement

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed.c | 1 - >  1 file changed, 1 deletion(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm

Re: [Qemu-devel] [PATCH v3 09/10] arm: add support for an ast2500 evaluation board

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > The ast2500 eval board has a hardware strapping register value of > 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1 > below. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Review

Re: [Qemu-devel] [PATCH v3 08/10] aspeed: add a AST2500 SoC and support to the SCU and SDMC controllers controllers

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > Based on previous work done by Andrew Jeffery <and...@aj.id.au>. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- > >  Changes since

Re: [Qemu-devel] [PATCH v3 07/10] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > This gives some explanation behind the magic number 0x120CE416. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- > >  Changes since v2: > >  

Re: [Qemu-devel] [PATCH v3 06/10] palmetto-bmc: add board specific configuration

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > aspeed_board_init() now uses a board identifier to customize some values > specific to the board. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> >

Re: [Qemu-devel] [PATCH v3 05/10] palmetto-bmc: replace palmetto_bmc with aspeed

ic Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed.c | 56 +--- >  1 file changed, 37 insertions(+), 19 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c

Re: [Qemu-devel] [PATCH v3 04/10] palmetto-bmc: rename the Aspeed board file to aspeed.c

On Tue, 2016-08-02 at 19:15 +0200, Cédric Le Goater wrote: > We plan to add more Aspeed boards to this file. There are no changes > in the code. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/Mak

Re: [Qemu-devel] [PATCH v3 03/10] aspeed-soc: provide a framework to add new SoCs

-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed_soc.c | 27 --- >  hw/arm/palmetto-bmc.c   | 12 >  include/hw/arm/aspeed_soc.h | 17 - >  3

Re: [Qemu-devel] [PATCH v3 02/10] ast2400: replace ast2400 with aspeed_soc

SoC AST2500, so this provides us a better common base for > the address space mapping on both SoCs. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  hw/arm/aspeed_soc.c | 95 ++-

Re: [Qemu-devel] [PATCH v3 01/10] ast2400: rename the Aspeed SoC files to aspeed_soc

peed_soc.o palmetto-bmc.o > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > new file mode 100644 > index ..b272f4e48cfc > --- /dev/null > +++ b/hw/arm/aspeed_soc.c > @@ -0,0 +1,229 @@ > +/* > + * AST2400 SoC > + * > + * Andrew Jeffery <and...@aj

Re: [Qemu-devel] [PATCH 1/6] palmetto-bmc: add a "silicon-rev" property at the soc level

On Sat, 2016-07-30 at 10:35 +0200, Cédric Le Goater wrote: > On 07/29/2016 03:16 AM, Andrew Jeffery wrote: > > > > On Thu, 2016-07-28 at 09:51 +0200, Cédric Le Goater wrote: > > > > > > On 07/28/2016 04:14 AM, Andrew Jeffery wrote: > > > > >

Re: [Qemu-devel] [PATCH 1/6] palmetto-bmc: add a "silicon-rev" property at the soc level

On Thu, 2016-07-28 at 09:51 +0200, Cédric Le Goater wrote: > On 07/28/2016 04:14 AM, Andrew Jeffery wrote: > > > > On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > > > > > > The SCU controler holds the board revision number in its 0x7C > >

Re: [Qemu-devel] [PATCH 6/6] arm: add support for an ast2500 evaluation board

On Thu, 2016-07-28 at 09:15 +0200, Cédric Le Goater wrote: > >  > > Also, the meaning of the bits have changed from the AST2400 - they > > probably should be documented somewhere? > > So you want me send to an updated version of : > >

Re: [Qemu-devel] [PATCH 6/6] arm: add support for an ast2500 evaluation board

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater > --- >  hw/arm/palmetto-bmc.c| 32 +++- >  include/hw/arm/ast2400.h |  5 + >  2 files changed, 36 insertions(+), 1 deletion(-) > > diff --git

Re: [Qemu-devel] [PATCH 2/6] palmetto-bmc: replace palmetto_bmc with aspeed

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > This is mostly a name replacement to prepare ground for other socs > specificities. It also adds a specific TypeInfo struct for the > palmetto_bmc board with a custom initialization for the same reason. I think we should rename the

Re: [Qemu-devel] [PATCH 5/6] aspeed: add ast2500 support to scu and sdmc controllers

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > Based on previous work done by Andrew Jeffery <and...@aj.id.au>. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --- >  

Re: [Qemu-devel] [PATCH 4/6] palmetto-bmc: add board specific configuration

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > aspeed_init() now uses a board identifier to customize some values > specific to the board, ram base, board revision number, etc. > > Signed-off-by: Cédric Le Goater Looks okay to me, some minor comments below: > --- >

Re: [Qemu-devel] [PATCH 3/6] ast2400: use machine cpu_model to initialize the soc cpu

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > It will be easier to specify a different cpu for other soc derived > from the ast2400 soc. > > Signed-off-by: Cédric Le Goater > --- >  hw/arm/ast2400.c  | 8 +++- >  hw/arm/palmetto-bmc.c | 1 + >  2 files

Re: [Qemu-devel] [PATCH 1/6] palmetto-bmc: add a "silicon-rev" property at the soc level

On Wed, 2016-07-27 at 18:46 +0200, Cédric Le Goater wrote: > The SCU controler holds the board revision number in its 0x7C > register. Let's use an alias to link a "silicon-rev" property of the > soc to the "silicon-rev" property of the SCU controler. > > The SDMC controler "silicon-rev" property

Re: [Qemu-devel] [PATCH 7/7] ast2400: add a memory controller device model

On Mon, 2016-07-04 at 14:18 +0200, Cédric Le Goater wrote: > The uboot in the previous release of the SDK was using a hardcoded > value for memory size. This is not true anymore, the value is now > retrieved from the memory controller. > > Below is a model for this device, only supporting unlock

Re: [Qemu-devel] [PATCH] misc/aspeed_scu: Fix build error caused by missing header

In function > ‘aspeed_scu_write’: > /home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c:154:23: error: > ‘LOG_GUEST_ERROR’ undeclared (first use in this function) > > This is caused by a missing header file. Fix it. > > Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com&g

Re: [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device

On Mon, 2016-06-27 at 14:47 +0100, Peter Maydell wrote: > On 24 June 2016 at 05:58, Andrew Jeffery <and...@aj.id.au> wrote: > > > > Hi all, > > > > These are three patches implementing minimal functionality for the ASPEED > > System > > Control Un

Re: [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit

On Mon, 2016-06-27 at 14:42 +0100, Peter Maydell wrote: > On 24 June 2016 at 05:58, Andrew Jeffery <and...@aj.id.au> wrote: > > > > The SCU is a collection of chip-level control registers that manage the > > various functions supported by ASPEED SoCs. Typically the bi

[Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register

: Configure MAC#2 for RMII/NCSI * 6: Configure MAC#1 for RMII/NCSI * 5: No VGA BIOS ROM * 4: Boot using 32bit SPI address mode * 3:2: Select 16MB VGA memory * 1:0: Boot from SPI flash memory Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Cédric Le Goater <c...@kaod.org&

[Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit

-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v2: * Fix mixing of offsets and register indexes * Sanity check device property values * Move trace event definition to hw/misc/trace-events Since v1: * Move reset values into SCU implementation (also make register defines private) *

[Qemu-devel] [PATCH v3 2/3] ast2400: Integrate the SCU model and set silicon revision

By specifying the silicon revision we select the appropriate reset values for the SoC. Additionally, expose hardware strapping properties aliasing those provided by the SCU for board-specific configuration. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Cédric Le Goa

[Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device

hardware strapping values via properties Andrew Jeffery (3): hw/misc: Add a model for the ASPEED System Control Unit ast2400: Integrate the SCU model and set silicon revision palmetto-bmc: Configure the SCU's hardware strapping register hw/arm/ast2400.c | 21 hw/arm/palmetto

Re: [Qemu-devel] [PATCH v2 3/3] palmetto-bmc: Configure the SCU's hardware strapping register

On Thu, 2016-06-23 at 18:39 +0100, Peter Maydell wrote: > On 23 June 2016 at 03:15, Andrew Jeffery <and...@aj.id.au> wrote: > > > > The magic constant configures the following options: > > > > * 28:27: Configure DRAM size as 256MB > > * 26:24: DDR3 SDRAM w

Re: [Qemu-devel] [PATCH v2 1/3] hw/misc: Add a model for the ASPEED System Control Unit

On Thu, 2016-06-23 at 18:42 +0100, Peter Maydell wrote: > On 23 June 2016 at 03:15, Andrew Jeffery <and...@aj.id.au> wrote: > > > > The SCU is a collection of chip-level control registers that manage the > > various functions supported by ASPEED SoCs. Typically the bi

Re: [Qemu-devel] [PATCH v2 1/3] hw/misc: Add a model for the ASPEED System Control Unit

On Thu, 2016-06-23 at 18:37 +0100, Peter Maydell wrote: > On 23 June 2016 at 03:15, Andrew Jeffery <and...@aj.id.au> wrote: > > > > The SCU is a collection of chip-level control registers that manage the > > various functions supported by ASPEED SoCs. Typically the bi

[Qemu-devel] [PATCH v2 3/3] palmetto-bmc: Configure the SCU's hardware strapping register

: Configure MAC#2 for RMII/NCSI * 6: Configure MAC#1 for RMII/NCSI * 5: No VGA BIOS ROM * 4: Boot using 32bit SPI address mode * 3:2: Select 16MB VGA memory * 1:0: Boot from SPI flash memory Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/arm/palmetto-bmc.c | 2 ++ 1 file chan

[Qemu-devel] [PATCH v2 2/3] ast2400: Integrate the SCU model and set silicon revision

By specifying the silicon revision we select the appropriate reset values for the SoC. Additionally, expose hardware strapping properties aliasing those provided by the SCU for board-specific configuration. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v1: * Remove reset

[Qemu-devel] [PATCH v2 1/3] hw/misc: Add a model for the ASPEED System Control Unit

-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v1: * Move reset values into SCU implementation (also make register defines private) * Expose silicon-rev property which is used to select appropriate reset values * Expose hw-strap1/hw-strap2 properties for board-specific SoC configuratio

[Qemu-devel] [PATCH v2 0/3] Add ASPEED SCU device

, influencing the configuration of the software and the software's configuration of the SoC. Since v1: * Select reset values based on silicon ID * Expose hardware strapping values via properties Cheers, Andrew Andrew Jeffery (3): hw/misc: Add a model for the ASPEED System Control Unit ast2400

Re: [Qemu-devel] [PATCH 1/2] hw/misc: Add a model for the ASPEED System Control Unit

On Tue, 2016-06-21 at 07:56 +0100, Peter Maydell wrote: > On 21 June 2016 at 04:49, Andrew Jeffery <and...@aj.id.au> wrote: > > > > On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote: > > > > > > I think there are a couple of plausible ways you might

Re: [Qemu-devel] [PATCH 1/2] hw/misc: Add a model for the ASPEED System Control Unit

On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote: > On 20 June 2016 at 04:44, Andrew Jeffery <and...@aj.id.au> wrote: > > > > On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote: > > > > > > +static Property aspeed_scu_properties[]

Re: [Qemu-devel] [PATCH 1/2] hw/misc: Add a model for the ASPEED System Control Unit

On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote: On 16 June 2016 at 08:48, Andrew Jeffery <and...@aj.id.au> wrote: The SCU is a collection of chip-level control registers that manage the various functions supported by the AST2400. Typically the bits control interactions with

[Qemu-devel] [PATCH 0/2] Add ASPEED SCU device

of the software and the software's configuration of the SoC. Cheers, Andrew Andrew Jeffery (2): hw/misc: Add a model for the ASPEED System Control Unit ast2400: Integrate the SCU model and configure reset values hw/arm/ast2400.c | 57 + hw/misc/Makefile.objs

[Qemu-devel] [PATCH 2/2] ast2400: Integrate the SCU model and configure reset values

Almost all configured reset values are specified by the datasheet. The notable exception is ASPEED_SCU_SOC_SCRATCH1, where we mark the DRAM as successfully initialised by the SoC to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: Andrew Jeffery <and...@aj.id

[Qemu-devel] [PATCH 1/2] hw/misc: Add a model for the ASPEED System Control Unit

of the state to determine how to boot, but the reset values vary from SoC to SoC. qdev properties are exposed so that the integrating SoC model can configure the appropriate reset values. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Cédric Le Goater <c...@kaod.org> Revie

[Qemu-devel] [PATCH v2] hw/timer: Add value matching support to aspeed_timer

Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v1: Address comments from Peter * Switch calculations to use muldiv64() * Switch to loop

Re: [Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

On Fri, 2016-06-10 at 11:42 +0100, Peter Maydell wrote: > On 10 June 2016 at 01:59, Andrew Jeffery <and...@aj.id.au> wrote: > > > > On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote: > > > > > > On 27 May 2016 at 06:08, Andrew Jeffery <and...@aj.id.

Re: [Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote: > On 27 May 2016 at 06:08, Andrew Jeffery <and...@aj.id.au> wrote: > > > > Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the > > palmetto-bmc machine. Two match registers are provided for each

Re: [Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

On Mon, 2016-06-06 at 15:01 +0100, Peter Maydell wrote: > On 27 May 2016 at 06:08, Andrew Jeffery <and...@aj.id.au> wrote: > > > > Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the > > palmetto-bmc machine. Two match registers are provided for each

[Qemu-devel] [PATCH] hw/timer: Add value matching support to aspeed_timer

Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- The change pulls out ptimer in favour of the regular timer infrastructure. As a consequence it impl

Re: [Qemu-devel] [PATCH] i2c: add aspeed i2c crontroller

On Mon, 2016-05-23 at 07:55 +0200, Cédric Le Goater wrote: > >  > > The hunk fails to apply to master as the SCU isn't yet integrated > > there. The change to ast2400.h also fails to apply for this reason. > > Ah yes. I am using your branch for this patch.  > > So, I will provide you a fix for

Re: [Qemu-devel] [PATCH 2/4] hw/misc: add a TMP42{1, 2, 3} device model

Hi Cédric, On Fri, 2016-05-20 at 18:31 +0200, Cédric Le Goater wrote: > Largely inspired by the TMP105 temperature sensor, this patch brings > to Qemu a model for TMP42{1,2,3} temperature sensors. > > Specs can be found here : > > http://www.ti.com/lit/gpn/tmp421 > > Signed-off-by:

Re: [Qemu-devel] [PATCH] i2c: add aspeed i2c crontroller

warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + * > + */ > + > +#include "qemu/osde

[Qemu-devel] [PATCH v5 1/4] hw/timer: Add ASPEED timer device model

configured with aspeed_defconfig. [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v4: * Fix to compile when using GCC 4.x * Drop unnecessary asserts Since v3: * Drop unnecessary mention of VMStateDescription in timer_t

[Qemu-devel] [PATCH v5 4/4] hw/arm: Add palmetto-bmc machine

), but creating specific machine types is preferable to a generic machine that doesn't match any particular hardware. [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v4: * Rename to hw/arm/palmetto-bmc.c, update functions, s

[Qemu-devel] [PATCH v5 0/4] Add ASPEED AST2400 SoC and Palmetto BMC machine

: Addressed reviews/comments from: * Cédric Le Goater Andrew Jeffery (4): hw/timer: Add ASPEED timer device model hw/intc: Add (new) ASPEED VIC device model hw/arm: Add ASPEED AST2400 SoC model hw/arm: Add palmetto-bmc machine default-configs/arm-softmmu.mak | 1 + hw/arm

[Qemu-devel] [PATCH v5 3/4] hw/arm: Add ASPEED AST2400 SoC model

While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Si

[Qemu-devel] [PATCH v5 2/4] hw/intc: Add (new) ASPEED VIC device model

will not be serviced (however the access will be logged). [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v3: * Switch from g_assert() to qemu_log_mask(LOG_GUEST_ERROR, ...) in guest path Since v2: * Implement all sup

Re: [Qemu-devel] [PATCH v4 0/4] Add ASPEED AST2400 SoC and OpenPower BMC machine

On Tue, 2016-03-15 at 11:25 +0100, Cédric Le Goater wrote: > On 03/15/2016 06:01 AM, Andrew Jeffery wrote: > > On Tue, 2016-03-15 at 12:34 +0800, Jeremy Kerr wrote: > > > Hi Andrew, > > > > > > > This patch series models enough of the ASPEED AST2400 ARM9 SoC

Re: [Qemu-devel] [PATCH v4 1/4] hw/timer: Add ASPEED timer device model

On Tue, 2016-03-15 at 14:14 +0100, Cédric Le Goater wrote: > On 03/14/2016 05:13 AM, Andrew Jeffery wrote: > > Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to > > 8 timers can independently be configured, enabled, reset and disabled. > > S

Re: [Qemu-devel] [PATCH v4 1/4] hw/timer: Add ASPEED timer device model

Hi Dmitry, On Tue, 2016-03-15 at 21:14 +0300, Dmitry Osipenko wrote: > Hello Andrew, > > 14.03.2016 07:13, Andrew Jeffery пишет: > > Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to > > 8 timers can independently be configured, enabled, reset a

Re: [Qemu-devel] [PATCH v4 0/4] Add ASPEED AST2400 SoC and OpenPower BMC machine

On Tue, 2016-03-15 at 12:34 +0800, Jeremy Kerr wrote: > Hi Andrew, > > > This patch series models enough of the ASPEED AST2400 ARM9 SoC[0] to > > boot an aspeed_defconfig Linux kernel[1][2]. Specifically, the series > > implements the ASPEED timer and VIC devices, integrates them into an > >

[Qemu-devel] [PATCH v4 1/4] hw/timer: Add ASPEED timer device model

configured with aspeed_defconfig. [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v3: * Drop unnecessary mention of VMStateDescription in timer_to_ctrl description * Mention hw/timer/a9gtimer.c with respect to clock value ma

[Qemu-devel] [PATCH v4 4/4] hw/arm: Add opbmc2400, an AST2400 OpenPOWER BMC machine

to be a common, formal name for the hardware configuration that isn't generic (e.g. 'BMC' or 'AST2400'). [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v3: * Split the machine from the SoC implementation I've gone the

[Qemu-devel] [PATCH v4 2/4] hw/intc: Add (new) ASPEED VIC device model

will not be serviced (however the access will be logged). [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v3: * Switch from g_assert() to qemu_log_mask(LOG_GUEST_ERROR, ...) in guest path Since v2: * Implement all sup

[Qemu-devel] [PATCH v4 3/4] hw/arm: Add ASPEED AST2400 SoC model

While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20=376 Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Si

[Qemu-devel] [PATCH v4 0/4] Add ASPEED AST2400 SoC and OpenPower BMC machine

* Joel Stanley Changes since v1: Addressed reviews/comments from: * Cédric Le Goater Andrew Jeffery (4): hw/timer: Add ASPEED timer device model hw/intc: Add (new) ASPEED VIC device model hw/arm: Add an ASPEED AST2400 SoC hw/arm: Add opbmc2400, an AST2400-based OpenPOWER BMC machine

Re: [Qemu-devel] [PATCH v3 2/3] hw/intc: Add (new) ASPEED VIC device model

On Fri, 2016-03-11 at 16:03 +0700, Peter Maydell wrote: > On 5 March 2016 at 11:29, Andrew Jeffery <and...@aj.id.au> wrote: > > Implement a basic ASPEED VIC device model, enough to boot a Linux kernel > > configured with aspeed_defconfig. The model implements the 'new' >

Re: [Qemu-devel] [PATCH v3 1/3] hw/timer: Add ASPEED timer device model

On Fri, 2016-03-11 at 15:56 +0700, Peter Maydell wrote: > On 5 March 2016 at 11:29, Andrew Jeffery <and...@aj.id.au> wrote: > > Implement basic AST2400 timer functionality: Up to 8 timers can > > independently be configured, enabled, reset and disabled. A couple of

[Qemu-devel] [PATCH v3 1/3] hw/timer: Add ASPEED timer device model

with aspeed_defconfig. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v2: * Improve handling of timer configuration with respect to enabled state * Remove redundant enabled member from AspeedTimer * Implement VMStateDescriptions * Fix interrupt behaviour (edge triggered, both

[Qemu-devel] [PATCH v3 2/3] hw/intc: Add (new) ASPEED VIC device model

the access will be logged). Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v2: * Implement all supported interrupt types and configurations * Implement a VMStateDescription * Log accesses to legacy IO space * Add documentation on some implementation and hardware details *

[Qemu-devel] [PATCH v3 3/3] hw/arm: Add ASPEED AST2400 machine model

Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- Since v2: * Implement a SOC model to move code out from the machine definition * Rework the machine to better use QOM * Include qemu/osdep.h * Revert back to qemu_log_mask(LOG_UNIMP, ...) in IO handlers Since v1: hw/arm/Makefile.objs

[Qemu-devel] [PATCH v3 0/3] Add ASPEED AST2400 machine model

Maydell * Alexey Kardashevskiy * Joel Stanley Changes since v1: Addressed reviews/comments from: * Cédric Le Goater Andrew Jeffery (3): hw/timer: Add ASPEED timer device model hw/intc: Add (new) ASPEED VIC device model hw/arm: Add ASPEED AST2400 machine model default-configs/arm

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model

On Thu, 2016-03-03 at 08:39 +, Peter Maydell wrote: > On 3 March 2016 at 05:14, Andrew Jeffery <and...@aj.id.au> wrote: > > > > On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote: > > > > > > > > > > > +case 0x20: /* Inte

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model

On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote: > > +case 0x20: /* Interrupt Enable */ > > +s->int_enable |= data; > > Are you sure this only ORs in new 1 bits? As in, am I sure I only want to take the newly set bits? If so, yes, as the the following register serves to clear

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model

Hi Peter, On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote: > On 16 February 2016 at 11:34, Andrew Jeffery <and...@aj.id.au> wrote: > > Implement a minimal ASPEED AVIC device model, enough to boot a Linux > > kernel configured with aspeed_defconfig. The VI

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 1/3] hw/timer: Add ASPEED AST2400 timer device model

On Fri, 2016-02-26 at 10:20 +, Peter Maydell wrote: > On 26 February 2016 at 03:14, Andrew Jeffery <and...@aj.id.au> wrote: > > > > Hi Peter, > > > > On Thu, 2016-02-25 at 16:11 +, Peter Maydell wrote: > > > > > > On 16 February 20

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 1/3] hw/timer: Add ASPEED AST2400 timer device model

Hi Peter, On Thu, 2016-02-25 at 16:11 +, Peter Maydell wrote: > On 16 February 2016 at 11:34, Andrew Jeffery <and...@aj.id.au> wrote: > > Implement basic AST2400 timer functionality: Timers can be configured, > > enabled, reset and disabled. > > > &

[Qemu-devel] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model

the provided offset to understand whether the access is requesting the lower or upper 32bits of the 64bit quantity. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/intc/Makefile.objs| 1 + hw/intc/aspeed_vic.c | 256 +++ include/h

[Qemu-devel] [PATCH v2 1/3] hw/timer: Add ASPEED AST2400 timer device model

with aspeed_defconfig. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- default-configs/arm-softmmu.mak | 2 + hw/timer/Makefile.objs | 2 + hw/timer/aspeed_timer.c | 313 include/hw/timer/aspeed_timer.h | 55 +++ trace-

[Qemu-devel] [PATCH v2 0/3] Add ASPEED AST2400 machine model

: * Refactor initialisation of and respect requested clock rates (APB/External) * Simplify some index calculations === Andrew Jeffery (3): hw/timer: Add ASPEED AST2400 timer device model hw/intc: Add (new) ASPEED AST2400 AVIC device model hw/arm: Add ASPEED AST2400 machine type default

[Qemu-devel] [PATCH v2 3/3] hw/arm: Add ASPEED AST2400 machine type

Adds the AST2400 machine type with ASPEED AVIC and timer models. The new machine type is functional enough to boot Linux to userspace. Signed-off-by: Andrew Jeffery <and...@aj.id.au> --- hw/arm/Makefile.objs | 1 + hw/arm/ast2400.c

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