Re: [PATCH v7 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties

o what we already do with MISA > extensions: the flag set only if the user is changing the extension > state. > > The 'supported' flag will be used later on to make an exception for > users that are disabling multi-letter extensions that are unknown to > KVM. &g

Re: [PATCH v4 0/6] Add RISC-V KVM AIA Support

On Wed, Jun 21, 2023 at 02:54:50PM +, Yong-Xuan Wang wrote: > This series adds support for KVM AIA in RISC-V architecture. > > In order to test these patches, we require Linux with KVM AIA support which > can > be found in the riscv_kvm_aia_hwaccel_v1 branch at > https://github.com/avpatel/li

Re: [PATCH v4 6/6] target/riscv: select KVM AIA in riscv virt machine

On Wed, Jun 21, 2023 at 02:54:56PM +, Yong-Xuan Wang wrote: > Select KVM AIA when the host kernel has in-kernel AIA chip support. > Since KVM AIA only has one APLIC instance, we map the QEMU APLIC > devices to KVM APLIC. > We also extend virt machine to specify the KVM AIA mode. The "kvm-aia" >

Re: [PATCH v4 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA

" HWADDR_PRIx "\n", > @@ -320,10 +334,12 @@ static void riscv_imsic_realize(DeviceState *dev, Error > **errp) > CPUState *cpu = cpu_by_arch_id(imsic->hartid); > CPURISCVState *env = cpu ? cpu->env_ptr : NULL; > > -imsic->num_eistate = imsic->num_pages * imsic->num_irqs; > -imsic->eidelivery = g_new0(uint32_t, imsic->num_pages); > -imsic->eithreshold = g_new0(uint32_t, imsic->num_pages); > -imsic->eistate = g_new0(uint32_t, imsic->num_eistate); > +if (!kvm_irqchip_in_kernel()) { > +imsic->num_eistate = imsic->num_pages * imsic->num_irqs; > +imsic->eidelivery = g_new0(uint32_t, imsic->num_pages); > +imsic->eithreshold = g_new0(uint32_t, imsic->num_pages); > +imsic->eistate = g_new0(uint32_t, imsic->num_eistate); > +} > > memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, >imsic, TYPE_RISCV_IMSIC, > -- > 2.17.1 > > Otherwise, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v4 4/6] target/riscv: Create an KVM AIA irqchip

On Wed, Jun 21, 2023 at 02:54:54PM +, Yong-Xuan Wang wrote: > implement a function to create an KVM AIA chip This is a bit too terse. We should at least summarize the KVM API this uses. > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu > --- > target/riscv/kvm.c | 163 +++

Re: [PATCH v4 3/6] target/riscv: check the in-kernel irqchip support

On Wed, Jun 21, 2023 at 02:54:53PM +, Yong-Xuan Wang wrote: > We check the in-kernel irqchip support when using KVM acceleration. > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu > Reviewed-by: Daniel Henrique Barboza > --- > target/riscv/kvm.c | 13 - > 1 file changed,

Re: [PATCH v4 2/6] target/riscv: support the AIA device emulation with KVM enabled

On Wed, Jun 21, 2023 at 02:54:52PM +, Yong-Xuan Wang wrote: > Remove M mode AIA devices when using KVM acceleration > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu > --- > hw/riscv/virt.c | 207 +--- > 1 file changed, 108 insertions(+), 9

Re: [PATCH v7 12/20] target/riscv: add KVM specific MISA properties

int bit = misa_cfg->offset; > + > +misa_cfg->name = riscv_get_misa_ext_name(bit); > +misa_cfg->description = riscv_get_misa_ext_description(bit); > + > + object_property_add(cpu_obj, misa_cfg->name, "bool", > +NULL, > +kvm_cpu_set_misa_ext_cfg, > +NULL, misa_cfg); > +object_property_set_description(cpu_obj, misa_cfg->name, > +misa_cfg->description); > +} > +} > + > static int kvm_riscv_get_regs_core(CPUState *cs) > { > int ret = 0; > @@ -427,6 +504,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) > return; > } > > +kvm_riscv_add_cpu_user_properties(cpu_obj); > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > > -- > 2.41.0 > Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v7 11/20] target/riscv/cpu: add misa_ext_info_arr[]

ab pipeline though, so code was changed to > make every runner happy. > > As a side effect, misa_ext_cfg[] is no longer a 'const' array because > it must be set during runtime. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > t

Re: [PATCH v6 11/20] target/riscv/cpu: add misa_ext_info_arr[]

On Thu, Jun 29, 2023 at 07:04:28PM -0300, Daniel Henrique Barboza wrote: > Drew, > > On 6/29/23 05:59, Andrew Jones wrote: > > On Wed, Jun 28, 2023 at 06:30:24PM -0300, Daniel Henrique Barboza wrote: > > > Next patch will add KVM specific user properties for both MIS

Re: [PATCH v6 17/20] target/riscv/cpu.c: create KVM mock properties

ty of extensions and can be > + * safely ignored as is. > + */ > +if (prop->info == &qdev_prop_bool) { > +object_property_add(obj, prop->name, "bool", > +NULL, cpu_set_cfg_unavailable, > +NULL, (void *)prop->name); > +continue; > +} > } > #endif > qdev_property_add_static(dev, prop); > -- > 2.41.0 > Reviewed-by: Andrew Jones

Re: [PATCH v6 15/20] target/riscv/cpu.c: add satp_mode properties earlier

} > @@ -1761,10 +1763,6 @@ static void riscv_cpu_add_user_properties(Object *obj) > #endif > qdev_property_add_static(dev, prop); > } > - > -#ifndef CONFIG_USER_ONLY > -riscv_add_satp_mode_properties(obj); > -#endif > } > > static Property riscv_cpu_properties[] = { > -- > 2.41.0 > Reviewed-by: Andrew Jones

Re: [PATCH v6 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties

> Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 8 +++ > target/riscv/kvm.c | 119 + > 2 files changed, 127 insertions(+) > Reviewed-by: Andrew Jones

Re: [PATCH v6 12/20] target/riscv: add KVM specific MISA properties

On Wed, Jun 28, 2023 at 06:30:25PM -0300, Daniel Henrique Barboza wrote: > Using all TCG user properties in KVM is tricky. First because KVM > supports only a small subset of what TCG provides, so most of the > cpu->cfg flags do nothing for KVM. > > Second, and more important, we don't have a way

Re: [PATCH v6 11/20] target/riscv/cpu: add misa_ext_info_arr[]

> extensions. For now doing just with MISA extensions is enough. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 83 ++ > target/riscv/cpu.h | 7 +++- > 2 files changed, 61

Re: [PATCH v6 01/20] target/riscv: skip features setup for KVM CPUs

dev); > +RISCVCPU *cpu = RISCV_CPU(dev); > +RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > +Error *local_err = NULL; > + > + cpu_exec_realizefn(cs, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return; > +} > + > +if (tcg_enabled()) { > +riscv_cpu_realize_tcg(dev, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return; > +} > +} > > riscv_cpu_finalize_features(cpu, &local_err); > if (local_err != NULL) { > -- > 2.41.0 > Reviewed-by: Andrew Jones

Re: [PATCH v5 16/19] target/riscv/cpu.c: create KVM mock properties

ev_prop_bool) { > +object_property_add(obj, prop->name, "bool", > +NULL, cpu_set_cfg_unavailable, > +NULL, (void *)prop->name); > +continue; > +} > } > > qdev_property_add_static(dev, prop); > -- > 2.41.0 > Otherwise, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v5 11/19] target/riscv/cpu: add misa_ext_info_arr[]

gt; > > > There's nothing holding us back from doing the same with multi-letter > > extensions. For now doing just with MISA extensions is enough. > > > > Suggested-by: Andrew Jones > > Signed-off-by: Da

Re: [PATCH v4 16/19] target/riscv/cpu.c: create KVM mock properties

On Mon, Jun 26, 2023 at 07:02:06PM -0300, Daniel Henrique Barboza wrote: > KVM-specific properties are being created inside target/riscv/kvm.c. But > at this moment we're gathering all the remaining properties from TCG and > adding them as is when running KVM. This creates a situation where > non-K

Re: [PATCH v3 12/19] target/riscv: add KVM specific MISA properties

er extensions as well. > > There is no need to duplicate more code than necessary, so we're going > to use the existing kvm_riscv_init_user_properties() to add the KVM > specific properties. Any code that is adding a TCG user prop is then > changed slightly to verify first

Re: [PATCH v3 16/19] target/riscv/cpu.c: create KVM mock properties

On Fri, Jun 23, 2023 at 11:28:03AM -0300, Daniel Henrique Barboza wrote: ... > > I think we should actually fail with an error when the user tries to > > enable an extension KVM doesn't support. Otherwise a user may be > > confused as to why their Zawrs=on didn't provide them a machine with > > Zaw

Re: [PATCH v3 12/19] target/riscv: add KVM specific MISA properties

On Fri, Jun 23, 2023 at 11:14:45AM -0300, Daniel Henrique Barboza wrote: > > > On 6/23/23 06:38, Andrew Jones wrote: > > On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote: > > ... > > > +#define KVM_MISA_CFG(_bit, _reg_id) \ > > > +

Re: [PATCH v3 16/19] target/riscv/cpu.c: create KVM mock properties

On Thu, Jun 22, 2023 at 10:56:57AM -0300, Daniel Henrique Barboza wrote: > KVM-specific properties are being created inside target/riscv/kvm.c. But > at this moment we're gathering all the remaining properties from TCG and > adding them as is when running KVM. This creates a situation where > non-K

Re: [PATCH v3 15/19] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()

a_arr[i])) { > +if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { > new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > g_free(old); > old = new; > -- > 2.41.0 > Nice! Reviewed-by: Andrew Jones

Re: [PATCH v3 12/19] target/riscv: add KVM specific MISA properties

On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote: ... > +#define KVM_MISA_CFG(_bit, _reg_id) \ > +{.offset = _bit, .kvm_reg_id = _reg_id} > + > +/* KVM ISA extensions */ > +static KVMCPUConfig kvm_misa_ext_cfgs[] = { > +KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), > +K

Re: [PATCH v3 11/19] target/riscv/cpu: add misa_ext_info_arr[]

> extensions. For now doing just with MISA extensions is enough. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 60 ++ > target/riscv/cpu.h | 11 - > 2 files changed, 44

Re: [PATCH v2 15/18] target/riscv: make riscv_isa_string_ext() KVM compatible

On Wed, Jun 21, 2023 at 10:20:37AM +0200, Andrew Jones wrote: > On Tue, Jun 20, 2023 at 07:05:18PM -0300, Daniel Henrique Barboza wrote: > > > > > > On 6/19/23 06:54, Andrew Jones wrote: > > > On Tue, Jun 13, 2023 at 05:58:54PM -0300, Daniel Henrique Barboza wrote:

Re: [PATCH v2 15/18] target/riscv: make riscv_isa_string_ext() KVM compatible

On Tue, Jun 20, 2023 at 07:05:18PM -0300, Daniel Henrique Barboza wrote: > > > On 6/19/23 06:54, Andrew Jones wrote: > > On Tue, Jun 13, 2023 at 05:58:54PM -0300, Daniel Henrique Barboza wrote: > > > The isa_edata_arr[] is used by riscv_isa_string_ext() to create the >

Re: [PATCH v2 18/18] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM

RE); > +} > +} > + > static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) > { > CPURISCVState *env = &cpu->env; > @@ -678,6 +740,14 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, > KVMScratchCPU *kvmcpu) > > kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); > } > + > +if (cpu->cfg.ext_icbom) { > +kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); > +} > + > +if (cpu->cfg.ext_icboz) { > +kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); > +} > } > > void kvm_riscv_init_user_properties(Object *cpu_obj) > -- > 2.40.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 17/18] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper

cpu, > KVMCPUConfig *multi_ext) > { > -int cpu_cfg_offset = multi_ext->offset; > -bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset; > +bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); > > return *ext_enabled; > } > -- > 2.40.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 15/18] target/riscv: make riscv_isa_string_ext() KVM compatible

On Tue, Jun 13, 2023 at 05:58:54PM -0300, Daniel Henrique Barboza wrote: > The isa_edata_arr[] is used by riscv_isa_string_ext() to create the > riscv,isa DT attribute. isa_edata_arr[] is kept in sync with the TCG > property vector riscv_cpu_extensions[], i.e. all TCG properties from > this vector

Re: [PATCH v2 14/18] target/riscv/kvm.c: add multi-letter extension KVM properties

able to read ISA_EXT KVM register %s, " > + "error %d", multi_ext_cfg->name, ret); > +kvm_riscv_destroy_scratch_vcpu(kvmcpu); > +exit(EXIT_FAILURE); > +} > +} else { > +multi_ext_cfg->supported = true; > +} > + > +kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); > +} > +} > + > void kvm_riscv_init_user_properties(Object *cpu_obj) > { > RISCVCPU *cpu = RISCV_CPU(cpu_obj); > @@ -540,6 +663,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) > kvm_riscv_add_cpu_user_properties(cpu_obj); > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > +kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); > > kvm_riscv_destroy_scratch_vcpu(&kvmcpu); > } > -- > 2.40.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 13/18] target/riscv/kvm.c: update KVM MISA bits

> + misa_cfg->name, ret); > +exit(EXIT_FAILURE); > +} > +env->misa_ext &= ~misa_bit; > +} > +} > + > static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > { > int i; > @@ -630,8 +665,13 @@ int kvm_arch_init_vcpu(CPUState *cs) > > if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { > ret = kvm_vcpu_set_machine_ids(cpu, cs); > +if (ret != 0) { > +return ret; > +} > } > > +kvm_riscv_update_cpu_misa_ext(cpu, cs); > + > return ret; > } > > -- > 2.40.1 > Besides the commit message clarification and the code comment typo, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v2 12/18] target/riscv: add KVM specific MISA properties

->name); > +} > + > +static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > +{ > +int i; > + > +for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { > +KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; > + > +object_property_add(cpu_obj, misa_cfg->name, "bool", > +NULL, > +kvm_cpu_set_misa_ext_cfg, > +NULL, misa_cfg); > +object_property_set_description(cpu_obj, misa_cfg->name, > +misa_cfg->description); > +} > +} > + > static int kvm_riscv_get_regs_core(CPUState *cs) > { > int ret = 0; > @@ -427,6 +502,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) > return; > } > > +kvm_riscv_add_cpu_user_properties(cpu_obj); > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > > -- > 2.40.1 > Reviewed-by: Andrew Jones

Re: [PATCH v2 11/18] target/riscv/cpu: add misa_ext_infos[]

tter > extensions. For now doing just with MISA extensions is enough. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 44 ++-- > target/riscv/cpu.h | 22 +- >

Re: [PATCH v4 1/4] target/riscv: Add Smrnmi cpu extension.

Please add a commit message to all patches of the series. Another comment below. On Thu, Jun 08, 2023 at 12:23:11AM -0700, Tommy Wu wrote: > Signed-off-by: Frank Chang > Signed-off-by: Tommy Wu > --- > hw/riscv/riscv_hart.c | 21 + > include/hw/riscv/riscv_hart.h

Re: [PATCH v4 0/4] target/riscv: Add Smrnmi support.

On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote: > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > =

Re: [PATCH 16/16] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM

On Wed, Jun 07, 2023 at 05:37:16PM -0300, Daniel Henrique Barboza wrote: > > > On 6/7/23 10:01, Andrew Jones wrote: > > On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote: > > > If we don't set a proper cbom_blocksize|cboz_blocksize in the FD

Re: [PATCH 13/16] target/riscv/kvm.c: add multi-letter extension KVM properties

On Wed, Jun 07, 2023 at 04:59:02PM -0300, Daniel Henrique Barboza wrote: > > > On 6/7/23 08:48, Andrew Jones wrote: > > On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote: > > > Let's add KVM user properties for the multi-letter extensions that

Re: [PATCH 16/16] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM

On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote: > If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the > Linux Kernel will fail to detect the availability of the CBOM/CBOZ > extensions, regardless of the contents of the 'riscv,isa' DT prop. > > The FDT is

Re: [PATCH 15/16] target/riscv: update multi-letter extension KVM properties

, ret); > +exit(EXIT_FAILURE); > +} > +} > +} > + > static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > { > int i; > @@ -829,6 +855,7 @@ int kvm_arch_init_vcpu(CPUState *cs) > } > > kvm_riscv_update_cpu_misa_ext(cpu, cs); > +kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); > > return ret; > } > -- > 2.40.1 > > Reviewed-by: Andrew Jones

Re: [PATCH 14/16] target/riscv: adapt 'riscv_isa_string' for KVM

On Tue, May 30, 2023 at 04:46:21PM -0300, Daniel Henrique Barboza wrote: > KVM is not using the same attributes as TCG, i.e. it doesn't use > isa_edata_arr[]. Add a new kvm_riscv_isa_string_ext() helper that does > basically the same thing, but using KVM internals instead. > > The decision to add

Re: [PATCH 12/16] target/riscv/kvm.c: update KVM MISA bits

On Tue, May 30, 2023 at 04:46:19PM -0300, Daniel Henrique Barboza wrote: > Our design philosophy with KVM properties can be resumed in two main > decisions based on KVM interface availability and what the user wants to > do: > > - if the user disables an extension that the host KVM module doesn't

Re: [PATCH 13/16] target/riscv/kvm.c: add multi-letter extension KVM properties

On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote: > Let's add KVM user properties for the multi-letter extensions that KVM > currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc, > svinval and svpbmt. > > As with the recently added MISA properties we're also goi

Re: [PATCH 11/16] target/riscv: add KVM specific MISA properties

On Tue, May 30, 2023 at 04:46:18PM -0300, Daniel Henrique Barboza wrote: > Using all TCG user properties in KVM is tricky. First because KVM > supports only a small subset of what TCG provides, so most of the > cpu->cfg flags do nothing for KVM. > > Second, and more important, we don't have a way

Re: [PATCH 10/16] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU

34 +++--- > 1 file changed, 23 insertions(+), 11 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH 08/16] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs

rch_init_vcpu(CPUState *cs) > } > env->misa_ext = isa; > > +if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { > +ret = kvm_vcpu_set_machine_ids(cpu, cs); > +} > + > return ret; > } > > -- > 2.40.1 > > Reviewed-by: Andrew Jones

Re: [PATCH 07/16] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()

KVM_REG_RISCV_CONFIG_REG(mimpid)); > +reg.addr = (uint64_t)&cpu->cfg.mimpid; > +ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > +if (ret != 0) { > + error_report("Unable to retrieve mimpid from host, error %d", ret); > +} > } > > void kvm_riscv_init_user_properties(Object *cpu_obj) > -- > 2.40.1 > > Reviewed-by: Andrew Jones

Re: [PATCH 06/16] target/riscv: use KVM scratch CPUs to init KVM properties

to > init other KVM specific properties in the next patches as well. > > [1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu() > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 4 ++ > target/riscv/kvm.c | 85 ++++ > target/riscv/kvm_riscv.h | 1 + > 3 files changed, 90 insertions(+) > Reviewed-by: Andrew Jones

Re: [PATCH 05/16] target/riscv/cpu.c: restrict 'marchid' value

" > + "and the remaining bits zero", mxlen); > +return; > +} > + > +cpu->cfg.marchid = value; > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -1893,6 +1928,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void > *data) >cpu_set_mimpid, >NULL, NULL); > > +object_class_property_add(c, "marchid", "uint64", NULL, > + cpu_set_marchid, > + NULL, NULL); > + get? > device_class_set_props(dc, riscv_cpu_properties); > } > > -- > 2.40.1 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 04/16] target/riscv/cpu.c: restrict 'mimpid' value

cpu_set_mvendorid, > NULL, NULL); > > +object_class_property_add(c, "mimpid", "uint64", NULL, > + cpu_set_mimpid, > + NULL, NULL); > + Same, shouldn't we also define 'get' comment as the last patch. > device_class_set_props(dc, riscv_cpu_properties); > } > > -- > 2.40.1 > > Reviewed-by: Andrew Jones

Re: [PATCH 03/16] target/riscv/cpu.c: restrict 'mvendorid' value

t; + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -1841,6 +1866,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void > *data) > cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; > cc->tcg_ops = &riscv_tcg_ops; > > +object_class_property_add(c, "mvendorid", "uint32", NULL, > + cpu_set_mvendorid, > + NULL, NULL); > + Shouldn't we provide a get function as well? > device_class_set_props(dc, riscv_cpu_properties); > } > > -- > 2.40.1 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 02/16] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set

e_max, > is_32_bit)); > +qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); > +g_free(sv_name); > +} > > name = riscv_isa_string(cpu_ptr); > qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); > -- > 2.40.1 > > Adding a sentence, like what I wrote above, to the commit message in order to provide better justification might be nice, but either way Reviewed-by: Andrew Jones Thanks, drew

Re: [RFC v2] linux-user/riscv: Add syscall riscv_hwprobe

On Fri, Jun 02, 2023 at 07:58:30PM -0700, Richard Henderson wrote: > On 6/2/23 07:02, Andrew Jones wrote: > > > +struct riscv_hwprobe { > > > +int64_t key; > > > +uint64_t value; > > > +}; > > > > The above is all uapi so Linux's ar

Re: [RFC v2] linux-user/riscv: Add syscall riscv_hwprobe

On Fri, Jun 02, 2023 at 04:39:20PM +0200, Robbin Ehn wrote: > On Fri, 2023-06-02 at 16:02 +0200, Andrew Jones wrote: > > On Fri, Jun 02, 2023 at 11:41:11AM +0200, Robbin Ehn wrote: ... > > > +#if defined(TARGET_RISCV) > > > +case TARGET_NR_riscv_hwprobe: > >

Re: [PATCH 01/16] target/riscv: skip features setup for KVM CPUs

cpu_exec_realizefn(cs, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return; > +} > + > +if (!riscv_running_KVM()) { > +riscv_cpu_realize_features(dev, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return; > +} > +} > > riscv_cpu_finalize_features(cpu, &local_err); > if (local_err != NULL) { > -- > 2.40.1 > > Otherwise, Reviewed-by: Andrew Jones

Re: [RFC v2] linux-user/riscv: Add syscall riscv_hwprobe

On Fri, Jun 02, 2023 at 11:41:11AM +0200, Robbin Ehn wrote: > This patch adds the new syscall for the > "RISC-V Hardware Probing Interface" > (https://docs.kernel.org/riscv/hwprobe.html). > > Signed-off-by: Robbin Ehn > --- > v1->v2: Moved to syscall.c > --- > linux-user/riscv/syscall32_nr.h |

Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements

On Fri, May 26, 2023 at 04:42:57AM -0400, Andrea Bolognani wrote: > On Fri, May 26, 2023 at 10:34:36AM +0200, Andrew Jones wrote: > > On Fri, May 26, 2023 at 03:49:11AM -0400, Andrea Bolognani wrote: > > > So, are edk2 users the only ones who would (temporarily) need to > &

Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements

On Fri, May 26, 2023 at 03:49:11AM -0400, Andrea Bolognani wrote: > On Fri, May 26, 2023 at 08:39:07AM +0200, Andrew Jones wrote: > > On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote: > > > With these patches applied, libvirt built from the master branch, > >

Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements

On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote: > On Thu, May 25, 2023 at 10:18:00PM +0530, Sunil V L wrote: > > This series improves the pflash usage in RISC-V virt machine with solutions > > to > > below issues. > > > > 1) Currently the first pflash is reserved for ROM/M-mode f

Re: [PTACH v2 2/6] target/riscv: support the AIA device emulateion with KVM enabled

sed 's/emulateion/emulation' <<<$SUBJECT and for the whole series sed 's/PTACH/PATCH/' <<<$SUBJECT Thanks, drew On Fri, May 05, 2023 at 11:39:37AM +, Yong-Xuan Wang wrote: > Remove M mode AIA devices when using KVM acceleration > > Signed-off-by: Yong-Xuan Wang > Reviewed-by: Jim Shu >

Re: [kvm-unit-tests PATCH v10 0/7] MTTCG sanity tests for ARM

On Tue, Apr 11, 2023 at 08:43:49AM +0100, Alex Bennée wrote: > > Andrew Jones writes: ... > > Someday mkstandalone could maybe learn how to build > > a directory hierarchy using the group names, e.g. > > > > tests/mttcg/tlb/all_other > > So nodefault is

Re: [kvm-unit-tests PATCH v10 4/7] arm/tlbflush-code: TLB flush during code execution

On Tue, Apr 11, 2023 at 09:26:56AM +0100, Alex Bennée wrote: > > Andrew Jones writes: > > > On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote: > >> This adds a fairly brain dead torture test for TLB flushes intended > >> for stressing the MTTCG QE

Re: [kvm-unit-tests PATCH v10 0/7] MTTCG sanity tests for ARM

On Tue, Mar 07, 2023 at 11:28:38AM +, Alex Bennée wrote: > I last had a go at getting these up-streamed at the end of 2021 so > its probably worth having another go. From the last iteration a > number of the groundwork patches did get merged: > > Subject: [kvm-unit-tests PATCH v9 0/9] MTTCG

Re: [kvm-unit-tests PATCH v10 4/7] arm/tlbflush-code: TLB flush during code execution

On Tue, Mar 21, 2023 at 04:02:21PM +0100, Andrew Jones wrote: ... > > + > > +# TLB Torture Tests > > +[tlbflush-code::all_other] > > It's better to use '-', '_', '.', or ',' than '::' because otherwise the > standa

Re: [kvm-unit-tests PATCH v10 5/7] arm/locking-tests: add comprehensive locking test

On Tue, Mar 07, 2023 at 11:28:43AM +, Alex Bennée wrote: > This test has been written mainly to stress multi-threaded TCG behaviour > but will demonstrate failure by default on real hardware. The test takes > the following parameters: > > - "lock" use GCC's locking semantics > - "atomic" u

Re: [kvm-unit-tests PATCH v10 4/7] arm/tlbflush-code: TLB flush during code execution

On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote: > This adds a fairly brain dead torture test for TLB flushes intended > for stressing the MTTCG QEMU build. It takes the usual -smp option for > multiple CPUs. > > By default it CPU0 will do a TLBIALL flush after each cycle. You can > pa

Re: [kvm-unit-tests PATCH v10 2/7] add .gitpublish metadata

-nogit > --nogit-fallback 2>/dev/null Should we also set the prefix for these? prefix = kvm-unit-tests PATCH And maybe even, 'signoff = true'? Otherwise, Acked-by: Andrew Jones Thanks, drew

Re: [kvm-unit-tests PATCH v10 1/7] Makefile: add GNU global tags support

.4d5f460f 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -12,6 +12,9 @@ tags > patches > .stgit-* > cscope.* > +GPATH > +GRTAGS > +GTAGS > *.swp > /lib/asm > /lib/config.h > -- > 2.39.2 > Acked-by: Andrew Jones

Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg

On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote: > henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/csr.c | 13 + > 1 file changed, 9 insertions(+), 4 deletions(-) > > di

Re: [PATCH v2 0/4] NUMA: Apply socket-NUMA-node boundary for aarch64 and RiscV machines

On Fri, Feb 24, 2023 at 09:16:39PM +1100, Gavin Shan wrote: > On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote: > > On 2/24/23 04:09, Gavin Shan wrote: > > > On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote: > > > > On 2/23/23 05:13, Gavin Shan wrote: > > > > > For arm64 and RiscV architecture,

Re: [PATCH V4 8/8] MAINTAINERS: Add entry for RISC-V ACPI

n Meng > Acked-by: Alistair Francis > Reviewed-by: Andrew Jones > --- > MAINTAINERS | 18 -- > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9adb628627..7a47c2c724 100644 > --- a/MAINTAINERS

Re: [PATCH v2 0/4] NUMA: Apply socket-NUMA-node boundary for aarch64 and RiscV machines

On Thu, Feb 23, 2023 at 04:13:57PM +0800, Gavin Shan wrote: > For arm64 and RiscV architecture, the driver (/base/arch_topology.c) is > used to populate the CPU topology in the Linux guest. It's required that > the CPUs in one socket can't span mutiple NUMA nodes. Otherwise, the Linux > scheduling

Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental

CVState *env, int > csrno, > static RISCVException write_misa(CPURISCVState *env, int csrno, > target_ulong val) > { > -if (!riscv_feature(env, RISCV_FEATURE_MISA)) { > +if (!riscv_cpu_cfg(env)->misa_w) { > /* drop write to misa */ > return RISCV_EXCP_NONE; > } > -- > 2.39.2 > > Reviewed-by: Andrew Jones

Re: [PATCH v6 1/9] target/riscv: turn write_misa() into an official no-op

On Tue, Feb 21, 2023 at 03:22:45PM -0300, Daniel Henrique Barboza wrote: > > > On 2/21/23 14:06, Andrew Jones wrote: > > On Tue, Feb 21, 2023 at 12:49:11PM -0300, Daniel Henrique Barboza wrote: > > > Hey, > > > > > > On 2/16/23 22:42, LIU Zhiwei wrote:

Re: [PATCH v6 1/9] target/riscv: turn write_misa() into an official no-op

t; > Thanks, > > > Daniel > > > > > > > Zhiwei > > > > > Given that allowing the dormant code to write MISA can cause tricky bugs > > > to solve later on, and we don't have a particularly interesting case of > > > wri

Re: [PATCH V3 5/8] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT

; build_fadt_rev6(tables_blob, tables->linker, s, dsdt); > > +acpi_add_table(table_offsets, tables_blob); > +build_madt(tables_blob, tables->linker, s); > + > /* XSDT is pointed to by RSDP */ > xsdt = tables_blob->len; > build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, > -- > 2.34.1 > Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH V3 4/8] hw/riscv/virt: Enable basic ACPI infrastructure

build_state, tables.table_data, > + ACPI_BUILD_TABLE_FILE); > +assert(build_state->table_mr != NULL); > + > +build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, > + build_state, > + tables.linker->cmd_blob, > + ACPI_BUILD_LOADER_FILE); > + > +build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, > + build_state, tables.rsdp, > + ACPI_BUILD_RSDP_FILE); > + > +qemu_register_reset(virt_acpi_build_reset, build_state); > +virt_acpi_build_reset(build_state); > +vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); > + > +/* > + * Clean up tables but don't free the memory: we track it > + * in build_state. > + */ > +acpi_build_tables_cleanup(&tables, false); > +} > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index 379501edcc..e5c474b26e 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -126,4 +126,5 @@ enum { > 1 + FDT_APLIC_INT_CELLS) > > bool virt_is_acpi_enabled(RISCVVirtState *s); > +void virt_acpi_setup(RISCVVirtState *vms); > #endif > -- > 2.34.1 > Otherwise, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v4 02/10] target/riscv: remove RISCV_FEATURE_MISA

FEATURE_DEBUG > }; > > -- > 2.39.1 > Probably could squash into the previous patch, but anyway Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v4 01/10] target/riscv: turn write_misa() into an official no-op

- > target/riscv/csr.c | 55 -- > 1 file changed, 55 deletions(-) > Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v3 02/10] target/riscv: always allow write_misa() to write MISA

On Thu, Feb 16, 2023 at 05:33:55PM +0800, Bin Meng wrote: > On Thu, Feb 16, 2023 at 5:29 PM Andrew Jones wrote: > > > > On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote: > > > At this moment, and apparently since ever, we have no way of enabling

Re: [PATCH v3 02/10] target/riscv: always allow write_misa() to write MISA

On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote: > At this moment, and apparently since ever, we have no way of enabling > RISCV_FEATURE_MISA. This means that all the code from write_misa(), all > the nuts and bolts that handles how to properly write this CSR, has > always b

Re: [PATCH v2 00/11] enable write_misa() and RISCV_FEATURE_* cleanups

target/riscv/cpu_helper.c | 6 +++--- > target/riscv/csr.c| 15 ++- > target/riscv/machine.c| 11 --- > target/riscv/monitor.c| 2 +- > target/riscv/op_helper.c | 2 +- > target/riscv/pmp.c| 8 ++++ > 9 files changed, 34 insertions(+), 66 deletions(-) > > -- > 2.39.1 > > For the series Reviewed-by: Andrew Jones

Re: [PATCH V2 10/10] MAINTAINERS: Add entry for RISC-V ACPI

> +RISC-V ACPI Subsystem > +M: Sunil V L > +L: qemu-ri...@nongnu.org > +S: Maintained > +F: hw/riscv/virt-acpi-build.c > + > STM32F100 > M: Alexandre Iooss > L: qemu-...@nongnu.org > -- > 2.34.1 > Please move the ARM ACPI entry down under the main ACPI entry and then add the RISC-V one there too. Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH V2 08/10] hw/riscv/Kconfig: virt: Enable ACPI config option

gt; bool > -- > 2.34.1 > This could probably squashed together with the previous patch. Reviewed-by: Andrew Jones

Re: [PATCH V2 09/10] hw/riscv/virt.c: Initialize the ACPI tables

led()) { > riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); > } > + > +if (virt_is_acpi_enabled(s)) { > +virt_acpi_setup(s); > +} > } > > static void virt_machine_init(MachineState *machine) > -- > 2.34.1 > Reviewed-by: Andrew Jones

Re: [PATCH V2 07/10] hw/riscv: meson.build: Build virt-acpi-build.c

;microchip_pfsoc.c')) > +riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) > > hw_arch += {'riscv': riscv_ss} > -- > 2.34.1 > Reviewed-by: Andrew Jones

Re: [PATCH V2 06/10] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table

*/ > +build_append_int_noprefix(table_data, 1, 2); /* number of > offsets */ s/number/Number/ > +build_append_int_noprefix(table_data, acpi_proc_id, 4); /* UID */ ACPI Processor UID > +build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets */ > +acpi_proc_id++; > +} > +} > + > +acpi_table_end(linker, &table); > +} > + > /* FADT */ > static void > build_fadt_rev6(GArray *table_data, BIOSLinker *linker, > -- > 2.34.1 > Other than getting the comments to match the spec fields, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH V2 05/10] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT

On Mon, Feb 13, 2023 at 08:10:33PM +0530, Sunil V L wrote: > Add Multiple APIC Description Table (MADT) with the > INTC structure for each cpu. > > Signed-off-by: Sunil V L > Acked-by: Alistair Francis > --- > hw/riscv/virt-acpi-build.c | 37 + > 1 file chang

Re: [PATCH V2 04/10] hw/riscv/virt: virt-acpi-build.c: Add basic ACPI tables

On Mon, Feb 13, 2023 at 08:10:32PM +0530, Sunil V L wrote: > Add few basic ACPI tables and DSDT with few devices in a > new file virt-acpi-build.c. > > These are mostly leveraged from arm64. > > Signed-off-by: Sunil V L > --- > hw/riscv/virt-acpi-build.c | 285 ++

Re: [PATCH V2 03/10] hw/riscv/virt: Add memmap pointer to RiscVVirtState

irt.h > @@ -59,6 +59,7 @@ struct RISCVVirtState { > char *oem_id; > char *oem_table_id; > OnOffAuto acpi; > +const MemMapEntry *memmap; > }; > > enum { > -- > 2.34.1 > Reviewed-by: Andrew Jones

Re: [PATCH V2 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

aa32 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -58,6 +58,7 @@ struct RISCVVirtState { > int aia_guests; > char *oem_id; > char *oem_table_id; > +OnOffAuto acpi; > }; > > enum { > @@ -123,4 +124,5 @@ enum { > #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ > 1 + FDT_APLIC_INT_CELLS) > > +bool virt_is_acpi_enabled(RISCVVirtState *s); > #endif > -- > 2.34.1 > Otherwise, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH V2 01/10] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields

ample. > /* create device tree */ > create_fdt(s, memmap); > > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index b3d26135c0..6c7885bf89 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -56,6 +56,8 @@ struct RISCVVirtState

Re: [PATCH V2 04/10] hw/riscv/virt: virt-acpi-build.c: Add basic ACPI tables

On Tue, Feb 14, 2023 at 09:13:28AM +0530, Sunil V L wrote: > On Mon, Feb 13, 2023 at 03:48:04PM -0300, Daniel Henrique Barboza wrote: > > Sunil, > > > > This patch is a bit confusing to me. You're using functions that doesn't > > exist > > in the code base yet (build_madt and build_rhct) because

Re: [PATCH 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

On Tue, Feb 07, 2023 at 06:38:15AM -0800, Andrea Bolognani wrote: > On Tue, Feb 07, 2023 at 03:02:19PM +0100, Thomas Huth wrote: > > On 07/02/2023 14.56, Andrea Bolognani wrote: > > > It looks like i440fx and q35 both have an 'acpi' machine property. Is > > > -no-acpi just sugar for acpi=off? > > >

Re: [PATCH 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote: > On 6/2/23 11:54, Andrea Bolognani wrote: > > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote: > > > +object_class_property_add(oc, "acpi", "OnOffAuto", > > > + virt_get_acpi, virt_se

Re: [PATCH 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

On Tue, Feb 07, 2023 at 09:50:29AM +0100, Philippe Mathieu-Daudé wrote: > On 6/2/23 13:56, Gerd Hoffmann wrote: > > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote: > > > On 6/2/23 11:54, Andrea Bolognani wrote: > > > > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrot

Re: [PATCH 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

On Tue, Feb 07, 2023 at 11:57:29AM +0800, Bin Meng wrote: > On Mon, Feb 6, 2023 at 8:36 PM Andrew Jones wrote: > > > > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote: > > > On 6/2/23 11:54, Andrea Bolognani wrote: > > > > On Thu, Feb 02,

Re: [PATCH 02/10] hw/riscv/virt: Add a switch to enable/disable ACPI

On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote: > On 6/2/23 11:54, Andrea Bolognani wrote: > > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote: > > > +object_class_property_add(oc, "acpi", "OnOffAuto", > > > + virt_get_acpi, virt_se

Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode

ig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b157806a5..3c02055825 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = > MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const bool valid_vm_1_10_32[16] = { > +const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV32] = true > }; > > -static const bool valid_vm_1_10_64[16] = { > +const bool valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV39] = true, > [VM_1_10_SV48] = true, > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, > int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > -if (riscv_cpu_mxl(env) == MXL_RV32) { > -return valid_vm_1_10_32[vm & 0xf]; > -} else { > -return valid_vm_1_10_64[vm & 0xf]; > -} > +RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + > +return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > } > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > -- > 2.37.2 > Other than the minor nit Reviewed-by: Andrew Jones Thanks, drew

<    1   2   3   4   5   6   7   8   9   10   >