[PATCH v7 08/12] target/riscv: Add sscofpmf extension support

. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 11 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 156 -- target/riscv/pmu.c | 347 +++- target

[PATCH v7 09/12] target/riscv: Simplify counter predicate function

Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 - 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 519d6377fd9f..20bdae7fe354 100644 --- a/target/riscv

[PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[PATCH v7 10/12] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra

[PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu

From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM ar

[PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret

[PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable

by the cpu. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 94 ++ 3 files changed, 63 insertions(+), 35

[PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR

From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h

[PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents

From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off

[PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function

From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode

From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair

[PATCH v7 00/12] Improve PMU support

[4] https://github.com/atishp04/qemu/tree/riscv_pmu_v7 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mode target/riscv: pmu: Rename the counters extension to pmu target/riscv: pmu: Make number of counters configurable target/ris

Re: [PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents

On Tue, Mar 15, 2022 at 12:41 AM Frank Chang wrote: > > Atish Patra 於 2022年3月4日 週五 上午8:06寫道： >> >> From: Atish Patra >> >> With SBI PMU extension, user can use any of the available hpmcounters to >> track any perf events based on the value written

Re: [PATCH v6 08/12] target/riscv: Add sscofpmf extension support

On Thu, Mar 17, 2022 at 12:38 AM Frank Chang wrote: > > On Fri, Mar 4, 2022 at 8:06 AM Atish Patra wrote: >> >> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, >> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) >> extension allo

Re: [PATCH v6 10/12] target/riscv: Add few cache related PMU events

On Tue, Mar 15, 2022 at 2:26 AM Frank Chang wrote: > > On Fri, Mar 4, 2022 at 8:11 AM Atish Patra wrote: >> >> From: Atish Patra >> >> Qemu can monitor the following cache related PMU events through >> tlb_fill functions. >> >> 1. DTLB load/sto

Re: [PATCH] target/riscv: Exit current TB after an sfence.vma

On Tue, Mar 29, 2022 at 11:15 PM Idan Horowitz wrote: > > On Wed, 30 Mar 2022 at 02:16, Atish Patra wrote: > > > > This is in for-next on Alistair's tree and fails to boot the kernel > > with the following error (found -d in_asm mode). > > Revert

Re: [PATCH] target/riscv: Exit current TB after an sfence.vma

On Wed, Mar 16, 2022 at 10:23 AM wrote: > > Here is a test case for this patch. I used to submit this bug on > https://bugs.launchpad.net/qemu/+bug/1906516 > > sfence.vma will flush the tlb, so after this instruction, the translation > block should be end. > The following code will only work in

[PATCH v7] target/riscv: Add isa extenstion strings to the device tree

Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Changes from v6->v7: 1. Fixed indentation and typo. 2. Added Reviewed-by tags. Changes from v5->v6: 1. Improved commit message. 2. Fixed a typo for Zfh. Changes from v4->v5: 1. Fixed the order of Zxx extensions. 2. Added

[PATCH v6] target/riscv: Add isa extenstion strings to the device tree

ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Ch

[PATCH v5] target/riscv: Add isa extenstion strings to the device tree

ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Changes f

[PATCH v4] target/riscv: Add isa extenstion strings to the device tree

ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Ch

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

rote: >>>> >>>> >>>> >>>> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote: >>>>> >>>>> Hi, >>>>> >>>>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra: >>>>&g

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

On Tue, Mar 8, 2022 at 2:53 PM Atish Patra wrote: > > On Sat, Mar 5, 2022 at 10:43 PM Frank Chang wrote: > > > > On Sun, Mar 6, 2022 at 2:12 PM Atish Kumar Patra > > wrote: > >> > >> > >> > >> On Sat, Mar 5, 2022 at 9:36 PM Frank Ch

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

On Sat, Mar 5, 2022 at 10:47 PM Frank Chang wrote: > > Typo in patch title: > s/extenstion/extension/g > Thanks for catching it. Will fix it. > Regards, > Frank Chang > > On Sat, Feb 26, 2022 at 3:45 PM Frank Chang wrote: >> >> >> >> Atish Pa

Re: [RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp

On Tue, Mar 8, 2022 at 1:33 PM Alistair Francis wrote: > > On Fri, Mar 4, 2022 at 2:08 PM Anup Patel wrote: > > > > On Fri, Mar 4, 2022 at 8:50 AM Atish Patra wrote: > > > > > > Currently, the aclint and ibex timer devices uses the "timer"

[RFC PATCH 3/3] target/riscv: Add vstimecmp support

vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Signed-off-by: Atish Patra --- target/riscv/cpu.h

[RFC PATCH 1/3] target/riscv: Rename timer & timecmp to mtimer and mtimecmp

iornment variables to indicate its true purpose. Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 20 ++-- hw/timer/ibex_timer.c | 14 +++--- target/riscv/cpu.h | 4 ++-- target/riscv/machine.c | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff -

[RFC PATCH 2/3] target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 7 +++ target/riscv/cpu.h | 5 ++ target/riscv

[RFC PATCH 0/3] Implement Sstc extension

m/ [3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg870659.html [4] https://github.com/atishp04/opensbi/tree/sstc_v1 [5] https://github.com/atishp04/linux/tree/sstc_v2 Atish Patra (3): target/riscv: Rename timer & timecmp to mtimer and mtimecmp target/riscv: Add stimecmp support target/risc

[PATCH v6 11/12] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[PATCH v6 07/12] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret

[PATCH v6 12/12] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30 deletions(-) diff --git a/target/riscv/csr.c b/target

[PATCH v6 10/12] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra

[PATCH v6 06/12] target/riscv: Add support for hpmcounters/hpmevents

From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off

[PATCH v6 09/12] target/riscv: Simplify counter predicate function

Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 - 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index cfcc1a0882d9..771e16d99f39 100644 --- a/target/riscv

[PATCH v6 08/12] target/riscv: Add sscofpmf extension support

. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 9 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 157 -- target/riscv/pmu.c | 346 +++- target

[PATCH v6 01/12] target/riscv: Fix PMU CSR predicate function

From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v6 05/12] target/riscv: Implement mcountinhibit CSR

From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h

[PATCH v6 03/12] target/riscv: pmu: Rename the counters extension to pmu

From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM ar

[PATCH v6 04/12] target/riscv: pmu: Make number of counters configurable

by the cpu. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35

[PATCH v6 02/12] target/riscv: Implement PMU CSR predicate function for S-mode

From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair

[PATCH v6 00/12] Improve PMU support

cv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v6 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v5 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv:

Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree

On Fri, Feb 25, 2022 at 11:46 PM Frank Chang wrote: > > > > Atish Patra 於 2022年2月23日 週三 上午6:39寫道： >> >> The Linux kernel parses the ISA extensions from "riscv,isa" DT >> property. It used to parse only the single letter base extensions >> until

[PATCH v5 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra

Re: [PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support

On Tue, Feb 22, 2022 at 8:34 PM Alistair Francis wrote: > > On Wed, Feb 23, 2022 at 8:09 AM Atish Patra wrote: > > > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > e

[PATCH v5 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 5

[PATCH v5 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cf748102efa2..7f67e920c650 100644

[PATCH v5 6/6] target/riscv: Enable privileged spec version 1.12

Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ffb7..c3fd018ecb6e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7

[PATCH v5 0/6] Privilege version update

redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in the CSR ops. targe

[PATCH v5 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5

[PATCH v5 3/6] target/riscv: Introduce privilege version field in the CSR ops.

, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv

[PATCH v3] target/riscv: Add isa extenstion strings to the device tree

ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Changes from v2->v3: 1. Used g_strconcat to replace snpr

Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree

On Tue, Feb 15, 2022 at 7:19 PM Anup Patel wrote: > > On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote: > > > > The Linux kernel parses the ISA extensions from "riscv,isa" DT > > property. It used to parse only the single letter base extensions > > un

[PATCH v4 6/6] target/riscv: Enable privileged spec version 1.12

Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2668f9c358b2..1c72dfffdc61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7

[PATCH v4 3/6] target/riscv: Introduce privilege version field in the CSR ops.

, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv

[PATCH v4 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5

[PATCH v4 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644

[PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39

[PATCH v4 0/6] Privilege version update

ability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in the CSR ops. target/r

[PATCH v4 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra

Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops.

On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis wrote: > > On Sun, Feb 6, 2022 at 7:19 PM Atish Patra wrote: > > > > To allow/disallow the CSR access based on the privilege spec, a new field > > in the csr_ops is introduced. It also adds the privileged specific

[PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents

From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target

[PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30 deletions(-) diff --git a/target/riscv/csr.c b/target

[PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[PATCH v5 09/12] target/riscv: Simplify counter predicate function

Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 - 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0071b13bc50f..54966a770672 100644 --- a/target/riscv/csr.c +++ b/target/riscv

[PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable

by the cpu. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35

[PATCH v5 10/12] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26

[PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function

From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret

[PATCH v5 08/12] target/riscv: Add sscofpmf extension support

. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 159 -- target/riscv/pmu.c | 346 +++- target

[PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR

From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h

[PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode

From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair

[PATCH v5 00/12] Improve PMU support

xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v6 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v5 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mode target/riscv: pmu: Rename the counters extension

[PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu

From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM ar

[PATCH v5 00/12] Improve PMU support

xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v6 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v5 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mode target/riscv: pmu: Rename the counters extension

[PATCH v2] target/riscv: Add isa extenstion strings to the device tree

ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Changes from v1->v2: 1. Improved the code redability

Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree

On Tue, Feb 15, 2022 at 8:20 AM Heiko Stübner wrote: > > Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra: > > Append the available ISA extensions to the "riscv,isa" string if it > > is enabled so that kernel can process it. > > > > Signed-

[PATCH] target/riscv: Add isa extenstion strings to the device tree

Append the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/r

Re: [PATCH v9 00/23] QEMU RISC-V AIA support

On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote: > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote: > > > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote: > > > > > > From: Anup Patel > > > > > > The advanced interrupt architecture (AIA) extends the per-HART local > > >

[PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed

[PATCH v3 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h

[PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions

[PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39

[PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops.

-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v3 0/6] Privilege version update

ned in *envcfg CSR Changes from v1->v2: 1. Unified both [m/h]envcfg & [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atis

[PATCH v2 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h

[PATCH v2 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions

[PATCH v2 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 +++ target/riscv/cpu_bits.h | 39

[PATCH v2 3/6] target/riscv: Introduce privilege version field in the CSR ops.

-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v2 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH v2 6/6] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed

[PATCH v2 0/6] Privilege version update

p; [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering

Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support

On Wed, Jan 26, 2022 at 12:37 AM Weiwei Li wrote: > > 在 2022/1/21 上午4:07, Atish Patra 写道: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. >

Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions

On Fri, Jan 21, 2022 at 1:55 AM Christoph Müllner wrote: > > On Tue, Jan 18, 2022 at 9:31 PM Atish Patra wrote: > > > > On Tue, Jan 18, 2022 at 8:48 AM Christoph Muellner > > wrote: > > > > > > The RISC-V base cache management operation ISA extensi

[RFC 1/5] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d630867650a..671f65100b1a 100644 --- a/target/riscv/cpu.h +++ b/target

[RFC 0/5] Privilege version update

, the privileged spec version should be updated in the csr table if required. I am open to other suggestions as well. [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Atish Patra (5): target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field

[RFC 5/5] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 10 ++ 2 files

[RFC 3/5] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h

[RFC 4/5] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 31

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