[PATCH v4 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis Signed-off-by: Atish

Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops.

On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis wrote: > > On Sun, Feb 6, 2022 at 7:19 PM Atish Patra wrote: > > > > To allow/disallow the CSR access based on the privilege spec, a new field > > in the csr_ops is introduced. It also adds the privileged specification >

[PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents

From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target

[PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs

The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Signed-off-by: Atish Patra --- target/riscv/csr.c | 90 ++ 1 file changed, 60 insertions(+), 30 deletions(-) diff --git a/target/riscv/csr.c b/target

[PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[PATCH v5 09/12] target/riscv: Simplify counter predicate function

Meng Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 - 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0071b13bc50f..54966a770672 100644 --- a/target/riscv/csr.c +++ b/target/

[PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable

by the cpu. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35

[PATCH v5 10/12] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26

[PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function

From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret

[PATCH v5 08/12] target/riscv: Add sscofpmf extension support

ed to handle the overflow. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 159 -- target/riscv/pmu.c | 346 +++

[PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR

From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h

[PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode

From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair

[PATCH v5 00/12] Improve PMU support

://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v6 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v5 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mod

[PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu

From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM

[PATCH v5 00/12] Improve PMU support

://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v6 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v5 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mod

[PATCH v2] target/riscv: Add isa extenstion strings to the device tree

string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Suggested-by: Heiko Stubner Signed-off-by: Atish Patra --- Changes from v1->v2: 1. Improved the code redability by

Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree

On Tue, Feb 15, 2022 at 8:20 AM Heiko Stübner wrote: > > Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra: > > Append the available ISA extensions to the "riscv,isa" string if it > > is enabled so that kernel can process it. > > > > Signed-

[PATCH] target/riscv: Add isa extenstion strings to the device tree

Append the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/r

Re: [PATCH v9 00/23] QEMU RISC-V AIA support

On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote: > > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis wrote: > > > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote: > > > > > > From: Anup Patel > > > > > > The advanced interrupt architecture (AIA) extends the per-HART local > > > interru

[PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed

[PATCH v3 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_b

[PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions

[PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39

[PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops.

-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v3 0/6] Privilege version update

in *envcfg CSR Changes from v1->v2: 1. Unified both [m/h]envcfg & [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atis

[PATCH v2 4/6] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_b

[PATCH v2 1/6] target/riscv: Define simpler privileged spec version numbering

Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions

[PATCH v2 5/6] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 +++ target/riscv/cpu_bits.h | 39

[PATCH v2 3/6] target/riscv: Introduce privilege version field in the CSR ops.

-off-by: Atish Patra --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++--- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b

[PATCH v2 2/6] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target

[PATCH v2 6/6] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 5 + 2 files changed

[PATCH v2 0/6] Privilege version update

p; [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering

Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support

On Wed, Jan 26, 2022 at 12:37 AM Weiwei Li wrote: > > 在 2022/1/21 上午4:07, Atish Patra 写道: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. > >

Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions

On Fri, Jan 21, 2022 at 1:55 AM Christoph Müllner wrote: > > On Tue, Jan 18, 2022 at 9:31 PM Atish Patra wrote: > > > > On Tue, Jan 18, 2022 at 8:48 AM Christoph Muellner > > wrote: > > > > > > The RISC-V base cache management operation ISA extensi

[RFC 1/5] target/riscv: Add the privileged spec version 1.12.0

Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d630867650a..671f65100b1a 100644 --- a/target/riscv/cpu.h +++ b/target

[RFC 0/5] Privilege version update

privileged spec version should be updated in the csr table if required. I am open to other suggestions as well. [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Atish Patra (5): target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in

[RFC 5/5] target/riscv: Enable privileged spec version 1.12

Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 8 +--- target/riscv/csr.c | 10 ++ 2 files

[RFC 3/5] target/riscv: Add support for mconfigptr

RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra --- target/riscv/cpu_b

[RFC 4/5] target/riscv: Add *envcfg* CSRs support

The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 31

[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.

-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 103 ++--- 2 files changed, 69 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 671f65100b1a..7f87917204c5 100644 --- a/target/riscv/cpu.h +++ b

Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions

On Tue, Jan 18, 2022 at 8:48 AM Christoph Muellner wrote: > > The RISC-V base cache management operation ISA extension has been > ratified [1]. This patch adds support for the defined instructions > and CSRs. > > [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions > > Co-developed

Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

On Sun, Jan 9, 2022 at 11:51 PM Bin Meng wrote: > > On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote: > > > > From: Atish Patra > > > > mcycle/minstret are actually WARL registers and can be written with any > > given value. With SBI PMU extension, it will

Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree

On Fri, Jan 7, 2022 at 6:46 AM Philippe Mathieu-Daudé wrote: > > On 7/1/22 01:48, Atish Patra wrote: > > Qemu virt machine can support few cache events and cycle/instret counters. > > It also supports counter overflow for these events. > > > > Add a DT node so that

[PATCH v4 10/11] target/riscv: Add few cache related PMU events

From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26

[PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[PATCH v4 08/11] target/riscv: Add sscofpmf extension support

ed to handle the overflow. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 156 -- target/riscv/pmu.c | 346 +++

[PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function

From: Atish Patra The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng

[PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents

From: Atish Patra With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 11

[PATCH v4 09/11] target/riscv: Simplify counter predicate function

All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Signed-off-by:

[PATCH v4 00/11] Improve PMU support

hub.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/linux/tree/riscv_pmu_v5 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v4 Atish Patra (11): target/riscv: Fix PMU CSR predicat

[PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR

From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h

[PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable

by the cpu. Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu

From: Atish Patra The PMU counters are supported via cpu config "Counters" which doesn't indicate the correct purpose of those counters. Rename the config property to pmu to indicate that these counters are performance monitoring counters. This aligns with cpu options for ARM

[PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode

From: Atish Patra Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair

[PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret

Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support

On Sun, Dec 26, 2021 at 8:38 PM Frank Chang wrote: > > Atish Patra 於 2021年10月26日 週二 上午3:57寫道： >> >> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, >> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) >> exten

Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

On Thu, Nov 4, 2021 at 4:47 AM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 4:41 AM Atish Patra wrote: > > > > The RISC-V privilege specification provides flexibility to implement > > any number of counters from 29 programmable counters. However, the QEMU > &g

Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu

On Thu, Nov 4, 2021 at 4:11 AM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 4:02 AM Atish Patra wrote: > > > > The PMU counters are supported via cpu config "Counters" which doesn't > > indicate the correct purpose of those counters. > > > >

Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for

On Thu, Nov 4, 2021 at 4:08 AM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 3:56 AM Atish Patra wrote: > > > > The commit title is incomplete > Oops. Fixed it. > > > Currently, the predicate function for PMU related CSRs only works if > > virtualizatio

[ PATCH v3 08/10] target/riscv: Add sscofpmf extension support

ed to handle the overflow. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 150 +- target/riscv/machine.c | 2 +- targ

[ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

by the cpu. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b55f5ed0036

[ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function

The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Signed-off-by: Atish Patra --- target/riscv/csr.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target

[ PATCH v3 09/10] target/riscv: Add few cache related PMU events

Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26 ++ 1 file changed, 26

[ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 target/riscv/csr.c | 25 + target/riscv/machine.c | 5

[ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu

Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e63..3b55f5ed0036 100644 --- a/target/riscv/cpu.c +++ b/tar

[ PATCH v3 00/10] Improve PMU support

G_2sihbfd/edit [3] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2 [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v3 Atish Patra (10): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for tar

[ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents

With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 12 ++ target/riscv/csr.c | 468

[ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Signed-off-by: Atish Patra

[ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation

counter infrastructure. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 24 +-- target/riscv/csr.c | 144 ++- target/riscv/machine.c | 26 ++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 + target/riscv

[ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for

Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Signed-off-by: Atish Patra --- target/riscv

Re: [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable

On Wed, Sep 15, 2021 at 7:51 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:29 AM Atish Patra wrote: > > > > The RISC-V privilege specification provides flexibility to implement > > any number of counters from 29 programmable counters. However, the Qemu > > nits:

Re: [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR

On Wed, Sep 15, 2021 at 7:54 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:29 AM Atish Patra wrote: > > > > As per the privilege specification v1.11, mcountinhibit allows to start/stop > > a pmu counter selectively. > > > > Signed-off-by: Atish Patra >

Re: [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function

On Wed, Sep 15, 2021 at 7:51 AM Bin Meng wrote: > > On Fri, Sep 10, 2021 at 4:27 AM Atish Patra wrote: > > > > Currently, the predicate function for PMU related CSRs only works if > > virtualization is enabled. Ideally, they should check the mcountern > > bits bef

[ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation

counter infrastructure. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 24 +-- target/riscv/csr.c | 144 ++- target/riscv/machine.c | 26 ++- target/riscv/meson.build | 1 + target/riscv/pmu.c | 32 + target/riscv

[ RFC v2 7/9] target/riscv: Add sscofpmf extension support

ed to handle the overflow. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 +++ target/riscv/csr.c | 152 +- target/riscv/pmu.c | 343 +++- target/ris

[ RFC v2 5/9] target/riscv: Add support for hpmcounters/hpmevents

With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 12 ++ target/riscv/csr.c | 468

[ RFC v2 0/9] Improve PMU support

k. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf [3] https://github.com/atishp04/linux/tree/riscv_pmu_v3 [4] https://github.com/a

[ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable

by the cpu. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 96 ++ 3 files changed, 65 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7a486450ebc6

[ RFC v2 8/9] target/riscv: Add few cache related PMU events

Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 26 ++ 1 file changed, 26

[ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 target/riscv/csr.c | 25 + target/riscv/machine.c | 5

[ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree

Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. Signed-off-by: Atish Patra --- hw/riscv/virt.c| 25

[ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu

Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb7604f..7a486450ebc6 100644 --- a/target/riscv/cpu.c +++ b/tar

[ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function

Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. Ideally, they should check the mcountern bits before cycle/minstret/hpmcounterx access. The predicate function also calculates the counter index incorrectly for hpmcounterx. Signed-off-by: Atish Patra

[ RFC 6/6] hw/riscv: virt: DEBUG PATCH to test PMU

ned-off-by: Atish Patra --- hw/riscv/virt.c | 34 -- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84570ad6425b..59d8325bf2a1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -194,7 +194,9 @@ static void

[ RFC 3/6] target/riscv: Support mcycle/minstret write operation

mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Signed-off-by: Atish Patra --- target

[ RFC 5/6] hw/riscv: virt: Add PMU device tree node to support SBI PMU extension

Qemu can't really support any PMU events other than cycle & instructions counters. Add a PMU device tree node only for these events based on device tree bindings defined in OpenSBI Signed-off-by: Atish Patra --- hw/riscv/virt.c | 22 -- 1 file changed, 20 inserti

[ RFC 0/6] Improve PMU support

04/linux/tree/riscv_pmu_v1 [4] https://github.com/atishp04/qemu/tree/riscv_pmu_v1 Atish Patra (6): target/riscv: Remove privilege v1.9 specific CSR related code target/riscv: Implement mcountinhibit CSR target/riscv: Support mcycle/minstret write operation target/riscv: Add support for hpmcounter

[ RFC 2/6] target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 target/riscv/csr.c | 23 +++ target/riscv/machine.c | 1 + 4

[ RFC 4/6] target/riscv: Add support for hpmcounters/hpmevents

With SBI PMU extension, user can use any of the available hpmcounters to track any perf events based on the value written to mhpmevent csr. Add read/write functionality for these csrs. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 7 + target/riscv/csr.c | 444

[ RFC 1/6] target/riscv: Remove privilege v1.9 specific CSR related code

Qemu doesn't support RISC-V privilege specification v1.9. Remove the remaining v1.9 specific references from the implementation. Signed-off-by: Atish Patra --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 4 +--- target/riscv/cpu_bits.h | 23 - t

Re: [PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured

On Thu, 2021-01-07 at 09:19 -0800, Alistair Francis wrote: > On Wed, Dec 23, 2020 at 11:26 AM Atish Patra > wrote: > > > > As per the privilege specification, any access from S/U mode should > > fail > > if no pmp region is configured. > > This doesn'

[v2 PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

ng Signed-off-by: Atish Patra --- Changes from v2->v1 1. Added the fixes tag and updated aligned down address to 16MB. --- hw/riscv/boot.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d62f3dc7581e..2ed23c7e9849 100644 --- a/hw

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

On Wed, 2021-01-06 at 08:04 +0800, Bin Meng wrote: > Hi Atish, > > On Wed, Jan 6, 2021 at 7:44 AM Atish Patra > wrote: > > > > On Tue, 2021-01-05 at 11:11 +0800, Bin Meng wrote: > > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra > > > wrote: > >

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

On Tue, 2021-01-05 at 11:11 +0800, Bin Meng wrote: > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra > wrote: > > > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which > > ever is > > lesser. However, Linux kernel can address only 1GB of memory for >

Re: [PATCH] RISC-V: Place DTB at 3GB boundary instead of 4GB

On Tue, 2020-12-29 at 12:49 +0800, Bin Meng wrote: > Hi Atish, > > On Wed, Dec 23, 2020 at 9:20 AM Bin Meng wrote: > > > > Hi Atish, > > > > On Wed, Dec 23, 2020 at 3:59 AM Atish Patra > > wrote: > > > > > > On Tue, 20

Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured

On Tue, 2020-12-22 at 18:49 -0800, Richard Henderson wrote: > On 12/22/20 5:21 PM, Atish Patra wrote: > > +++ b/target/riscv/pmp.c > > @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState > > *env, uint32_t pmp_index) > >  /* > >   *

[PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured

As per the privilege specification, any access from S/U mode should fail if no pmp region is configured. Signed-off-by: Atish Patra --- Changes from v2->v1 1. Removed the static from the function definition --- target/riscv/op_helper.c | 5 + target/riscv/pmp.c | 4 ++-- target/ri

[PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured

As per the privilege specification, any access from S/U mode should fail if no pmp region is configured. Signed-off-by: Atish Patra --- target/riscv/op_helper.c | 5 + target/riscv/pmp.c | 4 ++-- target/riscv/pmp.h | 1 + 3 files changed, 8 insertions(+), 2 deletions(-) diff

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