On Tue, 2020-12-22 at 13:35 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Sat, Dec 19, 2020 at 3:46 AM Atish Patra
> wrote:
> >
> > On Fri, 2020-12-18 at 16:42 +0800, Bin Meng wrote:
> > > Hi Atish,
> > >
> > > On Fri, Dec 18, 2020 at 4:00 PM Atis
On Fri, 2020-12-18 at 16:42 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Fri, Dec 18, 2020 at 4:00 PM Atish Patra
> wrote:
> >
> > On Fri, 2020-12-18 at 15:33 +0800, Bin Meng wrote:
> > > Hi Atish,
> > >
> > > On Fri, Dec 18, 2020 at 3:27 PM Atis
On Fri, 2020-12-18 at 15:33 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Fri, Dec 18, 2020 at 3:27 PM Atish Patra
> wrote:
> >
> > On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote:
> > > Hi Atish,
> > >
> > > On Fri, Dec 18, 2020 at 5:48 AM A
On Fri, 2020-12-18 at 15:21 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Fri, Dec 18, 2020 at 5:48 AM Atish Patra
> wrote:
> >
> > Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> > ever is
> > lesser. However, Linux kernel can address only
On Thu, 2020-12-17 at 14:31 -0800, Palmer Dabbelt wrote:
> On Thu, 17 Dec 2020 13:48:26 PST (-0800), Atish Patra wrote:
> > Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> > ever is
> > lesser. However, Linux kernel can address only 1GB of memory for
>
is used.
Fix this by placing the DTB at 2MB from 3GB or end of DRAM whichever is lower.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d62f3dc7581e..9e77b22e4d56 100644
--- a/hw/riscv
t the end of
the DRAM or 4GB whichever is lesser.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/boot.c | 53 +
hw/riscv/sifive_u.c | 28 ++
hw/riscv/spike.c| 7 +-
hw/riscv/virt.c
continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/boot.c | 42 ++
Qemu (with MSEL changes for sifive_u).
2. Improved the code organization
Atish Patra (4):
riscv: Unify Qemu's reset vector code path
RISC-V: Copy the fdt in dram instead of ROM
riscv: Add opensbi firmware dynamic support
RISC-V: Support 64 bit start address
hw/riscv
.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
hw/riscv/boot.c | 46 +
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c| 41 +++-
hw/riscv/virt.c
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 6 +-
hw/riscv/sifive_u.
On Sat, Jun 27, 2020 at 2:55 AM Bin Meng wrote:
>
> On Sat, Jun 27, 2020 at 12:37 PM Atish Patra wrote:
> >
> > On Fri, Jun 26, 2020 at 7:54 PM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
> > > On Sat, Jun 27, 2020 at 12:58 AM Atish Patra
On Fri, Jun 26, 2020 at 7:54 PM Bin Meng wrote:
>
> Hi Atish,
>
> On Sat, Jun 27, 2020 at 12:58 AM Atish Patra wrote:
> >
> > On Fri, Jun 26, 2020 at 4:50 AM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
> > > On Fri, Jun 26, 2020 at 8:
On Fri, Jun 26, 2020 at 5:18 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Fri, Jun 26, 2020 at 8:33 AM Atish Patra wrote:
> >
> > OpenSBI is the default firmware in Qemu and has various firmware loading
> > options. Currently, qemu loader uses fw_jump which has a compil
On Fri, Jun 26, 2020 at 4:50 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Fri, Jun 26, 2020 at 8:33 AM Atish Patra wrote:
> >
> > Currently, the fdt is copied to the ROM after the reset vector. The firmware
> > has to copy it to DRAM. Instead of this, directly cop
continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/boot.c | 39 +++
.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/boot.c | 45 +
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c| 41 +++--
hw/riscv/virt.c | 40
t the end of
the DRAM or 4GB whichever is lesser.
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/boot.c | 57 +
hw/riscv/sifive_u.c | 32 +++
hw/riscv/spike.c| 7 -
hw/riscv/virt.c
ak the existing setup.
Changes from v2->v3:
1. Removed redundant header includes.
Changes from v1->v2:
1. Rebased on top of latest upstream Qemu (with MSEL changes for sifive_u).
2. Improved the code organization
Atish Patra (3):
riscv: Unify Qemu's reset vector code path
RISC-V: Copy the
On Thu, Jun 25, 2020 at 12:50 PM Alistair Francis wrote:
>
> On Thu, Jun 25, 2020 at 11:38 AM Atish Patra wrote:
> >
> > Currently, all riscv machines except sifive_u have identical reset vector
> > code implementations with memory addresses being different for all m
continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 39 --
hw/riscv/sifive_u.c
t the end of
the DRAM or 4GB whichever is lesser.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 57 +
hw/riscv/sifive_u.c | 32 +++
hw/riscv/spike.c| 7 -
hw/riscv/virt.c | 7 -
include/hw/riscv/b
ak the existing setup.
Changes from v1->v2:
1. Rebased on top of latest upstream Qemu (with MSEL changes for sifive_u).
2. Improved the code organization
Atish Patra (3):
riscv: Unify Qemu's reset vector code path
RISC-V: Copy the fdt in dram instead of ROM
riscv: Add opensbi firmware dynamic s
.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 46 +
hw/riscv/spike.c| 38 +++---
hw/riscv/virt.c | 37 +++--
include/hw/riscv/boot.h | 2 ++
4 files changed, 54 insertions
On Fri, Jun 19, 2020 at 10:11 AM Alexander Richardson
wrote:
>
> On Tue, 16 Jun 2020 at 20:30, Atish Patra wrote:
> >
> > Currently, all riscv machines have identical reset vector code
> > implementations with memory addresses being different for all machines.
> &g
On Thu, Jun 18, 2020 at 1:03 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:30 AM Atish Patra wrote:
> >
> > Currently, all riscv machines have identical reset vector code
> > implementations with memory addresses being different for all machines.
> > They can be
On Thu, Jun 18, 2020 at 1:26 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:29 AM Atish Patra wrote:
> >
> > Currently, the fdt is copied to the ROM after the reset vector. The firmware
> > has to copy it to DRAM. Instead of this, directly copy the device tree to
On Thu, Jun 18, 2020 at 1:56 AM Bin Meng wrote:
>
> On Wed, Jun 17, 2020 at 3:29 AM Atish Patra wrote:
> >
> > This series adds support OpenSBI dynamic firmware support to Qemu.
> > Qemu loader passes the information about the DT and next stage (i.e. kernel
> > or
: Atish Patra
---
hw/riscv/boot.c | 46 +
hw/riscv/sifive_u.c | 38 +++---
hw/riscv/spike.c| 38 +++---
hw/riscv/virt.c | 37 +++--
include/hw/riscv
ak the existing setup.
Atish Patra (3):
riscv: Unify Qemu's reset vector code path
RISC-V: Copy the fdt in dram instead of ROM
riscv: Add opensbi firmware dynamic support
hw/riscv/boot.c | 95 +
hw/riscv/sifive_u.c | 59 -
t the end of
the DRAM or 4GB whichever is lesser.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 45 ++---
hw/riscv/sifive_u.c | 14 -
hw/riscv/spike.c| 14 -
hw/riscv/virt.c | 13 +++-
include/hw/
continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.
Signed-off-by: Atish Patra
---
hw/riscv/boot.c | 32 --
hw/riscv/sifive_u.c
r (timer and IPI) */
> sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
> @@ -472,15 +536,39 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
> mc->max_cpus = 1;
> }
>
> -static void spike_machine_init(MachineClass *mc)
> +DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
> +DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
> +
> +static void spike_machine_instance_init(Object *obj)
> +{
> +}
> +
> +static void spike_machine_class_init(ObjectClass *oc, void *data)
> {
> -mc->desc = "RISC-V Spike Board";
> +MachineClass *mc = MACHINE_CLASS(oc);
> +
> +mc->desc = "RISC-V Spike board";
> mc->init = spike_board_init;
> -mc->max_cpus = 8;
> +mc->max_cpus = SPIKE_CPUS_MAX;
> mc->is_default = true;
> mc->default_cpu_type = SPIKE_V1_10_0_CPU;
> +mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
> +mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
> +mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> +mc->numa_mem_supported = true;
> }
>
> -DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
> -DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
> -DEFINE_MACHINE("spike", spike_machine_init)
> +static const TypeInfo spike_machine_typeinfo = {
> +.name = MACHINE_TYPE_NAME("spike"),
> +.parent = TYPE_MACHINE,
> +.class_init = spike_machine_class_init,
> +.instance_init = spike_machine_instance_init,
> +.instance_size = sizeof(SpikeState),
> +};
> +
> +static void spike_machine_init_register_types(void)
> +{
> +type_register_static(&spike_machine_typeinfo);
> +}
> +
> +type_init(spike_machine_init_register_types)
> diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
> index dc770421bc..c55fdf4d24 100644
> --- a/include/hw/riscv/spike.h
> +++ b/include/hw/riscv/spike.h
> @@ -22,12 +22,19 @@
> #include "hw/riscv/riscv_hart.h"
> #include "hw/sysbus.h"
>
> +#define SPIKE_CPUS_MAX 8
> +#define SPIKE_SOCKETS_MAX 8
> +
> +#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
> +#define SPIKE_MACHINE(obj) \
> +OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE)
> +
> typedef struct {
> /*< private >*/
> -SysBusDevice parent_obj;
> +MachineState parent;
>
> /*< public >*/
> -RISCVHartArrayState soc;
> +RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
> void *fdt;
> int fdt_size;
> } SpikeState;
> --
> 2.25.1
>
>
As the upstream version of spike removed the deprecated ISA specific
machines, the rebased patch
will be bit different from this version. But I don't think there will
be any change in functionality.
With that assumption:
Reviewed-by: Atish Patra
--
Regards,
Atish
@@ static void riscv_virt_board_init(MachineState *machine)
>memmap[VIRT_MROM].base + sizeof(reset_vec),
> &address_space_memory);
>
> -/* create PLIC hart topology configuration string */
> -plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
> -plic_hart_config = g_malloc0(plic_hart_config_len);
> -for (i = 0; i < smp_cpus; i++) {
> -if (i != 0) {
> -strncat(plic_hart_config, ",", plic_hart_config_len);
> -}
> -strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
> plic_hart_config_len);
> -plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
> -}
> -
> -/* MMIO */
> -s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
> -plic_hart_config, 0,
> -VIRT_PLIC_NUM_SOURCES,
> -VIRT_PLIC_NUM_PRIORITIES,
> -VIRT_PLIC_PRIORITY_BASE,
> -VIRT_PLIC_PENDING_BASE,
> -VIRT_PLIC_ENABLE_BASE,
> -VIRT_PLIC_ENABLE_STRIDE,
> -VIRT_PLIC_CONTEXT_BASE,
> -VIRT_PLIC_CONTEXT_STRIDE,
> -memmap[VIRT_PLIC].size);
> -sifive_clint_create(memmap[VIRT_CLINT].base,
> -memmap[VIRT_CLINT].size, 0, smp_cpus,
> -SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
> +/* SiFive Test MMIO device */
> sifive_test_create(memmap[VIRT_TEST].base);
>
> +/* VirtIO MMIO devices */
> for (i = 0; i < VIRTIO_COUNT; i++) {
> sysbus_create_simple("virtio-mmio",
> memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
> -qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
> +qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
> }
>
> gpex_pcie_init(system_memory,
> @@ -611,14 +681,14 @@ static void riscv_virt_board_init(MachineState *machine)
> memmap[VIRT_PCIE_MMIO].base,
> memmap[VIRT_PCIE_MMIO].size,
> memmap[VIRT_PCIE_PIO].base,
> - DEVICE(s->plic), true);
> + DEVICE(pcie_plic), true);
>
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> -0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
> +0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
>
> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
> -qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
> +qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
>
> virt_flash_create(s);
>
> @@ -628,8 +698,6 @@ static void riscv_virt_board_init(MachineState *machine)
>drive_get(IF_PFLASH, 0, i));
> }
> virt_flash_map(s, system_memory);
> -
> -g_free(plic_hart_config);
> }
>
> static void riscv_virt_machine_instance_init(Object *obj)
> @@ -642,9 +710,13 @@ static void riscv_virt_machine_class_init(ObjectClass
> *oc, void *data)
>
> mc->desc = "RISC-V VirtIO board";
> mc->init = riscv_virt_board_init;
> -mc->max_cpus = 8;
> +mc->max_cpus = VIRT_CPUS_MAX;
> mc->default_cpu_type = VIRT_CPU;
> mc->pci_allow_0_address = true;
> +mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
> +mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
> +mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> +mc->numa_mem_supported = true;
> }
>
> static const TypeInfo riscv_virt_machine_typeinfo = {
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e69355efaf..1beacd7666 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -23,6 +23,9 @@
> #include "hw/sysbus.h"
> #include "hw/block/flash.h"
>
> +#define VIRT_CPUS_MAX 8
> +#define VIRT_SOCKETS_MAX 8
> +
> #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
> #define RISCV_VIRT_MACHINE(obj) \
> OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
> @@ -32,8 +35,8 @@ typedef struct {
> MachineState parent;
>
> /*< public >*/
> -RISCVHartArrayState soc;
> -DeviceState *plic;
> +RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
> +DeviceState *plic[VIRT_SOCKETS_MAX];
> PFlashCFI01 *flash[2];
>
> void *fdt;
> @@ -74,6 +77,8 @@ enum {
> #define VIRT_PLIC_ENABLE_STRIDE 0x80
> #define VIRT_PLIC_CONTEXT_BASE 0x20
> #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
> +#define VIRT_PLIC_SIZE(__num_context) \
> +(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
>
> #define FDT_PCI_ADDR_CELLS3
> #define FDT_PCI_INT_CELLS 1
> --
> 2.25.1
>
>
LGTM.
Reviewed-by: Atish Patra
--
Regards,
Atish
t; + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_NUMA_H
> +#define RISCV_NUMA_H
> +
> +#include "hw/sysbus.h"
> +#include "sysemu/numa.h"
> +
> +int riscv_socket_count(const MachineState *ms);
> +
> +int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
> +
> +int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
> +
> +int riscv_socket_hart_count(const MachineState *ms, int socket_id);
> +
> +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
> +
> +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
> +
> +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
> +
> +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
> + const char *node_name, int socket_id);
> +
> +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void
> *fdt);
> +
> +CpuInstanceProperties
> +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
> +
> +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
> +
> +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
> +
> +#endif /* RISCV_NUMA_H */
> --
> 2.25.1
>
>
LGTM.
Reviewed-by: Atish Patra
--
Regards,
Atish
> > > Francis
> > > Sent: 11 June 2020 04:59
> > > To: Anup Patel
> > > Cc: Peter Maydell ; open list:RISC-V
> > > > > ri...@nongnu.org>; Sagar Karandikar ;
> > > Anup
> > > Patel ; qemu-devel@nongnu.org Developers
> > >
T_PLIC_ENABLE_BASE,
> -VIRT_PLIC_ENABLE_STRIDE,
> -VIRT_PLIC_CONTEXT_BASE,
> -VIRT_PLIC_CONTEXT_STRIDE,
> -memmap[VIRT_PLIC].size);
> -sifive_clint_create(memmap[VIRT_CLINT].base,
> -memmap[VIRT_CLINT].size, 0, smp_cpus,
> -SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
> +/* SiFive Test MMIO device */
> sifive_test_create(memmap[VIRT_TEST].base);
>
> +/* VirtIO MMIO devices */
> for (i = 0; i < VIRTIO_COUNT; i++) {
> sysbus_create_simple("virtio-mmio",
> memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
> -qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
> +qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
> }
>
> gpex_pcie_init(system_memory,
> @@ -611,14 +667,14 @@ static void riscv_virt_board_init(MachineState *machine)
> memmap[VIRT_PCIE_MMIO].base,
> memmap[VIRT_PCIE_MMIO].size,
> memmap[VIRT_PCIE_PIO].base,
> - DEVICE(s->plic), true);
> + DEVICE(pcie_plic), true);
>
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> -0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
> +0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
>
> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
> -qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
> +qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
>
> virt_flash_create(s);
>
> @@ -628,12 +684,37 @@ static void riscv_virt_board_init(MachineState *machine)
>drive_get(IF_PFLASH, 0, i));
> }
> virt_flash_map(s, system_memory);
> +}
>
> -g_free(plic_hart_config);
> +static bool riscv_virt_get_multi_socket(Object *obj, Error **errp)
> +{
> +RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
> +
> +return s->multi_socket;
> +}
> +
> +static void riscv_virt_set_multi_socket(Object *obj, bool value, Error
> **errp)
> +{
> +RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
> +
> +s->multi_socket = value;
> }
>
> static void riscv_virt_machine_instance_init(Object *obj)
> {
> +RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
> +
> +/*
> + * Multi-socket is disabled by default so users have to
> + * explicitly enable it from command-line.
> + */
> +s->multi_socket = false;
> +object_property_add_bool(obj, "multi-socket",
> + riscv_virt_get_multi_socket,
> + riscv_virt_set_multi_socket);
> +object_property_set_description(obj, "multi-socket",
> +"Set on/off to enable/disable the "
> +"multi-socket support");
> }
>
> static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
> @@ -642,7 +723,7 @@ static void riscv_virt_machine_class_init(ObjectClass
> *oc, void *data)
>
> mc->desc = "RISC-V VirtIO board";
> mc->init = riscv_virt_board_init;
> -mc->max_cpus = 8;
> +mc->max_cpus = VIRT_CPUS_MAX;
> mc->default_cpu_type = VIRT_CPU;
> mc->pci_allow_0_address = true;
> }
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e69355efaf..e5fe10ad48 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -23,6 +23,9 @@
> #include "hw/sysbus.h"
> #include "hw/block/flash.h"
>
> +#define VIRT_CPUS_MAX 8
> +#define VIRT_SOCKETS_MAX 4
> +
> #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
> #define RISCV_VIRT_MACHINE(obj) \
> OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
> @@ -32,8 +35,10 @@ typedef struct {
> MachineState parent;
>
> /*< public >*/
> -RISCVHartArrayState soc;
> -DeviceState *plic;
> +bool multi_socket;
> +unsigned int num_socs;
> +RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
> +DeviceState *plic[VIRT_SOCKETS_MAX];
> PFlashCFI01 *flash[2];
>
> void *fdt;
> @@ -74,6 +79,8 @@ enum {
> #define VIRT_PLIC_ENABLE_STRIDE 0x80
> #define VIRT_PLIC_CONTEXT_BASE 0x20
> #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
> +#define VIRT_PLIC_SIZE(__num_context) \
> +(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
>
> #define FDT_PCI_ADDR_CELLS3
> #define FDT_PCI_INT_CELLS 1
> --
> 2.25.1
>
>
Otherwise, looks good to me.
Reviewed-by: Atish Patra
--
Regards,
Atish
On Mon, 2019-06-24 at 16:24 -0700, Alistair Francis wrote:
> On Mon, Jun 24, 2019 at 3:57 PM Atish Patra
> wrote:
> > Currently, there is no cpu topology defined in RISC-V.
> > Define a device tree node that clearly describes the
> > entire topology. This saves the troubl
cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..45a1edcd6c4a 100644
--- a/hw/riscv/vi
cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
---
hw/riscv/virt.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..da0b8aa18747 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -2
OpenSBI version 0.1 is now publicly available in GitHub at
https://github.com/riscv/opensbi.
OpenSBI is an open source implementation of the RISC-V Supervisor Binary
Interface (SBI). RISC-V SBI specifications are maintained as an
independent project by the RISC-V Foundation in [Github].
This i
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