erture_size = ATI_RADEON_LINEAR_APERTURE_SIZE;
+} else {
+aperture_size = ATI_RAGE128_LINEAR_APERTURE_SIZE;
+}
+memory_region_init(&s->linear_aper, OBJECT(dev), "ati-linear-aperture0",
+ aperture_size);
+
No new line needed here, it's still setting up BAR0 s
The DP_GUI_MASTER_CNTL register has separate bits for src and dest but
we were only looking at the dest bit. Use the correct bit for source.
Signed-off-by: BALATON Zoltan
---
hw/display/ati_2d.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/display/ati_2d.c
ed in the
header. I don't know if this is relevant but it keeps closer to the
current behaviour.
Regards,
BALATON Zoltan
space.
The goal is to reduce the risk of AS mis-use for targets
that uses multiple ASes per vCPU.
Based-on: <20251001082127.65741-1-phi...@linaro.org>
Philippe Ma
On Wed, 1 Oct 2025, Daniel P. Berrangé wrote:
On Wed, Oct 01, 2025 at 07:56:21PM +0200, BALATON Zoltan wrote:
On Wed, 1 Oct 2025, Alex Bennée wrote:
My first set of patches for the development tree. Should be mostly
self-explanatory. We still need to apply the upstream COPYING patch
the u-boot
myaddr, length);
Does this now fit on one line?
Regards,
BALATON Zoltan
return res == MEMTX_OK ? 0 : EIO;
}
d, otherwise I'd need
to send patches for each update and rely on somebody to merge them.
Regards,
BALATON Zoltan
Hopefully I'll have the new aarch64 runner online by Friday and ready
for the switchover.
Hopefully I'll also be able to pick up Gustavo's reverse debug test
];
uint64_t v;
CPUState *cs = mon_get_cpu(mon);
+AddressSpace *as = cs ? cpu_get_address_space(cs, 0)
+ : &address_space_memory;
Why move from local scope to an upper level?
Regards,
BALATON Zoltan
if (!cs && (format == 'i
On Wed, 10 Sep 2025, Alex Bennée wrote:
"Julian Ganz" writes:
September 10, 2025 at 12:06 PM, "BALATON Zoltan" wrote:
On Tue, 9 Sep 2025, Julian Ganz wrote:
I ran streamPPCpowerpcO3 on qemu with these patches:
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
The bit that is supposed to control if ISA IO ports are accessed with
discontiguous addresses was not connected so it did nothing. We can
now directly enable or disable the discontiguous region so allow the
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
Export memory regions as sysbus mmio regions and let the board code
map them similar to how it is done in grackle.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
Move the lines related to creating the bus master address space
together and reduce the number of memory regions stored in the device
state. These are used once to create the address space and can be
tracked
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
PREP allows remapping of the 64k ISA IO addresses from the normal
contiguous IO space into a discontiguous 8MB region and can switch
between the two modes. We can implement this in a simpler way than is
done
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
The mmcfg field in PCIHostState is only used by raven for the PCI
config direct access but is not actually needed as the memory region
lifetime can be managed by the object given during init so use that
and
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
Instead of passing unneeded enclosing objects to the config direct
access ops that only need the bus we can pass that directly thus
simplifying the functions.
Signed-off-by: BALATON Zoltan
Reviewed-by
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
No need to use an or-irq to map interrupt lines to a single IRQ as the
PCI code can handle this internally so simplify by dropping the or-irq.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 39
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 18/09/2025 19:50, BALATON Zoltan wrote:
The raven PCI device does not need a state struct as it has no data to
store there any more, so we can remove that to simplify code.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 30
The raven PCI device does not need a state struct as it has no data to
store there any more, so we can remove that to simplify code.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/hw/pci
the address space that is used later in a
callback.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37 ++---
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index bf4f4b7f71..ebf0c511dc 100644
--- a
Convert to using DEFINE_TYPES macro and move raven_pcihost_class_init
so methods of each object are grouped together.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 57 +
1 file changed, 26 insertions
Instead of passing unneeded enclosing objects to the config direct
access ops that only need the bus we can pass that directly thus
simplifying the functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 14 +++---
1 file changed, 7
On Thu, 18 Sep 2025, Mark Cave-Ayland wrote:
On 17/09/2025 12:19, BALATON Zoltan wrote:
On Thu, 3 Jul 2025, BALATON Zoltan wrote:
Hello,
Ping? Do we have hw/ppc maintainers who can look at this and merge it?
Apologies for the delay, things have been quite hectic here. I'll take a
bit which was there but did not work as it
was not connected but apparently it's not really used by any guest so
that wasn't noticed.
Regards,
BALATON Zoltan
V3:
- rebase on master
- Fix issue with device-crash-test reported by Akihiko Odaki: make
sure device is correctly used by add
Export memory regions as sysbus mmio regions and let the board code
map them similar to how it is done in grackle.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37 -
hw/ppc/prep.c | 11 +--
2 files changed, 21 insertions(+), 27
enabling/disabling the discontiguous
region as needed.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 88 -
1 file changed, 22 insertions(+), 66 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index bb0be40eb4..bf4f4b7f71
discontiguous IO addresses.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c| 9 -
hw/ppc/prep.c | 3 +++
hw/ppc/prep_systemio.c | 17 +++--
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index
Rename memory io ops implementing PCI configuration direct access to
mmcfg which describes better what these are for.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host
The PCI configuration direct access region occupies 8 MiB at offset
0x80 in PCI IO space so model that accordingly.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host
No need to use an or-irq to map interrupt lines to a single IRQ as the
PCI code can handle this internally so simplify by dropping the or-irq.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 39 +++
hw/ppc/prep.c | 5 -
2 files changed, 19
Use OBJECT_DECLARE_SIMPLE_TYPE macro instead of open coding it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index 172f01694c
Use ctz instead of an open coded version and rename function to better
show what it does.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index a400a22df3
The mmcfg field in PCIHostState is only used by raven for the PCI
config direct access but is not actually needed as the memory region
lifetime can be managed by the object given during init so use that
and remove the unused field from PCIHostState.
Signed-off-by: BALATON Zoltan
---
hw/pci-host
Instead of doing it manually use pci_register_root_bus() to create and
register the PCI bus.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index e0f98afebf
e that and I don't have to rebase that series. Otherwise these are
not related. I'll check the problem reported about my series and send an
updated one.
Regards,
BALATON Zoltan
is in
qemu-system-ppc64? Even if the CPU is 32-bit it has some 64-bit
instructions IIUC so does that make it TARGET_PPC64 only?
Regards,
BALATON Zoltan
On Thu, 3 Jul 2025, BALATON Zoltan wrote:
Hello,
Ping? Do we have hw/ppc maintainers who can look at this and merge it?
Regards,
BALATON Zoltan
This series cleans up and simplifies the raven model which does some
strange stuff that no other pci-host is doing and does it in a
convoluted way
On Tue, 9 Sep 2025, Julian Ganz wrote:
September 7, 2025 at 10:21 PM, "BALATON Zoltan" wrote:
I have uploaded some PPC binaries for the STREAM benchmark that I tested with
before here:
http://zero.eik.bme.hu/~balaton/qemu/stream-test.zip
which may excercise this if run on sam460ex
On Fri, 5 Sep 2025, Julian Ganz wrote:
September 5, 2025 at 9:25 PM, "BALATON Zoltan" wrote:
On Fri, 5 Sep 2025, Julian Ganz wrote:
September 5, 2025 at 1:38 PM, "BALATON Zoltan" wrote:
Have you done any testing on how much overhead this adds
to interrupt heavy guest wor
ean ups) but I could not get
that merged in the last devel cycle because of PPC being a bit
unmaintained. I'd prefer that series to be taken first instead of this
patch so I don't have to rebase that.
Regards,
BALATON Zoltan
Signed-off-by: Akihiko Odaki
---
hw/pci-host/raven.c | 27
On Fri, 5 Sep 2025, Julian Ganz wrote:
September 5, 2025 at 1:38 PM, "BALATON Zoltan" wrote:
On Thu, 4 Sep 2025, Julian Ganz wrote:
Even with the existing interfaces, it is more or less possible to
discern these situations, e.g. as done by the cflow plugin. However,
this proce
ready much
slower than real CPU so I'd like it to get faster not slower.
Regards,
BALATON Zoltan
These changes introduce a generic and easy-to-use interface for plugin
authors in the form of a callback for discontinuities. Patch 1 defines
an enumeration of some trap-related discontinuities
209,16 +211,42 @@ struct DisasContext {
#define DISAS_CHAINDISAS_TARGET_2 /* lookup next tb, pc updated */
#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
-/* Return true iff byteswap is needed in a scalar memop */
+/* Return true if byteswap is needed in instruction fetch */
This is likely not a typo but short for if and only if. Leave it
unchanged.
Regards,
BALATON Zoltan
QOM objects
since commit 067109a11c8 just an empty line after parent_obj.
Regards,
BALATON Zoltan
On Fri, 29 Aug 2025, Mark Cave-Ayland wrote:
On 15/07/2025 14:38, BALATON Zoltan wrote:
On Tue, 15 Jul 2025, Mark Cave-Ayland wrote:
Use QOM casts to convert between VFIOPCIDevice and PCIDevice instead of
accessing pdev directly.
Signed-off-by: Mark Cave-Ayland
---
hw/vfio/pci.c | 202
On Tue, 26 Aug 2025, Harsh Prateek Bora wrote:
On 8/25/25 20:03, BALATON Zoltan wrote:
On Mon, 25 Aug 2025, Harsh Prateek Bora wrote:
On 8/25/25 17:52, Thomas Huth wrote:
On 25/08/2025 14.08, Harsh Prateek Bora wrote:
On 8/25/25 17:28, Thomas Huth wrote:
As I said, qemu-system-ppc64 is
achines like mac_newworld that behaves differently
in qemu-system-ppc and qemu-system-ppc64 and the potentially lower
performance of qemu-system-ppc64 in emulating 32-bit machines which is why
we still have ppc-softmmu.
Regards,
BALATON Zoltan
regards,
Harsh
AFAIK we don't have a switch to disable 32-bit code in the ppc64 binary.
Thomas
On Thu, 17 Jul 2025, Xiaoyao Li wrote:
On 7/17/2025 1:28 AM, Philippe Mathieu-Daudé wrote:
Developers are custom to read RWX, not RWE.
"accustomed to"
Replace E -> X.
Reported-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Xiaoyao Li
---
accel/hvf/hvf-all.c | 2
ashed in patch 13.
Regards,
BALATON Zoltan
SocketAddress *socket;
bool send_queued; /* all sends are queued */
uint32_t wait_time; /* timeout for message replies */
necessary casts to functions
that can be called a lot.
Regards,
BALATON Zoltan
if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) {
return;
@@ -127,7 +128,7 @@ static void vfio_intx_interrupt(void *opaque)
trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A
Add field for the south bridge in machine state to have both north and
south bridges in it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index
Move the chipset reset which is pegasos2 specific out from machine
reset to a separate function and move parts not specific to pegasos2
form build_fdt in machine reset so now build_fdt contains pegasos2
specific parts and renamed accordingly.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c
Store the bus frequency in the machine state and set it from instance
init method.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index f7999520e4
These are not needed any more now that VOF can handle it.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index e15cf96427..73995624e5 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc
more generic.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c| 292 +++
pc-bios/dtb/meson.build | 1 +
pc-bios/dtb/pegasos2.dtb | Bin 0 -> 1701 bytes
pc-bios/dtb/pegasos2.dts | 167 ++
4 files changed, 220 insertions(+),
-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 170 +-
1 file changed, 124 insertions(+), 46 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index ae3f01231d..a88d93ae04 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -1,5 +1,5
Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
versions with less parameters based on that. This is inspired by how
the OBJECT_DEFINE macros do this in a similar way to allow using the
shortened definition in more complex cases too.
Signed-off-by: BALATON Zoltan
---
include
2 which is how it
identifies the machine.
Signed-off-by: BALATON Zoltan
Reviewed-by: Alexey Kardashevskiy
---
hw/ppc/vof.c | 50 +-
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c
index f14efa3a7c..
DEFINE_MACHINE macro that is later
used for more easily define the abstract machine type and hide most of
the QOM boiler plate.
Regards,
BALATON Zoltan
v2:
- rebase on master
- added some R-b tags from Philippe
- move first patch later (was first to allow merging separately)
- clarify blurb above
Rename machine state struct to PegasosMachineState as it will be used
for pegasos1 too.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 66 ---
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
Use more generic name for the field used to store the north bridge in
the machine state.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc
When running without firmware ROM using Virtual Open Firmware we need
to do some hardware initialisation and provide the device tree as the
machine firmware would normally do.
Signed-off-by: BALATON Zoltan
---
MAINTAINERS | 1 +
hw/ppc/pegasos2.c| 140
Collect steps of setting up PCI IRQ routing in one function.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 66 +++
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 66bceec5ef
The machine class has a field for storing the fdt so we don't need our
own and can use that instead.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 646755a3cc..7dc78
The mmcfg field in PCIHostState is only used by raven for the PCI
config direct access but is not actually needed as the memory region
lifetime can be managed by the object given during init so use that
and remove the unused field from PCIHostState.
Signed-off-by: BALATON Zoltan
---
hw/pci-host
discontiguous IO addresses.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c| 9 -
hw/ppc/prep.c | 3 +++
hw/ppc/prep_systemio.c | 14 --
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index
the address space that is used later in a
callback.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37 ++---
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index bf4f4b7f71..ebf0c511dc 100644
--- a
No need to use an or-irq to map interrupt lines to a single IRQ as the
PCI code can handle this internally so simplify by dropping the or-irq.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 39 +++
hw/ppc/prep.c | 5 -
2 files changed, 19
Use ctz instead of an open coded version and rename function to better
show what it does.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index a400a22df3
Export memory regions as sysbus mmio regions and let the board code
map them similar to how it is done in grackle.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37 -
hw/ppc/prep.c | 11 +--
2 files changed, 21 insertions(+), 27
The PCI configuration direct access region occupies 8 MiB at offset
0x80 in PCI IO space so model that accordingly.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host
Convert to using DEFINE_TYPES macro and move raven_pcihost_class_init
so methods of each object are grouped together.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 57 +
1 file changed, 26 insertions
Instead of passing unneeded enclosing objects to the config direct
access ops that only need the bus we can pass that directly thus
simplifying the functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 14 +++---
1 file changed, 7
The raven PCI device does not need a state struct as it has no data to
store there any more, so we can remove that to simplify code.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/hw/pci
Rename memory io ops implementing PCI configuration direct access to
mmcfg which describes better what these are for.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host
bit which was there but did not work as it
was not connected but apparently it's not really used by any guest so
that wasn't noticed.
Regards,
BALATON Zoltan
v2:
- rebase on master
- add R-b tags from Philippe
BALATON Zoltan (14):
hw/pci-host/raven: Simplify PCI facing part
hw/pci-
Instead of doing it manually use pci_register_root_bus() to create and
register the PCI bus.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index e0f98afebf
enabling/disabling the discontiguous
region as needed.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 88 -
1 file changed, 22 insertions(+), 66 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index bb0be40eb4..bf4f4b7f71
Use OBJECT_DECLARE_SIMPLE_TYPE macro instead of open coding it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index 172f01694c
node characters
(e.g., +--, |--), is a better approach.
As BALATON Zoltan pointed out, retaining space-based indentation for displaying
memory region (mr) nodes helps ensure that the output remains easily parseable
by other programs. This also provides better compatibility with existing tools
and
On Mon, 16 Jun 2025, Philippe Mathieu-Daudé wrote:
On 11/3/25 13:58, Nicholas Piggin wrote:
From: BALATON Zoltan
Add support for -kernel, -initrd and -append command line options.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Message-ID
depends: precache_all,
command: [python, '-c', ''])
Should I send a v4 of my patch?
I think it would help if you can send a v4 also fixing up the commit
message as was discussed so Stefan does not have to do it. Generally more
than trivial fixup needs a new version of the patch sent by the author,
only fixing simple typos might not need a resend. Ideally maintainers
should not need to do any fixup just take the latest patch version.
Regards,
BALATON Zoltan
On Thu, 12 Jun 2025, Paolo Bonzini wrote:
On 6/11/25 13:45, BALATON Zoltan wrote:
On Wed, 11 Jun 2025, Daniel P. Berrangé wrote:
On Wed, Jun 11, 2025 at 02:37:08AM +0200, BALATON Zoltan wrote:
On Tue, 10 Jun 2025, Bernhard Beschow wrote:
The next patch will make dtc mandatory for boards with
On Wed, 11 Jun 2025, Stefan Hajnoczi wrote:
On Wed, Jun 11, 2025 at 3:25 PM BALATON Zoltan wrote:
On Wed, 11 Jun 2025, Stefan Hajnoczi wrote:
From: oltolm
Sorry, I forgot to cc the maintainers.
Do we want comments like this end up in git log? This could have been
fixed before a pull
gards,
BALATON Zoltan
The build failed when run on Windows. I replaced calls to Unix programs
like ´cat´, ´sed´ and ´true´ with calls to ´python´. I wrapped calls to
´os.path.relpath´ in try-except because it can fail when the two paths
are on different drives. I made sure to convert the Windows pat
On Wed, 11 Jun 2025, Daniel P. Berrangé wrote:
On Wed, Jun 11, 2025 at 02:37:08AM +0200, BALATON Zoltan wrote:
On Tue, 10 Jun 2025, Bernhard Beschow wrote:
The next patch will make dtc mandatory for boards with a bundled DTB, causing
these boards to be omitted when dtc is missing. Allow
nown
working dtc to compile with. Why isn't that used when we already have it
for libfdt?
Regards,
BALATON Zoltan
Signed-off-by: Bernhard Beschow
---
meson.build | 12
Kconfig.host | 3 +++
meson_options.txt | 3 +++
pc-bios/d
On Tue, 10 Jun 2025, Bernhard Beschow wrote:
When changing meson_options.txt, this script gets updated automatically by QEMU
tooling which sorts the choices lexicographically. Fix this in preparation of
the ext patch.
Typo: next patch
Fixes: ccc403ed5844 ("meson: Add wasm build in build scrip
On Tue, 10 Jun 2025, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 2/5/25 01:20, BALATON Zoltan wrote:
Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
versions with less parameters based on that. This is inspired by how
the OBJECT_DEFINE macros do this in a similar way to
On Mon, 9 Jun 2025, BALATON Zoltan wrote:
On Mon, 9 Jun 2025, Tanish Desai wrote:
Moved the logic for timestamped logging (~6 lines) from
a_nocheck__trace_foo(header) into a new qemu_log_timestamp() function in
util/log.c. This avoids code duplication across binaries and enables reuse
as a
build time or
disk space but I could be wrong.
Regards,
BALATON Zoltan
Signed-off-by: Tanish Desai
---
include/qemu/log-for-trace.h | 3 +++
scripts/tracetool/backend/log.py | 13 +
util/log.c | 18 ++
3 files changed, 22 insertions(+), 12
On Thu, 5 Jun 2025, Philippe Mathieu-Daudé wrote:
tpm_emulator_ctrlcmd() is not in hot path.
Use the heap instead of the stack, removing
the g_alloca() call.
Typo in subject L -> :
Regards,
BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
backends/tpm/tpm_emulator.c | 4 ++--
1 f
On Tue, 3 Jun 2025, Philippe Mathieu-Daudé wrote:
On 4/5/25 18:01, BALATON Zoltan wrote:
Export memory regions as sysbus mmio regions and let the board code
map them.
Why? The mapping belong to the host bridge, not the board...
I took inspiration from grackle that does it the same way
On Tue, 3 Jun 2025, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 4/5/25 18:01, BALATON Zoltan wrote:
The raven PCI device does not need a state struct as it has no data to
store there any more so we can remove that to simplify code.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 30
On Tue, 3 Jun 2025, Philippe Mathieu-Daudé wrote:
On 4/5/25 18:01, BALATON Zoltan wrote:
The mmcfg field in PCIHostState is only used by raven for the PCI
config direct access but is not actually needed as the memory region
lifetime can be managed by the object given during init so use that
and
On Tue, 3 Jun 2025, Bernhard Beschow wrote:
Am 2. Juni 2025 08:12:39 UTC schrieb "Philippe Mathieu-Daudé"
:
On 30/5/25 02:54, BALATON Zoltan wrote:
On Thu, 29 May 2025, Bernhard Beschow wrote:
Am 25. April 2025 15:28:20 UTC schrieb "Philippe Mathieu-Daudé"
:
From: BALA
On Fri, 23 May 2025, BALATON Zoltan wrote:
On Fri, 2 May 2025, BALATON Zoltan wrote:
This series changes how the fdt for VOF is generated in pegasos2 by
moving the static parts to a dtb and only generate the changing parts
such as memory size and PCI devices programmatically. This simplifies
On Fri, 23 May 2025, BALATON Zoltan wrote:
On Sun, 4 May 2025, BALATON Zoltan wrote:
Hello,
This series cleans up and simplifies the raven model which does some
strange stuff that no other pci-host is doing and does it in a
convoluted way and also has some legacy bits that can be removed
On Mon, 2 Jun 2025, Philippe Mathieu-Daudé wrote:
On 30/5/25 02:54, BALATON Zoltan wrote:
On Thu, 29 May 2025, Bernhard Beschow wrote:
Am 25. April 2025 15:28:20 UTC schrieb "Philippe Mathieu-Daudé"
:
From: BALATON Zoltan
We have several device tree files already and may have m
On Thu, 29 May 2025, Bernhard Beschow wrote:
Am 25. April 2025 15:28:20 UTC schrieb "Philippe Mathieu-Daudé"
:
From: BALATON Zoltan
We have several device tree files already and may have more in the
future so add a new dtb subdirectory and move device tree files there
so they are
On Mon, 26 May 2025, Bernhard Beschow wrote:
Am 25. Mai 2025 00:03:15 UTC schrieb BALATON Zoltan :
On Sun, 28 Jul 2024, BALATON Zoltan wrote:
On Sun, 28 Jul 2024, quan wrote:
I am playing around with the parallel port on the pegasos 2 and I noticed
the following issue:
The parallel port on
On Sun, 28 Jul 2024, BALATON Zoltan wrote:
On Sun, 28 Jul 2024, quan wrote:
I am playing around with the parallel port on the pegasos 2 and I noticed
the following issue:
The parallel port on startup is set to iobase 0x378, then later it gets
remapped to iobase 0x3bc.
When I tried writing to
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