On 11/30/23 10:52, YangHang Liu wrote:
After applying this patch, the VM with a igbvf will not crash during reboot.
Tested-by: Yanghang Liumailto:yangh...@redhat.com>>
Michael, do you have plans to send a PR for -rc3 ?
Thanks,
C.
On Mon, Nov 27, 2023 at 5:12 PM Cédric Le
On 11/29/23 22:26, Stefan Hajnoczi wrote:
The name "iothread" is overloaded. Use the term Big QEMU Lock (BQL)
instead, it is already widely used and unambiguous.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Cédric Le Goater
Thanks,
C.
-by: Stefan Hajnoczi
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 11/29/23 22:26, Stefan Hajnoczi wrote:
The name "iothread" is overloaded. Use the term Big QEMU Lock (BQL)
instead, it is already widely used and unambiguous.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Cédric Le Goater
Thanks,
C.
mes. Subsequent patches
will rename them. There are also comments and documentation that will be
updated in later patches.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 11/29/23 22:29, Cédric Le Goater wrote:
On 11/29/23 15:56, Ninad Palsule wrote:
Hello Cedric,
On 11/27/23 10:31, Cédric Le Goater wrote:
Hello Ninad,
On 10/26/23 18:47, Ninad Palsule wrote:
Hello,
Please review the patch-set version 7.
I have incorporated review comments from Cedric
On 11/29/23 15:56, Ninad Palsule wrote:
Hello Cedric,
On 11/27/23 10:31, Cédric Le Goater wrote:
Hello Ninad,
On 10/26/23 18:47, Ninad Palsule wrote:
Hello,
Please review the patch-set version 7.
I have incorporated review comments from Cedric, Philippe and Thomas.
I reworked v7
On 11/28/23 18:38, Cédric Le Goater wrote:
On 11/27/23 18:13, Chalapathi V wrote:
Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed
On 11/21/23 18:11, Alex Bennée wrote:
Peter Maydell writes:
QEMU Summit Minutes 2023
As usual, we held a QEMU Summit meeting at KVM Forum. This is an
invite-only meeting for the most active maintainers and submaintainers
in the project, and we discuss various
On 11/27/23 18:13, Chalapathi V wrote:
Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed as skiboot defines the
device-tree and
On 11/24/23 09:06, Cédric Le Goater wrote:
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
vfio_pci_host_match
vfio_pci_post_reset
On 11/21/23 09:43, Zhenzhong Duan wrote:
Hi,
Thanks all for giving guides and comments on previous series, this is
the remaining part of the iommufd support.
Besides suggested changes in v6, I'd like to highlight two changes
for final review:
1. Instantiate can_be_deleted callback to fix race
On 11/27/23 18:13, Chalapathi V wrote:
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with
On 11/28/23 02:32, BALATON Zoltan wrote:
The machine uses a modified U-Boot under GPL license but the sources
of it are lost with only a binary available so it cannot be included
in QEMU. Allow running without the firmware image which can be used
when calling a boot loader directly and thus
On 11/28/23 02:47, Nicholas Piggin wrote:
On Tue Nov 28, 2023 at 2:37 AM AEST, Cédric Le Goater wrote:
I'm not sure, I don't think it's necessary if your minimal patch works.
I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
this as well.
I think this is a bit late
On 11/27/23 18:13, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
I'm not sure, I don't think it's necessary if your minimal patch works.
I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
this as well.
I think this is a bit late for 8.2 to change FW images, well, at least
SLOF and skiboot. Are the new versions fixing something
Hello Ninad,
On 10/26/23 18:47, Ninad Palsule wrote:
Hello,
Please review the patch-set version 7.
I have incorporated review comments from Cedric, Philippe and Thomas.
I reworked v7 with the suggestions I made in patches 1-6. Please check :
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embedded inside the FSI master which is a
bus controller.
The FSI
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special management
support. The scratchpad registers can be read or
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration
: Add support for Single Root I/O Virtualization
(SR/IOV)")
Buglink: https://issues.redhat.com/browse/RHEL-17209
Signed-off-by: Akihiko Odaki
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci/pcie_sriov.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/pci/pcie_sriov.
On 11/24/23 07:39, Nicholas Piggin wrote:
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending
On 11/24/23 11:10, Philippe Mathieu-Daudé wrote:
On 24/11/23 09:06, Cédric Le Goater wrote:
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
On 11/24/23 12:28, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
This part of the patchset connects the nest1 chiplet model to p10 chip.
Seems fine to me. Should it just be squashed into patch 2?
It is better to keep the model a part from the wiring because
On 11/24/23 12:26, Nicholas Piggin wrote:
For this and actually the last patch too, it would be good to mention
(possibly in a header comment in the file too) what actual functionality
is being provided/modeled. It looks like it's just modeling behaviour of
reads and writes for some registers.
On 11/24/23 12:40, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 5:16 PM AEST, Cédric Le Goater wrote:
On 11/24/23 07:39, Nicholas Piggin wrote:
[snip]
+static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
+uint64_t val, unsigned size
On 11/24/23 11:39, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 6:36 PM AEST, Cédric Le Goater wrote:
On 11/21/23 20:09, Glenn Miles wrote:
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used
On 11/21/23 20:09, Glenn Miles wrote:
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
detection
this.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
---
Reviewed-by: Cédric Le Goater
Thanks,
C.
No change from previous version
MAINTAINERS| 10 +-
hw/misc/pca9554.c | 328 +
include/hw/misc/pca9554.h | 36
Card" is present.
Signed-off-by: Glenn Miles
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
No change from previous version
hw/misc/Kconfig | 4
hw/misc/meson.build | 1 +
hw/ppc/Kconfig | 1 +
hw/ppc/pnv.c| 6 ++
4 files changed, 12 insertions(+)
diff --git
lenn Miles
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
No change from previous version
hw/ppc/pnv.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d8d19fb065..088824fd9f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
On 11/21/23 20:09, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Signed-off-by: Glenn Miles
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
Changes from previous version:
- Formatting changes
- Capitalized
On 11/24/23 09:01, Harsh Prateek Bora wrote:
On 11/23/23 19:42, Cédric Le Goater wrote:
On 11/23/23 10:31, Harsh Prateek Bora wrote:
On 11/23/23 14:20, Cédric Le Goater wrote:
On 11/23/23 06:57, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE
-default-devices
is use because VFIO is always selected in ppc/Kconfig but VFIO_PCI is
not.
Use an 'imply VFIO_PCI' in ppc/Kconfig and bypass compilation of the
VFIO EEH hooks routines defined in hw/ppc/spapr_pci_vfio.c with
CONFIG_VFIO_PCI.
Signed-off-by: Zhenzhong Duan
Signed-off-by: Cédric Le Goater
Zhenzhong,
How about what's below instead ?
Thanks,
C.
I will resend the build fix with the proposal below since it addresses
Phil's concerns.
Thanks,
C.
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -26,10 +26,12 @@
#include "hw/pci/pci_device.h"
#include
from there.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/pnv.h | 2 +
include/hw/ppc/pnv_chiptod.h | 4 ++
target/ppc/cpu.h | 7 ++
hw/ppc/pnv.c | 15
hw/ppc/pnv_chiptod.c | 132
On 11/24/23 07:39, Nicholas Piggin wrote:
The ChipTOD (for Time-Of-Day) is a chip pervasive facility that keeps a
time of day clock, and can synchronise that clock to other chips, and
can synchronize that clock to the timebase facility in each core.
This model implements basic status and error
inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/cpu.h | 8
target/ppc/helper_regs.c | 10 +-
2 files changed, 9 insertions(+), 9
by chiptod to indicate that it has sent TOD to the core timebase. The
core timebase will be implemented in later changes.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/ppc/pnv_chip.h| 3 +
include/hw/ppc/pnv_chiptod.h | 50
include
On 11/24/23 07:39, Nicholas Piggin wrote:
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/helper_regs.c | 31
also been called TBL and
it does only read TBL on 32-bit.
Change SPR 268 to be called TB on 64-bit implementations.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/helper_regs.c | 4
target/ppc/ppc-qmp-cmds.c | 4
2 files changed, 8
On 11/23/23 11:30, Nicholas Piggin wrote:
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending
On 11/23/23 11:30, Nicholas Piggin wrote:
The ChipTOD (for Time-Of-Day) is a pervasive facility that keeps the
clocks on multiple chips consistent which can keep TOD (time-of-day),
synchronise it across multiple chips, and can move that TOD to or from
the core timebase units.
May be rephrase a
On 11/23/23 11:30, Nicholas Piggin wrote:
The chiptod/TFMR/state machine is not really tied to the other
time register fixes, but they touch some of the same code, and
logically same facility.
Changes since v1 of chiptod patches:
- Split hackish ChipTOD<->TFMR/TBST interface into its own patch
On 11/23/23 10:31, Harsh Prateek Bora wrote:
On 11/23/23 14:20, Cédric Le Goater wrote:
On 11/23/23 06:57, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more
On 11/23/23 11:26, Philippe Mathieu-Daudé wrote:
On 23/11/23 09:47, Cédric Le Goater wrote:
On 11/23/23 06:03, Harsh Prateek Bora wrote:
Hi Philippe,
On 11/22/23 16:46, Philippe Mathieu-Daudé wrote:
Hi Harsh,
On 22/11/23 10:28, Harsh Prateek Bora wrote:
Initialize the machine specific
On 11/23/23 11:19, Philippe Mathieu-Daudé wrote:
Hi Cédric,
On 23/11/23 08:33, Cédric Le Goater wrote:
On 11/23/23 07:01, Zhenzhong Duan wrote:
VFIO is not a required subsystem for the pseries machine but it's
force enabled currently. When --without-default-devices is used
to drop some
'pseries-8.2' is 4096
[root@host build]#
Signed-off-by: Harsh Prateek Bora
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ppc/spapr.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index df09aa9d6a..222d926f46 100644
--- a/hw
interpretation.
Signed-off-by: Harsh Prateek Bora
Suggested-by: Cedric Le Goater
One comment below
Reviewed-by: Cédric Le Goater
---
include/hw/ppc/spapr_irq.h | 14 +-
hw/ppc/spapr_irq.c | 6 --
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/include/hw/ppc
On 11/23/23 06:03, Harsh Prateek Bora wrote:
Hi Philippe,
On 11/22/23 16:46, Philippe Mathieu-Daudé wrote:
Hi Harsh,
On 22/11/23 10:28, Harsh Prateek Bora wrote:
Initialize the machine specific max_cpus limit as per the maximum range
of CPU IPIs available. Keeping between 4096 to 8192 will
to hold stub functions of VFIO EEH hooks,
then vfio core could be compiled out.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
Nick,
I will take this patch through the vfio tree if that's OK for you.
---
Based on vfio-next/vfio-8.2
hw/ppc/spapr_pci_vfio_stub.c | 33
On 11/22/23 19:39, Philippe Mathieu-Daudé wrote:
xive2_regs.h only requires declarations from "qemu/bswap.h".
Include it instead of the huge target-specific "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/
Hello Harsh,
Please add to your .git/config file:
[diff]
orderFile = /path/to/qemu/scripts/git.orderfile
On 11/22/23 10:28, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs
On 11/22/23 12:13, Philippe Mathieu-Daudé wrote:
Hi Harsh,
On 22/11/23 10:28, Harsh Prateek Bora wrote:
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which
this.
Reviewed-by: Cédric Le Goater
My R-b was on patch "ppc/pnv: Add a pca9554 I2C device to powernv10-rainier".
Not on the pca9554 model itself.
Thanks,
C.
Signed-off-by: Glenn Miles
---
No change from previous version
MAINTAINERS| 10 +-
hw/misc
On 11/22/23 08:48, Harsh Prateek Bora wrote:
Initialize the machine specific max_cpus limit to a usable limit 4096.
Keeping between 4096 to 8192 will throw IRQ not free error due to XIVE
limitation and keeping beyond 8192 will hit assert in tcg_region_init
or spapr_xive_claim_irq.
The IRQ
The series is pushed on top of vfio-next in the vfio-8.2 tree :
https://github.com/legoater/qemu/commits/vfio-8.2
with a little extra to deal with a PPC build failure.
Thanks Cédric. That's strange I didn't see this failure on my env
which has CONFIG_VFIO_PCI enabled by default for PPC.
Adding Reza.
On 11/21/23 21:03, Miles Glenn wrote:
On Tue, 2023-11-21 at 19:36 +0100, Cédric Le Goater wrote:
On 11/21/23 00:51, Glenn Miles wrote:
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time
On 11/21/23 00:51, Glenn Miles wrote:
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good"
On 11/21/23 17:36, Miles Glenn wrote:
On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
On 11/21/23 02:33, Nicholas Piggin wrote:
On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices
to use the resettable interface so that
all child buses and devices are automatically reset.
Signed-off-by: Glenn Miles
---
Reviewed-by: Cédric Le Goater
Thanks,
C.
No changes from previous version
hw/ppc/pnv_i2c.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion
well
as from writing to the "Immediate Reset" register.
Reviewed-by: Cédric Le Goater
Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Signed-off-by: Glenn Miles
---
No changes from previous version
This patch was merged upstrea
numbering, which
starts at 1. Rather than changing the device tree numbering to start
with 0, the addressing was changed to be based on the existing device
tree numbers minus one.
Reviewed-by: Cédric Le Goater
Fixes: 1ceda19c28a1 ("ppc/pnv: Connect PNV I2C controller to powernv10)
Signe
Card" is present.
Signed-off-by: Glenn Miles
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
Changes from previous version:
- Code moved from pnv_chip_power10_realize to pnv_rainier_i2c_init
hw/misc/Kconfig | 4
hw/misc/meson.build | 1 +
hw/ppc/Kconfig | 1 +
hw
On 11/21/23 17:36, Miles Glenn wrote:
On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
On 11/21/23 02:33, Nicholas Piggin wrote:
On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices
Hello Zhenzhong
On 11/21/23 09:43, Zhenzhong Duan wrote:
Hi,
Thanks all for giving guides and comments on previous series, this is
the remaining part of the iommufd support.
Besides suggested changes in v6, I'd like to highlight two changes
for final review:
1. Instantiate can_be_deleted
starts at 1. Rather than changing the device tree numbering to start
with 0, the addressing was changed to be based on the existing device
tree numbers minus one.
Fixes: 1ceda19c28a1 ("ppc/pnv: Connect PNV I2C controller to powernv10)
Signed-off-by: Glenn Miles
Signed-off-by: Cédric Le Goater
--
the "Immediate Reset" register.
Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Signed-off-by: Glenn Miles
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv_i2c.c | 42 ++
1 file changed, 18 insertions(+), 24 deletions(-)
ssing it")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1941
Signed-off-by: John Platts
Reviewed-by: Richard Henderson
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 12 +-
tests/tcg/ppc64/vsx_f2i_nan.c | 300
tests
ealize time.
Fixes: Coverity CID 1523918
Cc: Glenn Miles
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Glenn Miles
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv_i2c.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc/pnv_i2c.c
index f75e59e
to integer values
Cédric Le Goater (1):
ppc/pnv: Fix potential overflow in I2C model
Glenn Miles (2):
ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses
ppc/pnv: Fix PNV I2C invalid status after reset
John
Hello Zhenzhong,
Below are other gaps I can think of for now:
Gaps:
1. dirty page sync, WIP (Joao)
2. p2p dma not supported yet.
3. fd passing with mdev not support ram discard(vfio-pci) as no way to know it's
a mdev from a fd.
Call the section Caveats maybe?
Got it.
It looks like v7
On 11/21/23 02:33, Nicholas Piggin wrote:
On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Is the plan to have a base powernv10 common to all and then
powernv10-rainier looks like a
ld fit on one line.
The rest looks good.
Reviewed-by: Cédric Le Goater
Thanks,
C.
+}
}
static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
@@ -2285,9 +2309,11 @@ static void pnv_machine_power10_class_init(ObjectClass
*oc, void *data)
static void pnv_machine_p10_
On 11/21/23 00:51, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Signed-off-by: Glenn Miles
---
hw/ppc/pnv.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c
Hello Zhenzhong
On 11/20/23 11:07, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Sent: Monday, November 20, 2023 4:25 PM
Subject: Re: [PATCH v6 01/21] backends/iommufd: Introduce the iommufd object
A similar issue with a fix submitted below, ccing
A similar issue with a fix submitted below, ccing related people.
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg02937.html
It looks the fix will not work for hotplug.
Or below qemu cmdline may help:
"-cpu host,host-phys-bits-limit=39"
don't you have the same issue with legacy VFIO
Nick,
Since I started collecting fixes for 8.2 while you were away, I will
finish this cycle with a last PR next week and let you take over 9.0.
On 11/14/23 20:56, Glenn Miles wrote:
The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C
On 11/14/23 20:56, Glenn Miles wrote:
The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and the SCL/SDA input
level fields.
Fixed this for resets caused by a system reset as well
as from writing to
Well, I was hoping to sweep the pca9554 model under the PowerNV
maintainership (like pca9552 is under the BMC aspeed maintainership).
I did update the PowerNV list to include it, but perhaps that was
presumptuous of me. :-)
Well, you are the person who has the most knowledge on both and
you
On 11/17/23 13:58, Cédric Le Goater wrote:
On 11/17/23 10:35, Zhenzhong Duan wrote:
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
The content looks good but it lacks formatting. Please try to generate
the docs.
Please check my vfio-8.2 branch.
Thanks,
C.
On 11/17/23 14:29, Eric Auger wrote:
Hi Cédric,
On 11/17/23 12:39, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Sent: Friday, November 17, 2023 7:10 PM
Subject: Re: [PATCH v6 01/21] backends/iommufd: Introduce the iommufd object
Hello,
+int
On 11/17/23 10:35, Zhenzhong Duan wrote:
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
The content looks good but it lacks formatting. Please try to generate
the docs.
Thanks,
C.
---
MAINTAINERS| 1 +
docs/devel/index-internals.rst | 1 +
docs
On 11/17/23 12:39, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Sent: Friday, November 17, 2023 7:10 PM
Subject: Re: [PATCH v6 01/21] backends/iommufd: Introduce the iommufd object
Hello,
+int iommufd_backend_map_dma(IOMMUFDBackend *be, uint32_t
Hello,
+int iommufd_backend_map_dma(IOMMUFDBackend *be, uint32_t ioas_id, hwaddr iova,
+ram_addr_t size, void *vaddr, bool readonly)
+{
+int ret, fd = be->fd;
+struct iommu_ioas_map map = {
+.size = sizeof(map),
+.flags =
Hello,
On 11/17/23 02:14, maobibo wrote:
Thomas,
Linux 6.7-rc1 has already released, LoongArch KVM is supported in this version.
LoongArch qemu KVM function depends on linux-headers and I do not know whether
LoongArch qemu KVM can be merged in 8.2 cycle.
It's too late for 8.2. See
On 11/16/23 03:16, Duan, Zhenzhong wrote:
-Original Message-
From: Cédric Le Goater
Sent: Wednesday, November 15, 2023 9:12 PM
Subject: Re: [PATCH 1/4] vfio/pci: Move VFIODevice initializations in
vfio_instance_init
On 11/15/23 09:32, Zhenzhong Duan wrote:
Some of the VFIODevice
Please add bare documentation:
/* Returns 0 on success, or a negative errno. */
+int vfio_device_get_name(VFIODevice *vbasedev, Error **errp);
Will do, I'd like to wait a few days to collect more suggested changes and RB,
Then send all these updates to Cédric in once before he pushes
On 11/15/23 17:37, Miles Glenn wrote:
On Wed, 2023-11-15 at 08:28 +0100, Cédric Le Goater wrote:
On 11/14/23 20:56, Glenn Miles wrote:
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6
well
as from writing to the "Immediate Reset" register.
Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Signed-off-by: Glenn Miles
---
This is 8.2 material.
Reviewed-by: Cédric Le Goater
Thanks,
C.
Changes from v2:
-A
s 8.2 material.
Reviewed-by: Cédric Le Goater
Thanks,
C.
Changes from v2:
- Added Fixes: tag
hw/ppc/pnv.c | 6 --
hw/ppc/pnv_i2c.c | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 645379d5bf..e82e9b30ec 100644
--- a/h
On 11/15/23 09:32, Zhenzhong Duan wrote:
Some of the VFIODevice initializations is in vfio_realize,
move all of them in vfio_instance_init.
No functional change intended.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
hw/vfio/pci.c | 10 ++
1 file changed, 6
On 11/15/23 13:09, Philippe Mathieu-Daudé wrote:
Hi Zhenzhong,
On 14/11/23 11:09, Zhenzhong Duan wrote:
This gives management tools like libvirt a chance to open the vfio
cdev with privilege and pass FD to qemu. This way qemu never needs
to have privilege to open a VFIO or iommu cdev node.
Nick,
On 11/14/23 20:56, Glenn Miles wrote:
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
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