[Qemu-devel] [PATCH v3] build: include sys/sysmacros.h for major() and minor()

, include directly. If you did not intend to use a system-defined macro "minor", you should undefine it after including . [-Werror] *devminor = minor(st.st_rdev); ^~ The additional include allows the build to complete on Fedora 26 (Rawh

Re: [Qemu-devel] [PATCH v2] build: include sys/sysmacros.h for major() and minor()

Hi Eric, On 12/28/2016 11:10 AM, Eric Blake wrote: > On 12/28/2016 08:53 AM, Christopher Covington wrote: >> The definition of the major() and minor() macros are moving within glibc to >> . Include this header to avoid the following sorts of >> build-stopping messages: &g

[Qemu-devel] [PATCH v2] build: include sys/sysmacros.h for major() and minor()

f you did not intend to use a system-defined macro "minor", you should undefine it after including . [-Werror] *devminor = minor(st.st_rdev); ^~ The additional include allows the build to complete on Fedora 26 (Rawhide) with gli

Re: [Qemu-devel] [PATCH kvm-unit-tests v8 03/10] arm/arm64: add some delay routines

On 12/09/2016 07:15 AM, Andrew Jones wrote: > On Fri, Dec 09, 2016 at 11:41:06AM +, Andre Przywara wrote: >> Hi, >> >> On 08/12/16 17:50, Andrew Jones wrote: >>> Allow a thread to wait some specified amount of time. Can >>> specify in cycles, usecs, and msecs. >>> +++ b/lib/arm/asm/delay.h

Re: [Qemu-devel] [kvm-unit-tests PATCH v13 4/4] arm: pmu: Add CPI checking

On 12/01/2016 03:27 PM, Andre Przywara wrote: > Hi, > > On 01/12/16 05:16, Wei Huang wrote: >> From: Christopher Covington <c...@codeaurora.org> >> >> Calculate the numbers of cycles per instruction (CPI) implied by ARM >> PMU cycle counter values. The c

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

On 11/16/2016 11:25 AM, Andrew Jones wrote: > On Wed, Nov 16, 2016 at 11:08:42AM -0500, Christopher Covington wrote: >> On 11/16/2016 08:01 AM, Andrew Jones wrote: >>> On Tue, Nov 15, 2016 at 04:50:53PM -0600, Wei Huang wrote: >>>> >>>> >>>&g

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

On 11/16/2016 08:01 AM, Andrew Jones wrote: > On Tue, Nov 15, 2016 at 04:50:53PM -0600, Wei Huang wrote: >> >> >> On 11/14/2016 09:12 AM, Christopher Covington wrote: >>> Hi Drew, Wei, >>> >>> On 11/14/2016 05:05 AM, Andrew Jones wrote: >>

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

Hi Drew, Wei, On 11/14/2016 05:05 AM, Andrew Jones wrote: > On Fri, Nov 11, 2016 at 01:55:49PM -0600, Wei Huang wrote: >> >> >> On 11/11/2016 01:43 AM, Andrew Jones wrote: >>> On Tue, Nov 08, 2016 at 12:17:14PM -0600, Wei Huang wrote: >>>> From:

Re: [Qemu-devel] [kvm-unit-tests PATCHv6 2/3] arm: pmu: Check cycle count increases

Hi Wei, On 10/12/2016 11:49 AM, Wei Huang wrote: > On 10/11/2016 01:40 PM, Christopher Covington wrote: >> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, >> even for the smallest delta of two subsequent reads. >> >> Signed-off-by: Christopher Cov

[Qemu-devel] [kvm-unit-tests PATCHv6 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 103 +- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 4

[Qemu-devel] [kvm-unit-tests PATCHv6 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- ar

[Qemu-devel] [kvm-unit-tests PATCHv6 1/3] arm: Add PMU test

-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- arm/Makefile.common | 3 +- arm/pmu.c | 82 + arm/unittests.cfg | 14 + 3 files changed, 98 insertions(+), 1 deletio

Re: [Qemu-devel] [PATCH] hw/intc/arm_gic_kvm: Fix build on aarch64

On 10/11/2016 12:43 PM, Peter Maydell wrote: > On 11 October 2016 at 17:32, Christopher Covington <c...@codeaurora.org> > wrote: >> Remove unused debugging code to fix native building on aarch64. Without >> this change, the following -Werr output inhibits make from com

[Qemu-devel] [PATCH] hw/intc/arm_gic_kvm: Fix build on aarch64

; ^ cc1: all warnings being treated as errors qemu/rules.mak:60: recipe for target 'hw/intc/arm_gic_kvm.o' failed make[1]: *** [hw/intc/arm_gic_kvm.o] Error 1 Makefile:205: recipe for target 'subdir-aarch64-softmmu' failed Signed-off-by: Christopher Covington &l

[Qemu-devel] [RFC] Use cpu_get_icount as cpu_get_host_ticks fallback

The previous increment-on-read fallback didn't increment fast enough for some versions of grub. https://bugs.launchpad.net/qemu-linaro/+bug/893208 Signed-off-by: Christopher Covington <c...@codeaurora.org> --- I unfortunately don't have the opportunity to fully test this right now, b

Re: [Qemu-devel] [Qemu-arm] [PATCH] linux-user: arm: Remove ARM_cpsr and similar #defines

On 03/03/2016 07:18 AM, Peter Maydell wrote: > Typoed qemu-devel email address again, sorry. I must figure out a > way to automate "cc the usual suspects"... git send-email ... \ --cc-cmd='scripts/get_maintainer.pl --norolestats' \ ... Cheers, Cov -- Qualcomm Innovation Center, Inc.

Re: [Qemu-devel] [Qemu-arm] [PATCH] linux-user: arm: Remove ARM_cpsr and similar #defines

very useful (it's >> not clear that they're intended for use with the target_pt_regs struct >> rather than (say) the CPUARMState structure) and we only use them in one >> function in elfload.c anyway. So just remove the #defines and directly >> access regs->uregs[]. >&g

[Qemu-devel] Build breakage: error: "ARM_cpsr" redefined

> Date: Tue Mar 1 15:54:03 2016 + === Thanks, Christopher Covington -- Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

[Qemu-devel] [PATCH] Rename cpu_get_icount_{locked,biased}

The function does not provide locking but rather adds a bias value. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- cpus.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cpus.c b/cpus.c index 898426c..50403c4 100644 --- a/cpus.c +++ b/cpus.c @@

Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers

On 02/09/2016 12:19 PM, Peter Maydell wrote: > On 6 February 2016 at 00:55, Alistair Francis > wrote: >> Signed-off-by: Aaron Lindsay >> Signed-off-by: Alistair Francis >> Tested-by: Nathan Rossi

Re: [Qemu-devel] [RFC 09/14] Implement remaining PMU functionality

Hi Alistair, On 02/02/2016 04:22 PM, Alistair Francis wrote: > On Wed, Aug 5, 2015 at 9:51 AM, Christopher Covington > <c...@codeaurora.org> wrote: >> This adds logic to increment PMEVCNTR's based on different event inputs, >> implements all remaining CP registers, a

Re: [Qemu-devel] [PATCH RFC V5 0/9] Implement GIC-500 from GICv3 family for arm64

lanning on another revision of this patchset? Are there any things you would like help with? Peter, Do you have any thoughts about what is essential and what isn't for a first wave of TCG GICv3 patches to be mergeable? Thanks, Christopher Covington -- Qualcomm Innovation Center, Inc. Qualcomm

Re: [Qemu-devel] [RFC v1 0/2] Add a generic loader

Hi Alistair, On 01/15/2016 07:19 PM, Alistair Francis wrote: > This work is based on the original work by Li Guang with extra > features added by Peter C. > > The idea of this loader is to allow the user to load multiple images > or values into QEMU at startup. > I have tested this on ARM and

Re: [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

On 11/10/2015 09:05 PM, Andrew Jones wrote: > On Mon, Nov 02, 2015 at 09:58:14AM -0600, Andrew Jones wrote: >> On Fri, Oct 30, 2015 at 03:32:43PM -0400, Christopher Covington wrote: >>> Hi Drew, >>> >>> On 10/30/2015 09:00 AM, Andrew Jones wrote: >>&

Re: [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

Hi Drew, On 10/30/2015 09:00 AM, Andrew Jones wrote: > On Wed, Oct 28, 2015 at 03:12:55PM -0400, Christopher Covington wrote: >> Calculate the numbers of cycles per instruction (CPI) implied by ARM >> PMU cycle counter values. The code includes a strict checking facil

[Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 103 +- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 4

[Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- ar

[Qemu-devel] [kvm-unit-tests PATCHv6] ARM PMU tests

inline assembly justification comments uniform. * Check argc properly. Thanks, Christopher Covington

[Qemu-devel] [kvm-unit-tests PATCHv5 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- arm/pmu.c

[Qemu-devel] [kvm-unit-tests PATCHv5 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- arm/pmu.c

[Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 105 +- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index c

[Qemu-devel] [kvm-unit-tests PATCHv5] ARM PMU tests

Changes from v4: * Add Drew's Reviewed-by to first patch. * Explain use of 32-bit cycle count values in AArch32. * Zero-initialize pmu_data struct before use in check_cycles_increase and check_cpi. While the insistence on not using memset is entirely my own vanity, I blame the funny syntax on

Re: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

On 10/26/2015 11:58 AM, Andrew Jones wrote: > On Mon, Oct 26, 2015 at 11:38:49AM -0400, Christopher Covington wrote: >> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, >> even for the smallest delta of two subsequent reads. >> >> Signed-off-b

[Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 60 1 file changed, 60 inse

Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking

supported by the in-line assembly code. >> The > > Not all odd counts, right? But rather all multiples of 3? IIUC this is because > the loop is two instructions (sub + branch), and then the clearing of the pmcr > register counts as the 3rd? Clearing the PMCR doesn't happen as part of the loop, but as part of the loop exit or epilogue. total_instrs = iteration_count * loop_instrs + eipilogue_instrs total_instrs = iteration_count * 2 + 1 Thanks, Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

On 10/13/2015 04:53 PM, Peter Maydell wrote: > On 24 September 2015 at 20:43, Christopher Covington <c...@codeaurora.org> > wrote: >> cpu_get_ticks() provides a common interface across targets for >> calculating CPU cycles. Using this fixes PMCCNTR reads when -icount >

[Qemu-devel] [kvm-unit-tests PATCHv4 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c| 82 arm/unittes

[Qemu-devel] [kvm-unit-tests PATCHv4 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 54 ++ 1 file changed, 54 insertions(+)

[Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 91 ++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index a

[Qemu-devel] [kvm-unit-tests PATCHv4] ARM PMU tests

Changes from v3 in response to Drew's suggestions: * Improved pmu_data / PMCR fields and usage * Straightened out awkward conditionals * Added 32-bit support * Styling enhancements * Deferred -icount testing to later patch

[Qemu-devel] [kvm-unit-tests PATCHv3 3/3] arm: pmu: Add CPI checking

Check the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. Check that in -icount mode these strictly match the specified rate. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c

[Qemu-devel] [kvm-unit-tests PATCHv3 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 66 + arm/unittests.cfg

[Qemu-devel] [kvm-unit-tests PATCHv3 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 29 + 1 file changed, 29 insertions(+) diff --git a/arm/pmu.c

[Qemu-devel] [kvm-unit-tests PATCHv3] ARM PMU tests

Changes from v2: * Explicit test for monotonically increasing cycle count * Tests now pass or fail * Tests broken into functions * Tests/functions broken into separate patches in series * Style improvements as suggested by Wei Huang and Linux checkpatch.pl * Spelling and comment improvements

Re: [Qemu-devel] Enabling PMU in qemu arm64

On 10/01/2015 03:32 PM, Pranith Kumar wrote: > On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington > <c...@codeaurora.org> wrote: >> >> Are you using KVM or TCG (are you running on an x86 host or an arm64 host)? > > I am using TCG, aarch64-softmmu on x86 host. &

Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

On 09/29/2015 10:07 AM, Christopher Covington wrote: > On 09/28/2015 06:05 PM, Alistair Francis wrote: >> On Thu, Sep 24, 2015 at 12:43 PM, Christopher Covington >> <c...@codeaurora.org> wrote: >>> cpu_get_ticks() provides a common interface across targets for >

[Qemu-devel] [kvm-unit-tests PATCHv2] arm: Add PMU test

when using -icount. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 89 + arm/unittests.cfg | 11 ++ config/config-arm64.mak | 4 ++- 3 files changed, 103 insertions(+), 1 deletion(-) creat

Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

On 10/02/2015 01:25 PM, Peter Crosthwaite wrote: > On Fri, Oct 2, 2015 at 9:56 AM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 2 October 2015 at 17:44, Christopher Covington <c...@codeaurora.org> >> wrote: >>> I've sent out the CPI test

Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

On 10/02/2015 03:56 PM, Peter Crosthwaite wrote: > On Fri, Oct 2, 2015 at 12:25 PM, Christopher Covington > <c...@codeaurora.org> wrote: >> On 10/02/2015 01:25 PM, Peter Crosthwaite wrote: >>> On Fri, Oct 2, 2015 at 9:56 AM, Peter Maydell <peter.mayd...@linaro.org&

Re: [Qemu-devel] Enabling PMU in qemu arm64

hen not using -icount) and code with known length in instructions; B) CPU frequency using PMCCNTR_EL0 and CNTVCT_EL0; and C) instructions event in the PMU for code with known length in instructions If you're using KVM, I think Shannon Zhao at Linaro has been working on that. Christopher Covington

[Qemu-devel] [PATCH] arm: Add PMU test

Beginning with just a read of the control register, add plumbing for testing the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c| 31 +++ arm/unittests.cfg| 5 +

[Qemu-devel] [PATCHv2] arm: Fail on unknown subtest

Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/selftest.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arm/selftest.c b/arm/selftest.c index fc9ec60..f4a5030 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -376,6 +376,9 @@ int main(int argc, char

[Qemu-devel] [PATCH] kvm-unit-tests: arm: Fail on unknown subtest

Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/selftest.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arm/selftest.c b/arm/selftest.c index fc9ec60..aa16a91 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -376,6 +376,8 @@ int main(int argc, char

Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

On 09/28/2015 06:05 PM, Alistair Francis wrote: > On Thu, Sep 24, 2015 at 12:43 PM, Christopher Covington > <c...@codeaurora.org> wrote: >> cpu_get_ticks() provides a common interface across targets for >> calculating CPU cycles. Using this fixes PMCCNTR reads when

[Qemu-devel] [PATCH] s/cpu_get_real_ticks/cpu_get_host_ticks/

This should help clarify the purpose of the function that returns the host system's CPU cycle count. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- bsd-user/main.c | 2 +- cpus.c| 6 +++--- hw/intc/xics.c| 2 +- hw/ppc

[Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure

cpu_get_ticks() provides a common interface across targets for calculating CPU cycles. Using this fixes PMCCNTR reads when -icount is specified (previously a non-increasing value was returned). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- target-arm/helper.c | 9 +++---

Re: [Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

On 09/24/2015 02:03 PM, Christopher Covington wrote: > Hi, > > On 09/17/2015 01:38 PM, Shlomo Pongratz wrote: >> From: Pavel Fedin <p.fe...@samsung.com> >> >> I would like to offer this, slightly improved implementation. The key thing >> is a new >>

Re: [Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

; > +if (type == 3) { > +/* Connect GIC to CPU */ > +for (i = 0; i < smp_cpus; i++) { > +CPUState *cpu = qemu_get_cpu(i); > +aatch64_registers_with_opaque_set(OBJECT(cpu), (void *)gicdev); Typo--should be "aarch64". With that

[Qemu-devel] [PATCHv2] target-arm: Use physical addresses for ldrex/strex

As different virtual addresses may end up aliasing by pointing to the same physical address, modify load- and store-exclusive to use physical addresses with the exclusive monitor. Written by Derek Hower. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- target-arm/helper

Re: [Qemu-devel] QEMU+Aarch64: in_asm log skips instructions of loop-programs

On 09/18/2015 04:15 AM, Sergey Smolov wrote: > Hi Christopher, > > 18.09.2015 02:02, Christopher Covington пишет: >> Hi Sergey, >> >> On 09/04/2015 12:38 PM, Sergey Smolov wrote: >>>> 03.09.2015 19:35, Peter Maydell пишет: >>>>> On 3 September

Re: [Qemu-devel] QEMU+Aarch64: in_asm log skips instructions of loop-programs

ssembled forms of instructions and > executed TBs. > Now my logger does "loop unrolling" successfully. This sounds like it solves the same issue as -d nochain but in what's probably a more time efficient manner. Are you able to share your implementation? Thanks, Christopher Covington -- Qua

Re: [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction

ing sure the user knows what files their guest is gaining access to would be to have a semihosting path prefix option. That way access could be allowed nowhere; clearly allow everywhere (/); or clearly be restricted to, and relative to, a certain sysroot directory (/home/user/my-sysroot). Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [Qemu-devel] add multiple times opening support to a virtserialport

? http://events.linuxfoundation.org/sites/events/files/slides/stefanha-kvm-forum-2015.pdf (Video doesn't seem to be up yet, but should probably be available eventually at the following link) https://www.youtube.com/playlist?list=PLW3ep1uCIRfyLNSu708gWG7uvqlolk0ep Regards, Christopher Covington

Re: [Qemu-devel] [PATCH v2 0/3] SysFS driver for QEMU fw_cfg device

such a tool for AArch64. (On AArch32 upstream QEMU disallows semihosting from userspace.) Before I had 9P on all the simulators I regularly ran, I used a semihosting based angel-load tool. Regards, Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc

Re: [Qemu-devel] [PATCH 0/9] target-arm: Implement A64 semihosting

Hi Peter, On 08/13/2015 12:35 PM, Peter Maydell wrote: This patch series implements support for semihosting for the 64-bit ARM instruction set. It owes a significant debt to the patches sent earlier by Christopher Covington (and with code written by Derek Hower). However, it is a full from

Re: [Qemu-devel] ARM softmmu breakpoint misbehavior

the alleged internal debug exception in the trace. Peter recently posted a series related to semihosting (target-arm: Implement A64 semihosting) that I think touches some of this code, if you haven't seen that already. Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation

Re: [Qemu-devel] [PATCH 6/9] target-arm/arm-semi.c: Support widening APIs to 64 bits

is a 64-bit value in X0 Implement the necessary handling for this widening. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Christopher Covington christopher.coving...@linaro.org

Re: [Qemu-devel] [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction

-by: Christopher Covington christopher.coving...@linaro.org

Re: [Qemu-devel] [PATCH 4/9] target-arm/arm-semi.c: Factor out repeated 'return env-regs[0]'

in the FIXME comment is not introduced by this commit, but was already present. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Christopher Covington christopher.coving...@linaro.org

Re: [Qemu-devel] [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call

Maydell peter.mayd...@linaro.org Reviewed-by: Christopher Covington christopher.coving...@linaro.org

[Qemu-devel] [RFC 1/2] icount: Print instruction count on exit

the instruction count to guest/target software through interfaces such as an emulated Performance Monitors Unit. Signed-off-by: Christopher Covington c...@codeaurora.org --- cpus.c | 9 + 1 file changed, 9 insertions(+) diff --git a/cpus.c b/cpus.c index a822ce3..b0bc8ec 100644 --- a/cpus.c

[Qemu-devel] [RFC 2/2] qemu-log: Add in_icount option

software through interfaces such as an emulated Performance Monitors Unit. * Basic Block used loosely; single-entry not guaranteed. Signed-off-by: Christopher Covington c...@codeaurora.org --- include/qemu/log.h | 1 + qemu-log.c | 2 ++ target-arm/translate-a64.c | 4

[Qemu-devel] RFC: Instruction Counting Debug Facilities

is the kind of person who would want to run with -icount shift=n set. Perhaps there's a statistics or verbose option that would be more appropriate to key off of. Additionally printing MIPS would be even neater, but I leave that for later. Thanks, Christopher Covington -- Qualcomm Innovation Center

Re: [Qemu-devel] [PATCH v4 07/11] qemu-log: new option -dfilter to limit output

is to filter based on mode (CurrentEL on AArch64) and PID (CONTEXTIDR on AArch64). Do you foresee any problems with adding such filters? Thanks, Christopher Covington v2 - More clean-ups to the documentation v3 - re-base - use GArray instead of GList to avoid cache bouncing

Re: [Qemu-devel] [PATCH v4 05/11] qemu-log: Improve the exec TB execution logging

0x7f38787cb1c0 [800c] Taking exception 11 [Hypervisor Call] ...from EL1 ...with ESR 0x5a00 Thanks, Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [Qemu-devel] Logging number of translated instructions per basic block

On 08/05/2015 01:11 PM, Christopher Covington wrote: Hi Anthony, On 07/28/2015 05:20 PM, Anthony Carno wrote: Hi there, As the subject of my email suggests, is there a way to log the number of translated instructions per basic block? I've dug into the debug code a bit (specifically

Re: [Qemu-devel] [RFC 01/14] Make unknown semihosting calls non-fatal

Hi Alex, Thanks for taking a look. On 08/06/2015 05:11 AM, Alex Bennée wrote: Christopher Covington c...@codeaurora.org writes: Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/arm-semi.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git

[Qemu-devel] [RFC 10/14] bbvec: Move mode/PID change detection to register writes

This should speed up basic block detection since these were previously being checked for on each basic block / instruction. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/cpu.h | 13 + target-arm/helper-a64.c| 2

[Qemu-devel] [RFC 12/14] bbvec: Detect mode changes after uncached_cpsr update

The previous code checked for the mode change before the new mode was written to env-uncached_cpsr, which unfortunately made the bbvec output look reasonable for small tests. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/helper.c | 6 +++--- 1

[Qemu-devel] [RFC 07/14] Add PMU to ARM virt platform

This reserves one PPI (private peripheral interrupt) for the PMU and creates a corresponding entry in the device tree. Writteb by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- hw/arm/virt.c| 21 + target-arm/cpu-qom.h | 4 ++-- target

[Qemu-devel] [RFC 06/14] Added support for block profiling for AArch32 and Aarch64

, ensuring all block vector files are closed and the block stats are printed to stdout when QEMU exits. Written by Gideon Billings and Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- Makefile.objs | 1 + bbv_profiler.c | 77 +++ bbv_profiler.h

[Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions

This is necessary because we need a way to differentiate between instructions executed in a PID by the benchmark we care about and those executed by CRIU. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- bbv_profiler.c | 15

[Qemu-devel] [RFC 14/14] bbvec: Properly detect conditional thumb2 branching instructions

the call to disas_neon_ls_insn() altogether is safe. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/translate.c | 264 - 1 file changed, 261 insertions(+), 3 deletions(-) diff --git a/target-arm

Re: [Qemu-devel] Logging number of translated instructions per basic block

a starting point. Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

[Qemu-devel] [RFC 02/14] Added semihosting support for A64 in full-system mode

This is for full-system only; not implemented in user mode Written by Derek Hower. Signed-off-by: Christopher Covington c...@codeaurora.org --- include/exec/softmmu-semi.h | 21 ++- target-arm/arm-semi.c | 142 target-arm/cpu.h

[Qemu-devel] [RFC 08/14] Add instruction-counting infrastructure to target-arm

This (partially) divorces counting instructions from basic block collection so instructions can be counted without the bbv plugin being enabled. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- include/exec/cpu-defs.h| 2 ++ target-arm/helper.c

[Qemu-devel] [RFC 01/14] Make unknown semihosting calls non-fatal

Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/arm-semi.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index a8b83e6..bcc70ec 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c

[Qemu-devel] [RFC 09/14] Implement remaining PMU functionality

This adds logic to increment PMEVCNTR's based on different event inputs, implements all remaining CP registers, and triggers an interrupt on event overflow. Written by Aaron Lindsay. Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/cpu-qom.h | 2 + target-arm/cpu.c

[Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU.

The icount setting specifies how far to shift the instruction count as a ratio of ns to tie system time to instruction count. Allow a negative value (i.e. a right shift instead of a left shift) to be used. Written by Pat Galizia. Signed-off-by: Christopher Covington c...@codeaurora.org

[Qemu-devel] [RFC 03/14] Fix makefile

Fixes https://bugs.launchpad.net/qemu/+bug/1319493/ Signed-off-by: Christopher Covington c...@codeaurora.org --- Makefile | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 93af871..fcc6314 100644 --- a/Makefile +++ b/Makefile @@ -408,7 +408,11

[Qemu-devel] [RFC 04/14] Modify load exclusive/store exclusive to use physical addresses with the monitor

Written by Derek Hower. Signed-off-by: Christopher Covington c...@codeaurora.org --- target-arm/helper-a64.h| 2 ++ target-arm/helper.c| 22 ++ target-arm/translate-a64.c | 25 +++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff

[Qemu-devel] [RFC 05/14] Fixed TLB invalidate ops.

Prior to this patch, QEMU was only invalidating the TLB for the local processor on a TLB flush event, causing unstable behavoir in smp mode. This patch corrects the behavoir so that all TLBs are invalidated across the system. Written by Derek Hower. Signed-off-by: Christopher Covington c

[Qemu-devel] RFC: ARM Semihosting, PMU, and BBV Changes

SimPoint algorithm [1] on the collected block vectors and dumping application level checkpoints using CRIU [2] in a second pass. Thanks, Christopher Covington 1. http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.58.4012 2. http://criu.org/Main_Page

Re: [Qemu-devel] Using the one disk image file on 2 virtual machines at the same time

On 07/29/2015 01:46 PM, John Snow wrote: On 07/29/2015 01:29 PM, Manjong Han wrote: Thanks, Stefan. 2015-07-29 17:46 GMT+09:00 Stefan Hajnoczi stefa...@gmail.com: You should probably use qcow2 backing files instead: 10G.qcow2 -- vm001.qcow2 ^-- vm002.qcow2 The command

Re: [Qemu-devel] [RFC] Towards an Heterogeneous QEMU

compare to current efforts for multithreaded TCG? Do you anticipate needing a mechanism to keep processes roughly in sync with each other, so that one doesn't unrealistically get way far ahead of the rest? Thanks, Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation

Re: [Qemu-devel] User space vs kernel space instructions distribution.

On 07/14/2015 04:45 AM, Peter Maydell wrote: On 14 July 2015 at 09:32, Shlomo Pongratz shlomopongr...@gmail.com wrote: Hi, I'm running aarm64 QEMU and I'm counting the number of instructions which belong to user space vs kernel space. My measurements shows that 99 percent of instructions are

Re: [Qemu-devel] [PATCH pic32 2/7] Stop simulation when processor is suspended forever by WAIT instruction with interrupts disabled.

On 06/30/2015 09:57 PM, Serge Vakulenko wrote: Hi Peter and Leon, With a bit of thinking, I agree, that the question of session termination on WAIT instruction is quite complicated in case of multi-core system, background i/o activity, mipsR6 core etc. So I'm going to find another solution

Re: [Qemu-devel] Monitoring write to memory

On 07/01/2015 08:23 AM, Jun Koi wrote: Hello, I am trying to monitor all the memory writing events inside Qemu by instrumenting tcg_gen_qemu_st8, tcg_gen_qemu_st16, tcg_gen_qemu_st32, tcg_gen_qemu_st64, as followings: // in tcg-op.h void helper_checkmem(int64_t data, int64_t

Re: [Qemu-devel] Asking about QEMU's process in memory address space of host

On 07/08/2015 07:14 AM, Piyawath Boukom wrote: Dear peoples in mailing-list, My name is Piyawath Boukom, I’m a student from Tokyo Tech. I hope you can enlighten me about this. Below are things that those I would like to perform. - I want to identify where guest kernel lives in QEMU’s

Re: [Qemu-devel] [PULL 1/8] target-sh4: use bit number for SR constants

Hi Aurelien, On 06/01/2015 05:29 PM, Aurelien Jarno wrote: Use the bit number for SR constants instead of using a bit mask. This make possible to also use the constants for shifts. Reviewed-by: Richard Henderson r...@twiddle.net Signed-off-by: Aurelien Jarno aurel...@aurel32.net ---

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