Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

rs1); > > float32 frs2 = check_nanbox_s(rs2); > > -return nanbox_s(float32_minnum(frs1, frs2, >fp_status)); > > +return nanbox_s(float32_minnum_noprop(frs1, frs2, >fp_status)); > > } > > Don't you need to conditionalize behaviour on the isa revision? > > I will pick the right API based on CPU privilege spec version. Thanks, Frank Chang > > r~ >

Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

ok. > > > +MINMAX_1(type, maxnum_noprop, minmax_isnum | minmax_snan_noprop) \ > > +MINMAX_1(type, minnum_noprop, minmax_ismin | minmax_isnum | \ > > + minmax_snan_noprop)\ > > But here, you have been given names

Re: [PATCH v8 00/78] support vector extension v1.0

於 2021年10月15日 週五 下午3:48寫道： > From: Frank Chang > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > RVV v1.0 spec is now fronzen for public review: > https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 > > The port is available here: >

[PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 + target/riscv/vector_helper.c| 21 + 4 files

[PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 + 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d7c6bc9af26

[PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv

[PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/csr.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 127393eb956..9f51626a3d8 100644 --- a/target/riscv/csr.c +++ b

[PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first

[PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 4 ++-- 4 files changed, 8 insertions(+), 8 deletions

[PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c| 205

[PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-

[PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction

From: Frank Chang Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv

[PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment

From: Frank Chang Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index

[PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 + 3 files changed, 187 insertions(+) diff --git

[PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 + target/riscv/insn32.decode

[PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 11 ++-- target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/csr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f51626a3d8..3929abb112a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -224,7 +224,8

[PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang -- --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target

[PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check

[PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32

[PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 22 - target/riscv/insn32.decode | 15 --- target/riscv/insn_trans/trans_rvv.c.inc | 59 + target/riscv/vector_helper.c| 45

[PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/

[PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 +++ target/riscv

[PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git

[PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 5 + target/riscv/helper

[PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a3f1101cd63..7548b71efdb 100644 --- a/target/riscv

[PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target

[PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 277a5e4120a..71d7b1e8796 100644 --- a/target/riscv

[PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions

[PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 +++--- target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvv.c.inc | 42 - target/riscv

[PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++--- target

[PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index dd15010c3da

[PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode

[PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 32 + 1 file changed, 22 insertions(+), 10 deletions

[PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 ++-- target/riscv/insn_trans

[PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c| 7 --- 4 files

[PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 43 ++--- target/riscv

[PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 + target/riscv/insn32.decode | 8

[PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files

[PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 ++-- target/riscv/vector_helper.c| 99 ++--- 2 files changed, 80 insertions(+), 51 deletions(-) diff --git a/target/riscv

[PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.c.inc | 68

[PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.c.inc | 25 + 2 files changed, 29 insertions(+) diff --git

[PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 92a0e6fe51e..f61eaf7c6ba

[PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 26 ++--- target/riscv/insn32.decode | 14 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 33 +++ target/riscv

[PATCH 23/76] target/riscv: rvv-1.0: amo operations

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 99 +++--- target/riscv/insn32.decode | 58 -- target/riscv/insn_trans/trans_rvv.c.inc | 230 ++- target/riscv/vector_helper.c

[PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 38 - target/riscv/internals.h| 5

[PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files

[PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 67 +++ target/riscv/insn32.decode | 21 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 110 +--- target/riscv

[PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 43

[PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7d8441d1f21..92a0e6fe51e

[PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.c.inc | 33 --- target

[PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 8 1 file changed, 4

[PATCH 20/76] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 67 target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.c.inc | 203 target/riscv/vector_helper.c

[PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3ac5162aeb7..ab274dcde12 100644 --- a/target/riscv

[PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 8 1 file changed, 4

[PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target

[PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(+), 8 deletions(-) diff --git

[PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 64 +++-- target/riscv/vector_helper.c| 14 +- 2 files changed, 41 insertions(+), 37 deletions(-) diff

[PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 129 +++--- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 227 +++- target/riscv

[PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions

From: Frank Chang Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang --- target/riscv/helper.h | 27 - target/riscv/insn32.decode

[PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv

[PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 6 +++--- 4 files changed

[PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting

[PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW

[PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv

[PATCH 18/76] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 64 +++-- target/riscv/vector_helper.c| 14 +- 2 files changed, 41 insertions(+), 37 deletions(-) diff

[PATCH v8 20/78] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 129 ++-- target/riscv/insn32.decode | 43 ++- target/riscv/insn_trans/trans_rvv.c.inc | 376 target/riscv/vector_helper.c

[PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 ++ target/riscv/insn_trans/trans_rvv.c.inc | 75 + target/riscv/translate.c

[PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b

[PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target

[PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed

[PATCH v8 15/78] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +--- 1 file changed, 507 insertions(+), 208 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 13

[PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

From: Frank Chang TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in commit: c445593, but other TB_FLAGS bits for rvv and rvh were not shift as well so these bits may overlap with each other when rvv is enabled. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 14

[PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 ++- target/riscv/csr.c| 25

[PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v8 00/78] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. RVV v1.0 spec is now fronzen for public review: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8 RVV v1.0 can

[PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4d

[PATCH v2 6/6] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h

[PATCH v2 5/6] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 6 ++ target/riscv/helper.h | 1 + target/riscv/insn32.decode| 1 + target/riscv/insn_trans

[PATCH v2 2/6] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 82 ++ target/riscv/helper.h | 13 +++ target/riscv/insn32.decode| 11 ++ target/riscv

[PATCH v2 3/6] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 67 + target/riscv/helper.h | 12 + target/riscv/insn32.decode| 19 ++ target/riscv/insn_trans

[PATCH v2 1/6] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 1 + target/riscv/insn32.decode| 4 ++ target/riscv/insn_trans

[PATCH v2 0/6] target/riscv: support Zfh, Zfhmin extension v0.1

From: Frank Chang Zfh - Half width floating point Zfhmin - Subset of half width floating point Zfh, Zfhmin v0.1 is now in public review period and is required by RVV extension: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ Zfh, Zfhmin can be enabled

[PATCH v2 4/6] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 21 + target/riscv/helper.h | 3 ++ target/riscv/insn32.decode| 3 ++ target/riscv/insn_trans

[PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang

[PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

From: Chih-Min Chao The sNaN propagation behavior has been changed since cd20cee7 in https://github.com/riscv/riscv-isa-manual Signed-off-by: Chih-Min Chao --- target/riscv/fpu_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/fpu_helper.c

[PATCH RESEND v3 0/2] add APIs to handle alternative sNaN propagation for fmax/fmin

From: Frank Chang In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag are removed and replaced with minimum, minimumNumber, maximum and maximumNumber. minimumNumber/maximumNumber behavior for SNaN is changed to: * If both operands are NaNs, a QNaN is returned. * If either operand

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax

axnum_noprop(frs1, frs2, >fp_status); > } > > uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) > -- > 2.25.1 > > > I should add the cover letter for this series of patchset, will resend it. Sorry for the confusion. Regards, Frank Chang

Re: [PATCH v3 1/2] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

n, riscv-spec-20191213 changes to > alternative) > > Signed-off-by: Chih-Min Chao > Signed-off-by: Frank Chang > --- > fpu/softfloat-parts.c.inc | 19 +++ > fpu/softfloat.c | 18 +- > include/fpu/softfloat.h | 10 ++

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