Many operands can only decode successfully if the ModR/M byte has the
direct form (i.e. MOD=3). Capture this common aspect by introducing a
special direct-only r/m field operand.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 37 +
1 file changed, 37
insnop_arg_t, insnop_ctxt_t and init, prepare and finalize functions
form the basis of instruction operand decoding. Introduce macros for
defining a generic instruction operand; use cases for operand decoding
will be introduced later.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 28
The either-or operand attempts to decode one operand, and if it fails,
it falls back to a second operand. It is unifying, meaning that
insnop_arg_t of the second operand must be implicitly castable to
insnop_arg_t of the first operand.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 46
This permits the ModR/M byte to be passed raw into the code generator,
effectively allowing to short-circuit the operand decoding mechanism
and do the decoding work manually in the code generator.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 20
1 file changed, 20
Add all the SSE3 instruction entries to sse-opcode.inc.h.
Signed-off-by: Jan Bobek
---
target/i386/sse-opcode.inc.h | 20
1 file changed, 20 insertions(+)
diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h
index efa67b7ce2..0cfe6fbe31 100644
From: Richard Henderson
We can compute cur_eip from values present within DisasContext.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 89 -
1 file changed, 44 insertions(+), 45 deletions(-)
diff --git a/target/i386/translate.c
Introduce a helper function to take care of instruction CPUID checks.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 6296a02991
Introduce code generators required by SSE3 instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index c72138014a..9da3fbb611 100644
TCG temporary operands allocate a 32-bit or 64-bit TCG temporary, and
later automatically free it.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/target/i386/translate.c b/target/i386
Reduce scope of the local variable prefixes to enforce use of prefix
from DisasContext instead.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 113
1 file changed, 57 insertions
Use the translator macros to define instruction translators required
by MMX instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 76c27d0380..4fecb0d240
It turns out it is useful to be able to declare operand name
aliases. Introduce a macro to capture this functionality.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
Similar in spirit to the already present gen_(ld,st)(q,o)_env_A0, it
will prove useful in later commits for smaller-sized vector loads.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target
The variable is_xmm does not change value after assignment, so make
this fact explicit by marking it const.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/i386
It is helpful to introduce aliases for some general gvec operations as
it makes a couple of instruction code generators simpler (added
later).
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target
The old code uses bitshifts and bitwise-and all over the place for
decoding ModR/M fields. Avoid doing that by introducing proper
decoding operands.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 62 +
1 file changed, 62 insertions(+)
diff --git
The variable pc_start is already a member of DisasContext. Remove the
superfluous local variable.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 131
1 file changed, 65 insertions(+), 66 deletions(-)
diff --git
The variable b1 does not change value once assigned. Make this fact
explicit by marking it const.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/i386/translate.c b
This function serves as the point-of-intercept for all newly
implemented instructions. If no new implementation exists, fall back
to gen_sse.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 29 -
1 file changed, 28 insertions
There already is a variable dflag in DisasContext, so reduce the scope
of the local variable dflag to enforce use of the one in DisasContext.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 184
for development only and shall not be
included in the final patch series.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index fdc7cb0054..e9741cd7f7 100644
--- a/target/i386/translate.c
From: Richard Henderson
Treat this the same as we already do for other rex bits.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
From: Richard Henderson
Treat this value the same as we do for rex_b and rex_x.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 85 +
1 file changed, 44 insertions(+), 41 deletions(-)
diff --git a/target/i386/translate.c
The variable aflag is not used in most of disas_insn; make this clear
by explicitly reducing its scope to the block where it is used.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 6 +-
1 file changed, 5 insertions
gvec operations require that all vectors be aligned on 16-byte
boundary; make sure the MM/XMM/YMM/ZMM register file is aligned as
neccessary.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
happy with it for now.
- Reduced the number of various INSN_* (now called OPCODE_*) macro
variants using variadic macros.
- Implemented translation for instructions up to SSE3.
Cheers,
-Jan
References:
1. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg01790.html
Jan Bobek
On 8/13/19 2:00 AM, Richard Henderson wrote:
> On 8/10/19 5:12 AM, Jan Bobek wrote:
>> This header is intended to eventually list all supported instructions
>> along with some useful details (e.g. mnemonics, opcode, operands etc.)
>> It shall be used (along with some preproces
On 8/13/19 2:30 AM, Richard Henderson wrote:
> On 8/10/19 5:12 AM, Jan Bobek wrote:
>> +#define CASES_LEG_NP_0F_W0(opcode) \
>> +case opcode | M_0F | W_0:
>> +#define CASES_LEG_NP_0F_W1(opcode) \
>> +case opcode | M_0F | W_1:
>> +
On 8/13/19 2:07 AM, Richard Henderson wrote:
> On 8/10/19 5:12 AM, Jan Bobek wrote:
>> +#define INSNOP_INIT(opT, init_stmt)\
>> +static int insnop_init(opT)(CPUX86State *env, DisasContext *s, \
>> +int mod
On 8/10/19 7:35 PM, Richard Henderson wrote:
> On 8/9/19 9:12 PM, Jan Bobek wrote:
>> This is a v2 of the patch series posted in [1]. Patches 1-9 are just
>> cleanups; patches 10-39 are something actually interesting. Compared
>> to v1, I started using preprocessor more ex
Introduce code generators required by SSE instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 440
1 file changed, 440 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 12d2ac2eb5..681fa1aee2 100644
Add all the SSE instruction entries to insn.h.
Signed-off-by: Jan Bobek
---
target/i386/insn.h | 158 +
1 file changed, 158 insertions(+)
diff --git a/target/i386/insn.h b/target/i386/insn.h
index 6506ff3137..6e0c75b9f7 100644
--- a/target/i386
Code generators defined using these macros rely on a gvec operation
(i.e. tcg_gen_gvec_*).
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index d721bb5142..36f2579654
.
Signed-off-by: Jan Bobek
---
target/i386/insn.h | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/i386/insn.h b/target/i386/insn.h
index 6e0c75b9f7..b61a4182f6 100644
--- a/target/i386/insn.h
+++ b/target/i386/insn.h
@@ -94,12 +94,14 @@ INSN_WR(movss, LEG(F3
the effective address into the register (as it should). The current
workaround is to declare the memory operand as read (rather than
write); this flaw will be addressed in the next iteration.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 25 +
1 file changed, 25
Instruction "translators" are responsible for decoding and loading
instruction operands, calling the passed-in code generator, and
storing the operands back (if applicable). Once a translator returns,
the instruction has been translated to TCG ops, hence the name.
Signed-off-by:
These address the SSE/AVX-technology register file. Offset of the
entire corresponding register is passed as the operand value,
regardless of operand-size suffix.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 45 +
1 file changed, 45 insertions
Add all MMX instruction entries to insn.h.
Signed-off-by: Jan Bobek
---
target/i386/insn.h | 131 +
1 file changed, 131 insertions(+)
diff --git a/target/i386/insn.h b/target/i386/insn.h
index 4b48c0c0e1..6506ff3137 100644
--- a/target/i386/insn.h
Introduce the immediate-byte operand, which loads a byte from the
instruction stream and passes its value as the operand.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
Use the translator macros to define translators required by SSE
instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 5802b324f0
In this context, "code generators" are functions that receive decoded
instruction operands and emit TCG ops implementing the correct
instruction functionality. Introduce the naming macros first, actual
generator macros will be added later.
Signed-off-by: Jan Bobek
---
target/i386/t
Use the translator macros to define instruction translators required
by MMX instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 36f2579654..3475727380
These address the MMX-technology register file; the corresponding
cpu_env offset is passed as the operand value. Notably, offset of the
entire register is pased at all times, regardless of the operand-size
suffix.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 37
The PINSRW family of instructions have a peculiar second operand:
32-bit general-purpose register file is addressed, but if the operand
is indirect, only 16 bits are loaded from memory. Reflect this by the
RdMw operand.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 6 ++
1 file
Code generators defined using these macros rely on a helper function
(as emitted by gen_helper_*).
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
The MOVHLPS instruction has a special operand: it reads the high
quadword of the source operand (hence it requires the full
double-quadword width), but if the operand is indirect, only 64-bits
are read from memory. Introduce UdqMq operand to address this case.
Signed-off-by: Jan Bobek
This operand attempts to capture the "indirect" or "memory" operand in
a generic way. It significatly reduces the amount code that needs to
be written in order to read operands from memory to temporary storage
and write them back.
Signed-off-by: Jan Bobek
---
target/i
These address the general-purpose register file. The corresponding
32-bit or 64-bit register is passed as the operand value.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 65 +
1 file changed, 65 insertions(+)
diff --git a/target/i386
insnop_t and the init, prepare and finalize functions form the basis
of instruction operand decoding. Introduce macros for defining a
generic instruction operand; use cases for operand decoding will be
introduced later with instruction translators.
Signed-off-by: Jan Bobek
---
target/i386
Define code generators required for MMX instructions.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 114
1 file changed, 114 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 3475727380..aa6fb8b013 100644
This header is intended to eventually list all supported instructions
along with some useful details (e.g. mnemonics, opcode, operands etc.)
It shall be used (along with some preprocessor magic) anytime we need
to automatically generate code for every instruction.
Signed-off-by: Jan Bobek
It is helpful to introduce aliases for some general gvec operations as
it makes a couple of instruction code generators simpler (added
later).
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/translate.c b/target/i386
It turns out it is useful to be able to declare operand name
aliases. Introduce a macro to capture this functionality.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
The variable pc_start is already a member of DisasContext. Remove the
superfluous local variable.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 131
1 file changed, 65 insertions(+), 66 deletions(-)
diff --git a/target/i386/translate.c b/target
Introduce a helper function to take care of instruction CPUID checks.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 03b49411e5
for development only and shall not be
included in the final patch series.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index fbf10b57a2..23550a21d3 100644
--- a/target/i386/translate.c
gvec operations require that all vectors be aligned on 16-byte
boundary; make sure the MM/XMM/YMM/ZMM register file is aligned as
neccessary.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Many operands can only decode successfully if the ModR/M byte has the
direct form (i.e. MOD=3). Capture this common aspect by introducing a
special operand-initialization statement wrapper.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 9 +
1 file changed, 9 insertions(+)
diff
This function serves as the point-of-intercept for all newly
implemented instructions. If no new implementation exists, fall back
to gen_sse.
Note: This changeset is intended for development only and shall not be
included in the final patch series.
Signed-off-by: Jan Bobek
---
target/i386
Reduce scope of the local variable prefixes to enforce use of prefix
from DisasContext instead.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 113
1 file changed, 57 insertions(+), 56 deletions(-)
diff --git a/target/i386/translate.c b/target
There already is a variable dflag in DisasContext, so reduce the scope
of the local variable dflag to enforce use of the one in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 184
1 file changed, 92
The old code uses bitshifts and bitwise-and all over the place for
decoding ModR/M fields. Avoid doing that by introducing proper
decoding macros.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/i386/translate.c b
Similar in spirit to the already present gen_(ld,st)(q,o)_env_A0, it
will prove useful in later commits for smaller-sized vector loads.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/i386/translate.c b/target/i386
From: Richard Henderson
Treat this the same as we already do for other rex bits.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
The variable is_xmm does not change value after assignment, so make
this fact explicit by marking it const.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/i386/translate.c b/target/i386
The variable b1 does not change value once assigned. Make this fact
explicit by marking it const.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
From: Richard Henderson
We can compute cur_eip from values present within DisasContext.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 89 -
1 file changed, 44 insertions(+), 45 deletions(-)
diff --git a/target/i386/translate.c
The variable aflag is not used in most of disas_insn; make this clear
by explicitly reducing its scope to the block where it is used.
Suggested-by: Richard Henderson
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
From: Richard Henderson
Treat this value the same as we do for rex_b and rex_x.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 85 +
1 file changed, 44 insertions(+), 41 deletions(-)
diff --git a/target/i386/translate.c
this time.
References:
1. https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg07041.html
Jan Bobek (36):
target/i386: reduce scope of variable aflag
target/i386: use dflag from DisasContext
target/i386: use prefix from DisasContext
target/i386: use pc_start from DisasContext
On 7/31/19 5:31 PM, Richard Henderson wrote:
> On 7/31/19 1:09 PM, Aleksandar Markovic wrote:
>>
>>
>> On Wed, Jul 31, 2019 at 9:51 PM Richard Henderson
>> > <mailto:richard.hender...@linaro.org>> wrote:
>>
>> On 7/31/19 10:57 AM, Jan Bobek
On 7/31/19 3:35 PM, Richard Henderson wrote:
> On 7/31/19 10:56 AM, Jan Bobek wrote:
>> +#define gen_pand_mm(env, s, modrm) gen_gvec_ld_modrm_mm ((env), (s),
>> (modrm), MO_64, tcg_gen_gvec_and, 0112)
>> +#define gen_pand_xmm(env, s, modrm) gen_gvec_ld_modrm_xmm ((
On 7/31/19 6:47 PM, Richard Henderson wrote:
> I suppose there aren't so many different combinations, but did you consider
> separate callbacks per operand? If you have
>
> typedef unsigned (*gen_offset)(CPUX86State *, DisasContext *, int);
>
> static unsigned offset_Pq(CPUX86State *env,
On 7/31/19 3:08 PM, Richard Henderson wrote:
> On 7/31/19 10:56 AM, Jan Bobek wrote:
>> These help with decoding/loading ModR/M vector operands; the operand's
>> register offset is returned, which is suitable for use with gvec
>> infrastructure.
>>
>> Signed-off
>
> On Wed, Jul 31, 2019 at 7:59 PM Jan Bobek <mailto:jan.bo...@gmail.com>> wrote:
>
> From: Richard Henderson mailto:r...@twiddle.net>>
>
> The variables are already there, we just have to hide the ones
> in disas_insn so that we
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 3 ---
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 12 +++-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/i386
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 4
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 12 +++-
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 13 ---
target/i386/ops_sse_header.h | 8 -
target/i386/translate.c | 66
3 files changed, 60 insertions(+), 27
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 5 -
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 19 +--
3 files changed, 17 insertions(+), 9 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 4
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 19 +--
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 2 --
target/i386/ops_sse_header.h | 1 -
target/i386/translate.c | 12 +++-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 6 --
target/i386/ops_sse_header.h | 5 -
target/i386/translate.c | 33 +
3 files changed, 29 insertions(+), 15 deletions
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 6 --
target/i386/ops_sse_header.h | 5 -
target/i386/translate.c | 33 +
3 files changed, 29 insertions(+), 15 deletions
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 6 --
target/i386/ops_sse_header.h | 4
target/i386/translate.c | 19 +--
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 2 --
target/i386/ops_sse_header.h | 1 -
target/i386/translate.c | 12 +++-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 2 --
target/i386/ops_sse_header.h | 1 -
target/i386/translate.c | 27 +--
3 files changed, 25 insertions(+), 5 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 4
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 19 +--
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 2 --
target/i386/ops_sse_header.h | 1 -
target/i386/translate.c | 26 --
3 files changed, 24 insertions(+), 5 deletions(-)
diff --git
Use the gvec infrastructure to achieve the desired functionality.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 4
target/i386/ops_sse_header.h | 2 --
target/i386/translate.c | 26 --
3 files changed, 24 insertions(+), 8 deletions(-)
diff
with all of the tables, and nothing will follow
the new dispatch switch in gen_sse.
Signed-off-by: Jan Bobek
---
target/i386/ops_sse.h| 2 --
target/i386/ops_sse_header.h | 1 -
target/i386/translate.c | 49 ++--
3 files changed, 47 insertions(+), 5
These help with decoding/loading ModR/M vector operands; the operand's
register offset is returned, which is suitable for use with gvec
infrastructure.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 47 +
1 file changed, 47 insertions(+)
diff
gen_gvec_ld_modrm_* helpers tie together a gen_ld_modrm_* helper and a
particular gvec operation, effectively handling a single instruction.
Signed-off-by: Jan Bobek
---
target/i386/translate.c | 77 +
1 file changed, 77 insertions(+)
diff --git a/target
From: Richard Henderson
Treat this value the same as we do for rex_b and rex_x.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 85 +
1 file changed, 44 insertions(+), 41 deletions(-)
diff --git a/target/i386/translate.c
From: Richard Henderson
The variables are already there, we just have to hide the ones
in disas_insn so that we are forced to use them.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 299
1 file changed, 152 insertions(+), 147
gvec operations require that all vectors be aligned on 16-byte
boundary; make sure the MM/XMM/YMM/ZMM register file is aligned as
neccessary.
Signed-off-by: Jan Bobek
---
target/i386/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386
From: Richard Henderson
We can compute cur_eip from values present within DisasContext.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 89 -
1 file changed, 44 insertions(+), 45 deletions(-)
diff --git a/target/i386/translate.c
into gen_sse; this is obviously intended for development only.
Eventually, everything that follows this switch will be removed,
along with the SSE tables and all that goes along with it.
Cheers,
-Jan
Jan Bobek (18):
target/i386: introduce gen_ld_modrm_* helpers
target/i386: introduce
From: Richard Henderson
Treat this the same as we already do for other rex bits.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
On 7/20/19 8:46 PM, Richard Henderson wrote:
> On 7/11/19 3:33 PM, Jan Bobek wrote:
>> +# VEX.256.0F.WIG 28 /r: VMOVAPS ymm1, ymm2/m256
>> +# VEX.256.0F.WIG 29 /r: VMOVAPS ymm2/m256, ymm1
>> +VMOVAPS AVX2 0010100 d \
>> + !constraints { vex($_, m => 0x0F, l
On 7/20/19 8:04 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, xmm2, xmm3
>> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, m32
>> +# VEX.LIG.F3.0F.WIG 11 /r: VMOVSS xmm1, xmm2, xmm3
>> +# VEX.LIG.F3.0F.
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