As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
---
v2
/FlyGoat/qemu/-/tree/mips-virt
v2: Address review comments
Jiaxun Yang (3):
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
target/mips: Cast offset field of Octeon BBIT to int16_t
target/mips: Disable DSP ASE for Octeon68XX
target/mips/cpu-defs.c.inc| 4 ++--
target/mips/cpu.c
> 2022年10月30日 00:19，Philippe Mathieu-Daudé 写道：
>
> On 29/10/22 21:50, Jiaxun Yang wrote:
>>> 2022年10月29日 18:44，Philippe Mathieu-Daudé 写道：
>>>
>>> On 29/10/22 04:00, Jiaxun Yang wrote:
>>>> As per "Loongson-2F processor user man
> 2022年10月29日 18:44，Philippe Mathieu-Daudé 写道：
>
> On 29/10/22 04:00, Jiaxun Yang wrote:
>> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
>> should is not writeable and hardcoded to 1.
>> Without those bits set, kernel is unable to acce
/FlyGoat/qemu/-/tree/mips-virt
Jiaxun Yang (3):
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
target/mips: Cast offset field of Octeon BBIT to int16_t
target/mips: Disable DSP ASE for Octeon68XX
target/mips/cpu-defs.c.inc | 4 ++--
target/mips/cpu.c | 6
As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
should is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
---
target/mips/cpu.c | 6 ++
1 file
eon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang
-
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/octeon_translate.c | 2 +-
1 file
mu-devel/5a22bbe1-5023-6fc3-a41b-8d72ec2bb...@flygoat.com/
For the series:
Tested-by: Jiaxun Yang
Reviewed-by: Jiaxun Yang
I thought this series was committed in whole.. Just forgot that there are still
something remaining :-)
Thanks
- Jiaxun
>
> *** BLURB HERE ***
>
So we can do decodetree translation for those exts alone.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/loongson_translate.c | 1290 +
target/mips/tcg/meson.build |1 +
target/mips/tcg/translate.c | 1577 --
target/mips/tcg
Introduce register access functions with value extend capability
to prepare for decodetree based translation implmentation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 143 +++-
target/mips/tcg/translate.h | 54 ++
2 files changed
form MIPS's internal
architecture validation tools so they are gureented to be correct.
Note:
There are some checkpatch warning/error on test cases but I'm not going to
touch them as they are generated code.
Thanks.
RFC->v1:
- Tidy up test cases
- Convert TX79 as well
- Jiaxun
Jiaxun Yang
Move MUL family instructions into decodetree.
Also implement RDHWR emulation for user instructions in decodetree
SQ translation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 410 +--
target/mips/tcg/tx79.decode | 14 ++
target/mips/tcg
MXU is treated as an ISA extension for now.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/mxu_translate.c | 98 ++---
target/mips/tcg/translate.c | 13 ++---
2 files changed, 60 insertions(+), 51 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b
Mostly copy paste from translate.c, with some simplification
based on newly introduced register access functions.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/insn_trans/trans_arith.c.inc | 352 +++
target/mips/tcg/legacy.decode| 62
target/mips/tcg
Those cases are delivered from MIPS internal architecture validation
tools.
Signed-off-by: Jiaxun Yang
---
tests/tcg/mips/include/test_utils_32.h| 75 +++
.../tcg/mips/user/isa/mips32/arithmatic/add.c | 99 ++
.../mips/user/isa/mips32/arithmatic/addi.c| 70
-by: Jiaxun Yang
---
hw/mips/boston.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..aa7942bbc0 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -424,7 +424,7 @@ static inline XilinxPCIEHost *
xilinx_pcie_init
Please ignore this mail.
Sorry for the noise.
Thanks.
> 2022年10月24日 15:35，Jiaxun Yang 写道：
>
> Hi all,
>
> Just a small addition to make boston board easier to use :-)
>
> Thanks
> - Jiaxun
>
> Jiaxun Yang (2):
> mips/boston: Support initrd for ELF kernel
&
Hi all,
Just a small addition to make boston board easier to use :-)
Thanks
- Jiaxun
Jiaxun Yang (2):
mips/boston: Support initrd for ELF kernel
hw/mips/boston: Pack fdt in fdt filter
hw/mips/boston.c | 40
1 file changed, 40 insertions
2-bit ABI that passes 64-bit arguments in pairs of GPRs. Fix by
> excluding TARGET_ABI_MIPSN32 from various TARGET_ABI_BITS == 32 checks.
>
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/1238
> Signed-off-by: WANG Xuerui
> Cc: Philippe Mathieu-Daudé
> Cc: Jiaxun Yang
> 2022年9月27日 11:33，Jiaxun Yang 写道：
>
>
>
>> 2022年9月26日 22:35，Philippe Mathieu-Daudé 写道：
>>
>> Hi Jiaxun,
>>
>> On Mon, Sep 26, 2022 at 4:44 PM Jiaxun Yang wrote:
>>>> 2022年9月21日 13:41，Jiaxun Yang 写道：
>>>>
>>
> 2022年9月26日 22:35，Philippe Mathieu-Daudé 写道：
>
> Hi Jiaxun,
>
> On Mon, Sep 26, 2022 at 4:44 PM Jiaxun Yang wrote:
>>> 2022年9月21日 13:41，Jiaxun Yang 写道：
>>>
>>> Hi,
>>>
>>> This is my attempt of converting MIPS translation
> 2022年9月21日 13:41，Jiaxun Yang 写道：
>
> Hi,
>
> This is my attempt of converting MIPS translation code into decodetree.
>
> Currently only MIPS I to MIPS Release 5 arithmatic functions are converted.
> Old decoding functions are perserved in codebase for now du
dealing with
release 6.
Both instruction encoding and test cases are generated form MIPS's internal
architecture validation tools so they are gureented to be correct.
Thanks.
- Jiaxun
Jiaxun Yang (3):
target/mips: Introduce register access helper functions
target/mips: Convert legacy
Mostly copy paste from translate.c, with some simplification
based on newly introduced register access functions.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/insn_trans/trans_arith.c.inc | 352 +++
target/mips/tcg/legacy.decode| 62
target/mips/tcg
Introduce register access functions with value extend capability
to prepare for decodetree based translation implmentation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 143 +++-
target/mips/tcg/translate.h | 54 ++
2 files changed
Those cases are delivered from MIPS internal architecture validation
tools.
Signed-off-by: Jiaxun Yang
---
tests/tcg/mips/include/test_utils_32.h| 75 +++
.../tcg/mips/user/isa/mips32/arithmatic/add.c | 99 ++
.../mips/user/isa/mips32/arithmatic/addi.c| 70
> 2022年8月16日 01:44，Philippe Mathieu-Daudé 写道：
>
> On 13/8/22 18:27, Jiaxun Yang wrote:
>> FDT can be awfully fat after series of modifications in fdt
>> filter. Just pack it up before add to ram.
>> Signed-off-by: Jiaxun Yang
>> ---
>> hw/mips/boston.
Hi all,
Just a small addition to make boston board easier to use :-)
Thanks
- Jiaxun
Jiaxun Yang (2):
mips/boston: Support initrd for ELF kernel
hw/mips/boston: Pack fdt in fdt filter
hw/mips/boston.c | 40
1 file changed, 40 insertions
When loading ELF kernel we can just load out initrd after DTB
and append initrd information to DeviceTree's chosen node.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips
FDT can be awfully fat after series of modifications in fdt
filter. Just pack it up before add to ram.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 5145179951..a40f193f78 100644
--- a/hw/mips
Hi all,
This series properly filled AT_BASE_PLATFORM of MIPS.
There is a checkpatch error about braces after if statement,
I intentionally left it for style consistency.
v2: Commit meesage rewording (philmd)
Thanks.
- Jiaxun
Jiaxun Yang (2):
linux-user: Introduce stubs for ELF
AT_BASE_PLATFORM is a elf auxiliary vector pointing to a string
to pass some architecture information.
See getauxval(3) man-page.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 29 +++--
1 file changed, 27 insertions(+), 2
Match most appropriate base platform string based on insn_flags.
Logic is aligned with aligned with set_isa() from
arch/mips/kernel/cpu-probe.c in Linux kernel.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 31 +++
1 file
AT_BASE_PLATFORM is a elf auxiliary vector pointing to a string
to pass some architecture information.
Signed-off-by: Jiaxun Yang
---
linux-user/elfload.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user
Match most appropriate base platform string based on insn_flags.
Logic is aligned with arch/mips/kernel/cpu-probe.c in Linux kernel.
Signed-off-by: Jiaxun Yang
---
linux-user/elfload.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/linux-user/elfload.c b
Hi all,
This series properly filled AT_BASE_PLATFORM of MIPS.
There is a checkpatch error about braces after if statement,
I intentionally left it for style consistency.
Thanks.
- Jiaxun
Jiaxun Yang (2):
linux-user: Introduce stubs for ELF AT_BASE_PLATFORM
linux-user: Set ELF_BASE_PLATFORM
has some patches applied.
For the whole series:
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Run some sample program with GCC unaligned-access enabled.
Thanks.
r~
Richard Henderson (2):
tcg/mips: Support unaligned access for user-only
tcg/mips: Support unaligned access for sof
在2021年12月26日十二月 上午12:19，Philippe Mathieu-Daudé写道：
> Unfortunately this fails:
>
> $ make run-tcg-tests-mips64el-linux-user
> ...
> Files float_convs.out and tests/tcg/mips64el/float_convs.ref differ
> --- float_convs.out 2021-12-26 01:03:48.585973637 +0100
> +++
在2021年12月2日十二月 下午6:01，Philippe Mathieu-Daudé写道：
> On 12/2/21 11:51, Jiaxun Yang wrote:
>> 在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
>>> On 11/30/21 22:17, Jiaxun Yang wrote:
>>>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>>&
在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
> On 11/30/21 22:17, Jiaxun Yang wrote:
>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>> while sd is illegal on 32 bit CPUs.
>>
>> Replace sd with sw on 32bit CPUs.
>>
>> Fixes: 3ebbf86 ("
load_elf gives negative return in case of error, not zero.
Fixes: 10e3f30 ("hw/mips/boston: Allow loading elf kernel and dtb")
Signed-off-by: Jiaxun Yang
---
For 6.2.
---
hw/mips/boston.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/mips/boston.c
bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
while sd is illegal on 32 bit CPUs.
Replace sd with sw on 32bit CPUs.
Fixes: 3ebbf86 ("hw/mips: Add a bootloader helper")
Signed-off-by: Jiaxun Yang
---
Should be backported to 6.0 onwards.
---
hw/mips/bootloader.c | 6
Two problems caught when I was trying to add CI job for various configurations.
Jiaxun Yang (2):
hw/mips: bootloader: Fix write_ulong
hw/mips/boston: Fix elf_load error detection
hw/mips/bootloader.c | 6 +-
hw/mips/boston.c | 5 +++--
2 files changed, 8 insertions(+), 3 deletions
在 2021/10/28 22:21, Philippe Mathieu-Daudé 写道:
FCR0_HAS2008 flag has been enabled in commit ba5c79f2622
("target-mips: indicate presence of IEEE 754-2008 FPU in
R6/R5+MSA CPUs"), so remove the obsolete FIXME comment.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yan
dummy-convert.
The resulting msa.decode file is quite pleasant to look at, and
the diff-stat is encouraging: number of LoC halved.
Regards,
Thanks that's really helpful!
For the whole series:
Reviewed-by: Jiaxun Yang
Double checked decode tree opcode with manual.
Thanks.
- Jiaxun
son-3A4000 CPU model added in
commit af868995e1b ("target/mips: Add Loongson-3 CPU definition").
Cc: Huacai Chen
Cc: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/cpu-defs.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/ta
在2021年10月15日十月 上午2:06，BALATON Zoltan写道：
> Other functions in the VT82xx chips need to raise ISA interrupts. Keep
> a reference to them in the device state and add via_isa_set_irq() to
> allow setting their state.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
> ---
--
- Jiaxun
在2021年10月15日十月 上午2:06，BALATON Zoltan写道：
> The vt82c686b_realize and vt8231_realize methods are almost identical,
> factor out the common parts to a via_isa_realize function to avoid
> code duplication.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
> ---
&g
在2021年10月15日十月 上午9:49，Philippe Mathieu-Daudé写道：
> On 10/11/21 15:58, Jiaxun Yang wrote:
>> ping?
>>
>> 在 2021/10/2 19:45, Jiaxun Yang 写道:
>>> Jiaxun Yang (3):
>>> hw/mips/boston: Massage memory map information
>>> hw/mips/boston: Allow
ping?
在 2021/10/2 19:45, Jiaxun Yang 写道:
Jiaxun Yang (3):
hw/mips/boston: Massage memory map information
hw/mips/boston: Allow loading elf kernel and dtb
hw/mips/boston: Add FDT generator
hw/mips/boston.c | 348 +++
1 file changed, 320
在 2021/10/4 10:25, Philippe Mathieu-Daudé 写道:
Hardware emulated models don't belong to the TCG MAINTAINERS
section. Move them to a new 'Overall MIPS Machines' section
in the 'MIPS Machines' group.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Thanks.
- Jiaxun
time with the ISA, I agree to maintain
it along with the other MIPS ISA.
For historical notes, see commit a60442eb8 ("Deprecate nanoMIPS ISA").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Probably it's worthy to ask MTK folks if they are willing to maintain QEM
在 2021/10/4 10:25, Philippe Mathieu-Daudé 写道:
MIPS CPS and GIC models are unrelated to the TCG frontend.
Move them as new sections under the 'Devices' group.
Cc: Paul Burton
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Thanks.
- Jiaxun
---
MAINTAINERS | 22
在 2021/10/4 10:25, Philippe Mathieu-Daudé 写道:
The architecture is covered in TCG (frontend and backend)
and hardware models. Add a generic section matching the
'mips' word in patch subjects.
Cc: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Thanks.
- Jiaxun
在 2021/10/3 18:45, Philippe Mathieu-Daudé 写道:
On 10/2/21 20:45, Jiaxun Yang wrote:
Generate FDT on our own if no dtb argument supplied.
Avoid introducing unused device in FDT with user supplied dtb.
Signed-off-by: Jiaxun Yang
--
v2: Address f4bug cmments (Thanks!)
---
hw/mips/boston.c
Reviewed-by: Jiaxun Yang
Just double checked kernel of fuloong2e which uses this bridge chip and
it's supposed to route UHCI IRQ to i8259.
Thanks.
- Jiaxun
---
Maybe bit of a hack but fixes USB interrupts on pegasos2 until
somebody has a better idea. I'm not sure about fuloong2e but the
VT82C686B
Mathieu-Daudé
Reviewed-by: Jiaxun Yang
That seems much more clear!
Thanks.
- Jiaxun
---
target/mips/tcg/translate.c | 68 -
1 file changed, 29 insertions(+), 39 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index
ELF kernel allows us debugging much easier with DWARF symbols.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Use g_autofree
v3: Remove unused kernel_low and uint64_t cast (BALATON)
---
hw/mips/boston.c | 35 +++
1 file changed, 31
Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Fix minor style issue, fix uart map size
---
hw/mips/boston.c | 95
Jiaxun Yang (3):
hw/mips/boston: Massage memory map information
hw/mips/boston: Allow loading elf kernel and dtb
hw/mips/boston: Add FDT generator
hw/mips/boston.c | 348 +++
1 file changed, 320 insertions(+), 28 deletions(-)
--
2.30.2
Generate FDT on our own if no dtb argument supplied.
Avoid introducing unused device in FDT with user supplied dtb.
Signed-off-by: Jiaxun Yang
--
v2: Address f4bug cmments (Thanks!)
---
hw/mips/boston.c | 234 +--
1 file changed, 226 insertions(+), 8
在 2021/9/29 16:36, BALATON Zoltan 写道:
On Wed, 29 Sep 2021, Jiaxun Yang wrote:
ELF kernel allows us debugging much easier with DWARF symbols.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Use g_autofree
---
hw/mips/boston.c | 36
在 2021/9/29 16:32, BALATON Zoltan 写道:
On Wed, 29 Sep 2021, Jiaxun Yang wrote:
Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Fix minor style issue, fix
Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Fix minor style issue, fix uart map size
---
hw/mips/boston.c | 95
Jiaxun Yang (3):
hw/mips/boston: Massage memory map information
hw/mips/boston: Allow loading elf kernel and dtb
hw/mips/boston: Add FDT generator
hw/mips/boston.c | 349 +++
1 file changed, 321 insertions(+), 28 deletions(-)
--
2.30.2
Generate FDT on our own if no dtb argument supplied.
Avoid introducing unused device in FDT with user supplied dtb.
Signed-off-by: Jiaxun Yang
--
v2: Address f4bug cmments (Thanks!)
---
hw/mips/boston.c | 234 +--
1 file changed, 226 insertions(+), 8
ELF kernel allows us debugging much easier with DWARF symbols.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v2: Use g_autofree
---
hw/mips/boston.c | 36
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/mips/boston.c b
在2021年8月19日八月 上午4:19，Richard Henderson写道：
> We can use the routines just added for user-only to emit
> unaligned accesses in softmmu mode too.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Thanks!
> ---
> tcg/mips/tcg
ELF kernel allows us debugging much easier with DWARF symbols.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 38 ++
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index a5746ede65..42b31a1ce4 100644
Generate FDT on our own if no dtb argument supplied.
Avoid introduce unused device in FDT with user supplied dtb.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 238 +--
1 file changed, 228 insertions(+), 10 deletions(-)
diff --git a/hw/mips
Use memmap array to unfiy address of memory map.
That would allow us reuse address information for FDT generation.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 95
1 file changed, 71 insertions(+), 24 deletions(-)
diff --git a/hw/mips
Jiaxun Yang (3):
hw/mips/boston: Massage memory map information
hw/mips/boston: Allow loading elf kernel and dtb
hw/mips/boston: Add FDT generator
hw/mips/boston.c | 351 +++
1 file changed, 323 insertions(+), 28 deletions(-)
--
2.32.0
On Tue, Apr 6, 2021, at 9:06 PM, Alex Bennée wrote:
> Hi,
>
> I was trying to bootstrap a Loongson3 Debian image but ran into some
> roadblocks. Philippe pointed me at:
>
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg768848.html
>
> which gives a bit of detail but elides over
On Tue, Mar 23, 2021, at 9:56 PM, Philippe Mathieu-Daudé wrote:
> Hi Huacai,
>
> We are going to tag QEMU v6.0-rc0 today.
>
> I only have access to a 64-bit MIPS in little-endian to
> test KVM.
>
> Can you test the other configurations please?
> - 32-bit BE
> - 32-bit LE
> - 64-bit BE
+syq
{IP,IPV6}_MULTICAST_IF was not supported.
Signed-off-by: Jiaxun Yang
Reported-by: Yunqiang Su
---
v3: Add missing reported-by.
---
linux-user/syscall.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 389ec09764..77343130b3 100644
=a1515ec7204edca770c07929df8538fcdb03ad46
Signed-off-by: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
v2: Fix up tittle and sphinx format (f4bug)
Lost in the sea of emails :-)
---
docs/system/deprecated.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index
=a1515ec7204edca770c07929df8538fcdb03ad46
Signed-off-by: Jiaxun Yang
---
docs/system/deprecated.rst | 8
1 file changed, 8 insertions(+)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index cfabe69846..a409c65485 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -496,3
On Thu, Mar 11, 2021, at 3:12 AM, Philippe Mathieu-Daudé wrote:
> No need to create a local ISA I/O MemoryRegion, use get_system_io().
>
> This partly reverts commit 5c63bcf7501527b844f61624957bdba254d75bfc.
>
> Signed-off-by: Philippe Mathieu-Daudé
No luck to boot arcboot with current jazz
{IP,IPV6}_MULTICAST_IF was not supported.
Signed-off-by: Jiaxun Yang
---
linux-user/syscall.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 389ec09764..77343130b3 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -2219,6
在 2021/3/5 上午11:35, Jiaxun Yang 写道:
> {IP,IPV6}_MULTICAST_IF was not supported.
>
> Reported-by: Yunqiang Su
> Signed-off-by: Jiaxun Yang
> ---
> linux-user/syscall.c | 4 +
> linux-user/syscall.c.orig | 13305
在 2021/2/20 上午1:38, Philippe Mathieu-Daudé 写道:
Restrit KVM to the following MIPS machines:
- malta
- loongson3-virt
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
hw/mips/loongson3_virt.c | 5 +
hw/mips/malta.c | 5 +
2 files changed, 10 insertions
On Mon, Feb 8, 2021, at 3:39 AM, Thomas Bogendoerfer wrote:
> On Wed, Feb 03, 2021 at 08:52:34PM +0800, Jiaxun Yang wrote:
> >
> >
> > On Wed, Feb 3, 2021, at 8:34 PM, Thomas Bogendoerfer wrote:
> > > Hi,
> > >
> > > Does kvm guest kernel
在 2021/2/2 上午4:04, BALATON Zoltan 写道:
On Sun, 10 Jan 2021, BALATON Zoltan wrote:
On Sun, 10 Jan 2021, Philippe Mathieu-Daudé wrote:
+PCI experts
On 1/10/21 1:43 AM, BALATON Zoltan wrote:
On Sun, 10 Jan 2021, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
在 2021/1/27 下午2:54, Jiaxun Yang 写道:
v2:
A big reconstruction. rewrite helpers with CPU feature and sepreate
changesets.
v3:
respin
ping?
Jiaxun Yang (4):
hw/mips: Add a bootloader helper
hw/mips: Use bl_gen_kernel_jump to generate bootloaders
hw/mips/malta: Use bootloader helper
-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 64e89591abc..14f5b1a0a9c 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -222,7 +222,7
Reviewed-by: Jiaxun Yang
---
target/mips/internal.h | 8
target/mips/tlb_helper.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 34915c275c4..99264b8bf6a 100644
--- a/target/mips/internal.h
, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 21b7d38f11c
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass
MMUAccessType to raise_mmu_exception(). Let the prototype use it
as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, do_translate_address(), passes MMUAccessType
to cpu_mips_translate_address(). Let the prototype use it as
argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, HELPER_LD_ATOMIC(), passes MMUAccessType to
do_translate_address(). Let the prototype use it as argument,
as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
The single caller, mips_cpu_tlb_fill(), passes MMUAccessType
to page_table_walk_refill(). Let the prototype use it as
argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/op_helper.c | 2 +-
target/mips/tlb_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
Remove these confusing and unused definitions.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/cpu.h | 16
1 file changed, 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 22 +-
1 file changed, 9 insertions
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_segctl_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 20 ++--
1 file changed, 10
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
get_seg_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/tlb_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
在 2021/1/28 下午10:41, Philippe Mathieu-Daudé 写道:
TLB map_address() handlers don't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
---
target/mips/internal.h | 8
target/mips/tlb_helper.c | 15
Translate embedded assembly into IO writes which is more
readable.
Also hardcode cm_base at boot time instead of reading from CP0.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
--
v3: Use bl_gen_write_ulong.
---
hw/mips/boston.c | 47
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang
---
hw/mips/malta.c | 68 -
1 file changed, 22 insertions(+), 46 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ffd67b8293
101 - 200 of 383 matches
Mail list logo
