: 20230904161847.18468-1-jonathan.came...@huawei.com
Jonathan Cameron (3):
hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c
hw/cxl: Add utility functions decoder interleave ways and target
count.
hw/cxl: Support 4 HDM decoders at all levels of topology
include/hw/cxl/cxl_component.h | 30
On Tue, 5 Sep 2023 18:55:23 +0200
Philippe Mathieu-Daudé wrote:
> On 5/9/23 17:06, Jonathan Cameron wrote:
> > On Tue, 5 Sep 2023 15:56:39 +0100
> > Jonathan Cameron via wrote:
> >
> >> On Mon, 4 Sep 2023 20:26:59 +0200
> >> Philippe Mathieu-Dau
On Wed, 6 Sep 2023 19:22:19 +0800
Yuquan Wang wrote:
> Hi, Jonathan
> On 2023-09-05 22:34, jonathan.cameron wrote:
> >
> > As I understand it the distinction is more about the format / contents of
> > that memory
> > than how you access them.
>
> Yes, RCH DP RCRB includes registers from
On Thu, 31 Aug 2023 21:29:14 -0400
Gregory Price wrote:
> Create a new device to emulate the SK hynix Niagara MHSLD platform.
>
> This device has custom CCI commands that allow for applying isolation
> to each memory block between hosts. This enables an early form of
> dynamic capacity, whereby
On Tue, 5 Sep 2023 10:48:54 +0200
Philippe Mathieu-Daudé wrote:
> Hi Jonathan,
>
> On 4/9/23 19:57, Jonathan Cameron wrote:
> > Will be needed so there is a defined serial number for
> > information queries via the Switch CCI.
> >
> > Signed-off-by: Jonathan
On Tue, 5 Sep 2023 05:02:47 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Sep 05, 2023 at 10:48:54AM +0200, Philippe Mathieu-Daudé wrote:
> > Hi Jonathan,
> >
> > On 4/9/23 19:57, Jonathan Cameron wrote:
> > > Will be needed so there is a defined serial
On Mon, 4 Sep 2023 20:36:02 +0200
Philippe Mathieu-Daudé wrote:
> Hi Jonathan,
>
> Few style comments inlined.
>
> On 4/9/23 18:47, Jonathan Cameron wrote:
> > Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
> > and CXL Type 3 end points.
>
On Tue, 5 Sep 2023 15:56:39 +0100
Jonathan Cameron via wrote:
> On Mon, 4 Sep 2023 20:26:59 +0200
> Philippe Mathieu-Daudé wrote:
>
> > On 4/9/23 18:47, Jonathan Cameron wrote:
> > > As an encoded version of these key configuration parameters is
> > > a regis
On Mon, 4 Sep 2023 20:26:59 +0200
Philippe Mathieu-Daudé wrote:
> On 4/9/23 18:47, Jonathan Cameron wrote:
> > As an encoded version of these key configuration parameters is
> > a register, provide functions to extract it again so as to avoid
> > the need for du
On Tue, 5 Sep 2023 18:45:02 +0800
Yuquan Wang wrote:
> Hi, Jonathan
> On 2023-09-04 20:43, jonathan.cameron wrote:
> >
> > At the system design level, MMIO space of Root complex register space via
> > RCRB
> > does not map in a similar fashion to PCIE MMIO space (which is handled via
> >
Will be needed so there is a defined serial number for
information queries via the Switch CCI.
Signed-off-by: Jonathan Cameron
---
No ordering dependencies wrt to other CXL patch sets.
Whilst we 'need' it for the Switch CCI set it is valid without
it and aligns with existing EP serial number
On Thu, 31 Aug 2023 21:29:13 -0400
Gregory Price wrote:
> When memory accesses are made, some MHSLD's would validate the address
> is within the scope of allocated sections. To do this, the base device
> must call an optional function set by inherited devices.
>
> Signed-off-by: Gregory Price
On Thu, 31 Aug 2023 21:29:11 -0400
Gregory Price wrote:
> Call CXL_TYPE3 once at top of function to avoid multiple invocations.
>
> Signed-off-by: Gregory Price
Good cleanup on it's own.
I'll queue this one up on the backend of the sanitize set that
introduces the second use in each of these
Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
and CXL Type 3 end points.
Signed-off-by: Jonathan Cameron
---
Note there is a fix in here for a wrong increment that had
no impact when there was only one HDM decoder.
include/hw/cxl/cxl_component.h | 7 +++
hw/cxl/cxl
As an encoded version of these key configuration parameters is
a register, provide functions to extract it again so as to avoid
the need for duplicating the storage.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h | 14 ++
hw/cxl/cxl-component-utils.c | 17
Jonathan Cameron (2):
hw/cxl: Add utility functions decoder interleave ways and target
count.
hw/cxl: Support 4 HDM decoders at all levels of topology
include/hw/cxl/cxl_component.h | 21
hw/cxl/cxl-component-utils.c | 43 +++
hw/cxl/cxl-host.c | 65
Description of change in previous patch.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/DSDT.cxl| Bin 9655 -> 9723 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
{ 0x00, 0x00 }
}
})
}
}
}
Signed-off-by: Dave Jiang
Signed-off-by: Jonathan Cameron
--
v2: Minor edit to drop reference to switches in patch description.
---
include/hw/acpi/cxl.h | 1 +
hw/acpi/cxl.c | 57 +++
hw/i386/acp
Addition of QTG in following patch requires an update to the test
data.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
for ACPI0017 device
Jonathan Cameron (2):
tests/acpi: Allow update of DSDT.cxl
tests/acpi: Update DSDT.cxl with QTG DSM
include/hw/acpi/cxl.h| 1 +
hw/acpi/cxl.c| 57 +++
hw/i386/acpi-build.c | 1 +
tests/data/acpi/q35/DSDT.cxl | Bin
From: Li Zhijian
Using the same style as elsewhere for topology / topo
Signed-off-by: Li Zhijian
Link:
https://lore.kernel.org/r/20230519085802.2106900-2-lizhij...@cn.fujitsu.com
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 8
1 file changed, 4 insertions(+), 4
From: Fan Ni
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
Reviewed-by: Davidlohr Bueso
Reviewed-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1
he comment notes
it's 16GB/s for .latency_bandwidth.
Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE")
Signed-off-by: Dave Jiang
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_upstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
From: Li Zhijian
Allocate targets and targets[n] resources when all sanity checks are
passed to avoid memory leaks.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Li Zhijian
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 12 ++--
1
A small set gathering patches that have been posted and reviewed on list
over the last few months. Looking to get these upstream before making
any significant changes to the CXL emulation for this cycle.
More wide spread cleanup will follow later this cycle (reference
updates to available spec
On Mon, 4 Sep 2023 18:27:10 +0800
Yuquan Wang wrote:
> Hi, Jonathan
>
Hi Yuquan
Given this question isn't just ARM specific included qemu-devel in the cc list
as
that gets much wider reading than qemu-arm.
> Due to my poor experience and knowledge on cxl development history, I am
> sorry to
On Thu, 31 Aug 2023 12:59:24 -0400
Gregory Price wrote:
> On Mon, Aug 07, 2023 at 03:56:09PM +0100, Jonathan Cameron wrote:
> > On Fri, 21 Jul 2023 12:35:08 -0400
> > Gregory Price wrote:
> >
> > > Implement the MHD GET_INFO cci command and add a shared me
> > +
> > +/*
> > + * This function check whether a dpa range [dpa, dpa + len) has been backed
> > + * with dc extents, used when validating read/write to dc regions
> > + */
> > +static bool test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
> > +uint64_t len)
> > +{
> > +int
On Fri, 25 Aug 2023 09:34:50 -0700
Fan Ni wrote:
> On Fri, Aug 25, 2023 at 12:42:56PM +0100, Jonathan Cameron wrote:
> > On Thu, 24 Aug 2023 13:49:00 -0700
> > Fan Ni wrote:
> >
> > > On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> &
posted code by Padmakar Kalghatgi, Arun
> Kumar Agasar and Saurav Kumar.
>
> Signed-off-by: Klaus Jensen
Hi Klaus
Minor suggestions inline. Either way given how trivial they are
Reviewed-by: Jonathan Cameron
> diff --git a/hw/nvme/nmi-i2c.c b/hw/nvme/nmi-i2c.c
> new file mode 10
tended to derive from this and implement the class
> methods.
>
> Parts of this implementation is inspired by code[1] previously posted by
> Jonathan Cameron.
>
> Squashed a fix[2] from Matt Johnston.
>
> [1]:
> https://lore.kernel.org/qemu-devel/20220520170128.4436-
On Wed, 23 Aug 2023 11:21:58 +0200
Klaus Jensen wrote:
> From: Klaus Jensen
>
> Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a
> message.
>
> Signed-off-by: Klaus Jensen
Reviewed-by: Jonathan Cameron
> ---
> hw/i2c/smb
t/qemu/-/issues/1846
> Signed-off-by: Richard Henderson
Tested-by: Jonathan Cameron
I'm not pretending I've understood the change though, just that
it makes the crashes I saw go away.
Jonathan
> ---
> softmmu/physmem.c | 40 +---
> 1 file changed
On Thu, 10 Aug 2023 14:18:50 +0100
Jonathan Cameron via wrote:
> On Fri, 4 Aug 2023 09:15:13 -0700
> Richard Henderson wrote:
>
> > On 8/4/23 04:09, Mikhail Tyutin wrote:
> > > Apply save_iotlb_data() to io_readx() as well as to io_writex(). This
&g
On Thu, 24 Aug 2023 13:49:00 -0700
Fan Ni wrote:
> On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> > On Tue, 25 Jul 2023 18:39:56 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Not all dpa range in t
all the
hard work. Note a common case in real systems is likely to be Multi Head
devices for memory pooling, but they also require configuration before the
memory is available to the host, so the points above are the same.
Jonathan
>
>
>
> On Fri, 11 Aug 2023 at 19:25, Jo
8
> Sent: Thursday, August 17, 2023 10:18 PM
> To: Jonathan Cameron
> Cc: Jonathan Cameron via ; linux-...@vger.kernel.org
>
> Subject: Re: CXL volatile memory is not listed
>
> Hi Jonathan,
>
> The use case of CXL switch will always need some sort of management
> ag
On Mon, 14 Aug 2023 17:50:58 +0800
Zhao Liu wrote:
> Hi Jonathan,
>
> On Tue, Aug 08, 2023 at 12:57:09PM +0100, Jonathan Cameron via wrote:
> > Date: Tue, 8 Aug 2023 12:57:09 +0100
> > From: Jonathan Cameron via
> > Subject: [RFC PATCH 1/5] hw/acpi: Add PPTT cach
On Mon, 14 Aug 2023 11:13:58 +0100
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > Used to drive the MPAM cache intialization and to exercise more
> > of the PPTT cache entry generation code. Perhaps a default
> > L3 cache is acceptable for max?
> >
>
On Fri, 11 Aug 2023 18:31:28 +0800
Yuquan Wang wrote:
> Hi,
> On 2023-08-10 21:56, jonathan.cameron wrote:
>
> So took a look at your issue - be it on the cxl-2023-08-07 branch rebased on
> qemu/master
> from today (side effect of looking at the segfault that was stopping me
> getting to
gt; >
> Manual works with "cxl create regiton" :)
Great.
Jonathan
>
> On Thu, 10 Aug 2023 at 16:05, Jonathan Cameron
> wrote:
> >
> > On Wed, 9 Aug 2023 04:21:47 +0530
> > Maverickk 78 wrote:
> >
> > > Hello,
> > >
> &
On Fri, 4 Aug 2023 09:15:13 -0700
Richard Henderson wrote:
> On 8/4/23 04:09, Mikhail Tyutin wrote:
> > Apply save_iotlb_data() to io_readx() as well as to io_writex(). This fixes
> > SEGFAULT on qemu_plugin_hwaddr_phys_addr() call plugins for addresses
> > inside of
> > MMIO region.
> >
> >
On Wed, 9 Aug 2023 04:21:47 +0530
Maverickk 78 wrote:
> Hello,
>
> I am running qemu-system-x86_64
>
> qemu-system-x86_64 --version
> QEMU emulator version 8.0.92 (v8.1.0-rc2-80-g0450cf0897)
>
+Cc linux-cxl as the answer is more todo with linux than qemu.
> qemu-system-x86_64 \
> -m
On Wed, 9 Aug 2023 12:45:35 -0400
Alistair Francis wrote:
> On Wed, Aug 9, 2023 at 8:11 AM Jonathan Cameron
> wrote:
> >
> > On Tue, 8 Aug 2023 11:51:21 -0400
> > Alistair Francis wrote:
> >
> > > The Security Protocol and Data Model (SPDM) Specificati
On Tue, 8 Aug 2023 11:51:21 -0400
Alistair Francis wrote:
> The Security Protocol and Data Model (SPDM) Specification defines
> messages, data objects, and sequences for performing message exchanges
> over a variety of transport and physical media.
> -
>
On Sat, 5 Aug 2023 08:46:29 +0300
Michael Tokarev wrote:
> 31.05.2023 14:08, Jonathan Cameron via wrote:
> > On Wed, 31 May 2023 09:51:43 +0200
> > Philippe Mathieu-Daudé wrote:
> >
> >> On 31/5/23 08:07, Li Zhijian wrote:
> >>> Allocate target
on that front.
Note that for now MPAM MSC creation is dependent on having SRAT
and hence you need some numa nodes defined.
Signed-off-by: Jonathan Cameron
---
include/hw/arm/mpam.h| 1 +
hw/arm/virt-acpi-build.c | 197 +++
hw/arm/virt.c| 134
Note this doesn't 'do' anything other than provide an introspection
interface. The intent here is to support work on the Linux kernel support
and for that a functional emulation of the interface is useful.
Signed-off-by: Jonathan Cameron
---
qapi/mpam.json | 78
qapi/qapi
It is common to support MPAM on CPU cores, but not in the rest
of the system, so there is little disadvantage in always enabling
these.
Signed-off-by: Jonathan Cameron
---
target/arm/cpu.h| 15 +++
target/arm/cpu.c| 10 +-
target/arm/helper.c | 30
Used to drive the MPAM cache intialization and to exercise more
of the PPTT cache entry generation code. Perhaps a default
L3 cache is acceptable for max?
Signed-off-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/arm/tcg
L3.
FIXME: Test updates.
Signed-off-by: Jonathan Cameron
---
qapi/machine.json | 8 +-
include/hw/acpi/aml-build.h | 19 +++-
include/hw/boards.h | 4 +
hw/acpi/aml-build.c | 189 ++--
hw/arm/virt-acpi-build.c| 130
"mbw-idr": 0,
"csumon-idr": 0,
"esr": 0,
"ecr": 1,
"cfg-part-sel": 0,
"iidr": 44042038,
"cpor-idr": 32,
On Fri, 4 Aug 2023 21:17:59 +0800
Zhao Liu wrote:
> Hi Jonathan,
>
> On Tue, Aug 01, 2023 at 04:35:27PM +0100, Jonathan Cameron via wrote:
> > >
>
> [snip]
>
> > >
> > > ## New property: x-l2-cache-topo
> > >
> > > The prop
On Fri, 21 Jul 2023 12:35:09 -0400
Gregory Price wrote:
> Create a new device to emulate the SK hynix Niagara MHSLD platform.
>
> This device has custom CCI commands that allow for applying isolation
> to each memory block between hosts. This enables an early form of
> dynamic capacity, whereby
On Fri, 21 Jul 2023 12:35:08 -0400
Gregory Price wrote:
> Implement the MHD GET_INFO cci command and add a shared memory
> region to the type3 device to host the information.
>
> Add a helper program to initialize this shared memory region.
>
> Add a function pointer to type3 devices for
On Fri, 4 Aug 2023 12:41:26 -0400
Gregory Price wrote:
> On Fri, Aug 04, 2023 at 04:14:14PM +0100, Jonathan Cameron wrote:
> > On Fri, 21 Jul 2023 12:35:06 -0400
> > Gregory Price wrote:
> >
> > > This enables wrapper devices to customize the base device's CCI
&
On Fri, 4 Aug 2023 14:07:55 -0400
Gregory Price wrote:
> On Fri, Aug 04, 2023 at 05:36:23PM +0100, Jonathan Cameron wrote:
> > On Tue, 25 Jul 2023 18:39:56 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Add (file/memory backed
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and add get DC extent list mailbox command per
> CXL.spec.3.0:.8.2.9.8.9.2.
>
> Signed-off-by: Fan Ni
A couple of general name format
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Per CXL spec 3.0, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
>
> Signed-off-by: Fan Ni
I'm reviewing these
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Since fabric manager emulation is not supported yet, the change implements
> the functions to add/release dynamic capacity extents as QMP interfaces.
>
> 1. Add dynamic capacity extents:
>
> For example, the command to add
On Mon, 7 Aug 2023 09:53:42 +0100
Jonathan Cameron via wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Not all dpa range in the dc regions is valid to access until an extent
> > covering the range has been ad
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Not all dpa range in the dc regions is valid to access until an extent
> covering the range has been added. Add a bitmap for each region to
> record whether a dc block in the region has been backed by dc extent.
> For the
On Tue, 25 Jul 2023 18:39:56 +
Fan Ni wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend, all the dynamic capacity regions
> will share a single, large enough host backend. Set up address space for
> DC regions to support read/write operations to dynamic capacity for DCD.
>
>
On Tue, 25 Jul 2023 18:39:55 +
Fan Ni wrote:
> From: Fan Ni
>
> With the change, when setting up memory for type3 memory device, we can
> create DC regions
> A property 'num-dc-regions' is added to ct3_props to allow users to pass the
> number of DC regions to create. To make it easier,
On Tue, 25 Jul 2023 18:39:55 +
Fan Ni wrote:
> From: Fan Ni
>
> Rename mem_size as static_mem_size for type3 memdev to cover static RAM and
> pmem capacity, preparing for the introduction of dynamic capacity to support
> dynamic capacity devices.
>
> Signed-off-by: Fan Ni
Looks good.
On Tue, 25 Jul 2023 18:39:55 +
Fan Ni wrote:
> From: Fan Ni
You should fix the author on these to match the SoB
git commit --amend --author="Fan Ni " fixes them.
I'm trying to pick these up for my tree as I review them (where they aren't
invasive). So I'll fix this stuff whilst doing so.
ion)
without the need to change the base device.
The also enabled the base device to dispatch those commands without
requiring additional driver support.
Signed-off-by: Gregory Price
Link: https://lore.kernel.org/r/20230721163505.1910-3-gregory.pr...@memverge.com
Signed-off-by: Jonathan Cameron
On Fri, 21 Jul 2023 12:35:04 -0400
Gregory Price wrote:
Typo in patch title. reference
> This allows devices to have fully customized CCIs, along with complex
> devices where wrapper devices can override or add additional CCI
> commands without having to replicate full command structures or
>
On Tue, 25 Jul 2023 18:39:55 +
Fan Ni wrote:
> From: Fan Ni
>
> Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output
> Payload), dynamic capacity event log size should be part of
> output of the Identify command.
> Add dc_event_log_size to the output payload for the host to get
On Tue, 1 Aug 2023 18:35:10 +0800
Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> This is the our v3 patch series, rebased on the master branch at the
> commit 234320cd0573 ("Merge tag 'pull-target-arm-20230731' of https:
> //git.linaro.org/people/pmaydell/qemu-arm into staging").
>
>
On Sat, 22 Jul 2023 21:52:06 -0700
Ira Weiny wrote:
> nifan@ wrote:
> > From: Fan Ni
> >
> > The patch series provides dynamic capacity device (DCD) emulation in Qemu.
>
> I don't the patches on the list.
>
>
On Wed, 19 Jul 2023 14:49:07 -0400
Gregory Price wrote:
> On Wed, Jul 19, 2023 at 09:19:47AM +0100, Jonathan Cameron wrote:
> > On Tue, 18 Jul 2023 17:30:57 -0400
> > Gregory Price wrote:
> >
> > > On Mon, Jul 17, 2023 at 06:16:39PM +0100, Jonathan Cameron wro
On Tue, 18 Jul 2023 17:30:57 -0400
Gregory Price wrote:
> On Mon, Jul 17, 2023 at 06:16:39PM +0100, Jonathan Cameron wrote:
> > @@ -397,8 +401,9 @@ struct CXLType3Dev {
> > AddressSpace hostpmem_as;
> > CXLComponentState cxl_cstate;
> > CXLDeviceState
ck' and 'make check-avocado'.
Ah. Had this on my todo list form your report but got distracted.
Anyhow, thanks for fixing it up.
Tested somewhat. Actually poking this particular DOE instance to
read the CDAT requires a bunch of kernel hacks I haven't forward
ported recently and I don't want to delay thi
Allow a switch CCI to perform basic tunneling (which is transported
in real hardware via PCIe VDM) to downstream devices.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-mailbox-utils.c | 92 +
hw/mem/cxl_type3.c
Signed-of-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 87 ++
1 file changed, 87 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 9c1020d9ab..4cddd6eae1 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl
a BMC attached to a switch
upstream port, it is also useful to allow emulation of this feature
on the upstream port connected to a host using the CXL devices as
this greatly simplifies testing.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl.h | 6 +
include/hw/cxl
troller"
}
}
})
}
}
To add devices to the bus use something like:
-device i2c_mctp_cxl_switch,bus=aspeed.i2c.bus.0,address=4,target=us0
Signed-off-by: Jonathan Cameron
---
include/hw/i386/pc.h | 1 +
hw/i386/acpi-build.c | 65 +++
A lot more needed here on what these are for and what can be done
with them.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 27 +++
1 file changed, 27 insertions(+)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index
}
}
})
}
Tests not updated given I'm not currently proposing this for upstream.
Signed-off-by: Jonathan Cameron
---
hw/arm/virt-acpi-build.c | 60
hw/i2c/meson.build | 2 +-
2 files changed, 61 insertions(+), 1 deletion(-)
dif
. Throw down the simplest reset controller
I could find so as to avoid need to make any changes to the kernel
code.
Patch also builds appropriate device tree.
Signed-off-by: Jonathan Cameron
---
include/hw/arm/virt.h | 2 +
hw/arm/virt.c | 86
The CCI and Fabric Manager APIs are used to configure CXL switches and
devices. DMTF has defined an MCTP binding specification to carry
these messages. The end goal of this work is to hook this
up to emulated CXL switches and devices to allow control of the
configuration.
Signed-off-by: Jonathan
From: Matt Johnston
The Null Destination ID, 0, is used for MCTP control messages when
addressing by physical ID. That is used for Get Endpoint ID and
Set Endpoint ID when querying/assigning an EID to an endpoint.
Signed-off-by: Matt Johnston
Signed-off-by: Jonathan Cameron
---
hw/i2c/mctp.c
by code[1] previously posted by
Jonathan Cameron.
[1]:
https://lore.kernel.org/qemu-devel/20220520170128.4436-1-jonathan.came...@huawei.com/
Signed-off-by: Klaus Jensen
Signed-off-by: Jonathan Cameron
---
MAINTAINERS | 7 +
include/hw/i2c/mctp.h | 114
Needed for later patches that add MCTP over I2C support to both
x86 and ARM boards.
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/aml-build.h | 1 +
hw/acpi/aml-build.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/include/hw/acpi/aml-build.h b/include
By moving the parts of the mailbox command handling that are
CCI type specific out to the caller, make the main handling
code generic. Rename it to cxl_process_cci_message() to
reflect this new generality.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 5 -
hw/cxl/cxl
Enables having multiple CCIs per devices. Each CCI (mailbox)
has it's own state and command list, so they can't share
a single structure.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 48 ++-
hw/cxl/cxl-device-utils.c | 31 +---
hw/cxl/cxl-mailbox
New CCI types that will be supported shortly do not have a single
buffer used in both directions. As such, split it up.
For CXL mailboxes the two pointers will be aliases of the same memory
so all callbacks must allow for that.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h
Putting the pointer in the structure for command handling puts
a single variable element inside an otherwise constant structure.
Move it out as a directly passed variable and take the cxl_cmd
structures constant.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 6 +-
hw/cxl
-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 12
hw/cxl/cxl-mailbox-utils.c | 17 -
2 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 887a38bdbc..2c239fca47 100644
--- a/include/hw/cxl
.smctp_type = 0x7, /* CXL FMAPI */
.smctp_tag = MCTP_TAG_OWNER,
};
struct sockaddr_mctp addrrx;
socklen_t addrlen = sizeof(addrrx);
enum cxl_type type;
cci_sd = socket(AF_MCTP, SOCK_DGRAM, 0);
rc = bind(cci_sd, (struct sockad
To avoid repitition of switch upstream port specific data in
the CXLDeviceState structure it will be necessary to call
access the switch USP specific from mailbox callbacks.
Hence move it to a header so it is no longer an opaque
structure.
Signed-off-by: Jonathan Cameron
---
include/hw/pci
On Wed, 28 Jun 2023 10:09:47 -0700
"ni...@outlook.com" wrote:
> The 05/15/2023 16:22, Jonathan Cameron wrote:
> > On Thu, 11 May 2023 17:56:40 +
> > Fan Ni wrote:
> >
> > > From: Fan Ni
> > >
> > > Before the change, read fr
On Thu, 22 Jun 2023 13:41:32 +0200
Thomas Huth wrote:
> It's good style to clean up temporary directories when they
> are not needed anymore.
>
> Signed-off-by: Thomas Huth
Acked-by: Jonathan Cameron
> ---
> tests/qtest/cxl-test.c | 2 ++
> 1 file changed, 2 insertio
On Fri, 23 Jun 2023 02:59:44 -0400
"Michael S. Tsirkin" wrote:
> On Fri, May 26, 2023 at 06:00:06PM +0100, Jonathan Cameron wrote:
> > v8: Formatting fixes for QMP docs from Markus Armbruster (thanks!)
>
> This and other patches add a bunch of over-80 char
On Fri, 16 Jun 2023 14:10:24 -0400
Gregory Price wrote:
> On Fri, Jun 16, 2023 at 03:43:31PM +0800, Yuquan Wang wrote:
> > Hi, Gregory
> >
> > There is one confusion about CXL in QEMU I hope to consult.
> > If you have some time to look at this email, I would have better
> > understanding of
On Mon, 12 Jun 2023 19:40:29 +0100
Mark Cave-Ayland wrote:
> On 12/06/2023 16:20, Jonathan Cameron via wrote:
>
> > On Tue, 6 Jun 2023 10:47:58 +0100
> > Peter Maydell wrote:
> >
> >> From: Richard Henderson
> >>
> >> Round len_align
On Tue, 6 Jun 2023 10:47:58 +0100
Peter Maydell wrote:
> From: Richard Henderson
>
> Round len_align to 16 instead of 8, handling an odd 8-byte as part
> of the tail. Use MO_ATOM_NONE to indicate that all of these memory
> ops have only byte atomicity.
>
> Reviewed-by: Peter Maydell
>
can probably do that automatically once more infrastructure is in place.
Jonathan
>
> From: Jonathan Cameron
> Sent: Thursday, June 8, 2023 3:36 AM
> To: Shesha Bhushan Sreenivasamurthy
> Cc: linux-...@vger.kernel.org ;
> <"qemu-devel@nongnu.org"
> Subject: [EXT] R
-terry.bow...@amd.com/T/#t
for example
Jonathan
On Thu, 8 Jun 2023 11:31:53 +0100
Jonathan Cameron wrote:
> On Wed, 7 Jun 2023 23:01:11 +
> Shesha Bhushan Sreenivasamurthy wrote:
>
> > Hi,
> > For DCD sideband there needs to be LD-ID. Is the following approach
> &
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