> > aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
> > > diff --git a/include/hw/acpi/cpu_hotplug.h
> > b/include/hw/acpi/cpu_hotplug.h
> > > index 48b291e45e..ef631750b4 100644
> > > --- a/include/hw/acpi/cpu_hotplug.h
> > > +++ b/include/hw/acpi/cpu_hotplug.h
> > > @@ -20,6 +20,8 @@
> >
On Tue, 3 Oct 2023 12:05:11 +0100
Salil Mehta wrote:
> Hi Jonathan,
>
> > From: Jonathan Cameron
> > Sent: Monday, October 2, 2023 4:53 PM
> > To: Salil Mehta
> > Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; m...@kernel.org; jean-
> > phili...@linaro.org; lpieral...@kernel.org;
On Sat, 30 Sep 2023 01:19:31 +0100
Salil Mehta wrote:
> Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also
> involves destruction of the CPU AddressSpace. Add common function to help
> destroy the CPU AddressSpace.
>
> Signed-off-by: Salil Mehta
I'm not that familiar
On Sat, 30 Sep 2023 01:19:30 +0100
Salil Mehta wrote:
> ACPI GED shall be used to convey to the guest kernel about any CPU
> hot-(un)plug
> events. Therefore, existing ACPI GED framework inside QEMU needs to be
> enhanced
> to support CPU hotplug state and events.
>
> Co-developed-by: Keqian
On Sat, 30 Sep 2023 01:19:29 +0100
Salil Mehta wrote:
> OSPM evaluates _EVT method to map the event. The cpu hotplug event eventually
> results in start of the cpu scan. Scan figures out the cpu and the kind of
> event(plug/unplug) and notifies it back to the guest.
>
> The change in this patch
On Sat, 30 Sep 2023 01:19:28 +0100
Salil Mehta wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based
> on
> PCI and is IO port based and hence existing cpus AML code assumes _CRS objects
> would evaluate to a system resource which describes IO Port address. But
On Sat, 30 Sep 2023 01:19:27 +0100
Salil Mehta wrote:
> ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI
> events
> when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM
> then maps or demultiplexes the event by evaluating _EVT method.
>
> This
On Fri, 29 Sep 2023 13:42:59 +0100
Salil Mehta wrote:
> ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI
> events
> when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM
> then maps or demultiplexes the event by evaluating _EVT method.
>
> This
On Sat, 30 Sep 2023 01:19:26 +0100
Salil Mehta wrote:
> ACPI CPU hotplug related initialization should only happen if ACPI_CPU_HOTPLUG
> support has been enabled for particular architecture. Add
> cpu_hotplug_hw_init()
> stub to avoid compilation break.
>
> Signed-off-by: Salil Mehta
Seems
On Sat, 30 Sep 2023 01:19:25 +0100
Salil Mehta wrote:
> CPU ctrl-dev MMIO region length could be used in ACPI GED and various other
> architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more
> appropriate common header file.
>
> Signed-off-by: Salil Mehta
> Reviewed-by: Alex
On Sat, 30 Sep 2023 01:19:24 +0100
Salil Mehta wrote:
> KVM vCPU creation is done once during the initialization of the VM when Qemu
> threads are spawned. This is common to all the architectures.
>
> Hot-unplug of vCPU results in destruction of the vCPU objects in QOM but
> the KVM vCPU
On Mon, 2 Oct 2023 09:15:58 +0200
Klaus Jensen wrote:
> On Sep 15 21:27, Alistair Francis wrote:
> > From: Wilfred Mallawa
> >
> > Setup Data Object Exchance (DOE) as an extended capability for the NVME
> > controller and connect SPDM to it (CMA) to it.
> >
> > Signed-off-by: Wilfred Mallawa
On Wed, 27 Sep 2023 10:37:37 -0600
Alex Williamson wrote:
> On Wed, 27 Sep 2023 15:03:09 +
> Vikram Sethi wrote:
>
> > > From: Alex Williamson
> > > Sent: Wednesday, September 27, 2023 9:25 AM
> > > To: Jason Gunthorpe
> > > Cc: Jonathan Cameron ; Ankit Agrawal
> > > ; David Hildenbrand
On Wed, 27 Sep 2023 12:42:40 -0300
Jason Gunthorpe wrote:
> On Wed, Sep 27, 2023 at 03:03:09PM +, Vikram Sethi wrote:
> > > From: Alex Williamson
> > > Sent: Wednesday, September 27, 2023 9:25 AM
> > > To: Jason Gunthorpe
> > > Cc: Jonathan Cameron ; Ankit Agrawal
> > > ; David Hildenbrand
On Wed, 27 Sep 2023 15:03:09 +
Vikram Sethi wrote:
> > From: Alex Williamson
> > Sent: Wednesday, September 27, 2023 9:25 AM
> > To: Jason Gunthorpe
> > Cc: Jonathan Cameron ; Ankit Agrawal
> > ; David Hildenbrand ; Cédric Le
> > Goater ; shannon.zha...@gmail.com;
> >
On Wed, 27 Sep 2023 19:13:35 +
Fan Ni wrote:
> On Mon, Sep 25, 2023 at 04:22:58PM +0100, Jonathan Cameron wrote:
>
> > Rename the version not burried in the macro to cap_h.
> The change looks good to me. Just one minor thing. why "version" get
> involved here?
>
Used in the sense of two
...
> +/* CXL r3.0 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */
> +static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
> + uint8_t *payload_in,
> + size_t len_in,
> +
On Thu, 14 Sep 2023 19:45:59 -0700
wrote:
> From: Ankit Agrawal
>
> To add the memory in the guest as NUMA nodes, it needs the PXM node index
> and the total count of nodes associated with the memory. The range of
> proximity domains are communicated to the VM as part of the guest ACPI
> using
On Wed, 27 Sep 2023 07:14:28 +
Ankit Agrawal wrote:
> > >
> > > Based on the suggestions here, can we consider something like the
> > > following?
> > > 1. Introduce a new -numa subparam 'devnode', which tells Qemu to mark
> > > the node with MEM_AFFINITY_HOTPLUGGABLE in the SRAT's memory
On Tue, 26 Sep 2023 14:54:36 +
Ankit Agrawal wrote:
> > With an ACPI spec clarification agreed then I'm fine with
> > using this for all the cases that have come up in this thread.
> > Or a good argument that this is valid in under existing ACPI spec.
>
> Hi Jonathan
>
> I looked at the
On Mon, 25 Sep 2023 13:00:43 -0300
Jason Gunthorpe wrote:
> On Mon, Sep 25, 2023 at 03:53:51PM +0100, Jonathan Cameron wrote:
> > On Mon, 25 Sep 2023 11:03:28 -0300
> > Jason Gunthorpe wrote:
> >
> > > On Mon, Sep 25, 2023 at 02:54:40PM +0100, Jonathan Cameron wrote:
> > >
> > > >
On Mon, 25 Sep 2023 17:11:05 +0100
Jonathan Cameron wrote:
> Based on: [PATCH] hw/cxl: Fix local variable shadowing of cap_hdrs
> Based on: [PATCH v2 0/3] hw/cxl: Add dummy ACPI QTG DSM
Missed one.
Based on: [PATCH v4 0/4] hw/cxl: Support emulating 4 HDM decoders throughout
topology
> Based
The implementation of tunneling makes the choice that our Type 3 device is
a Logical Device (LD) of a Multi-Logical Device (MLD) that just happens to
only have one LD for now.
Tunneling is supported from a Switch Mailbox CCI or via MCTP over I2C
connected to the switch mctp CCI via an outer level
Needed to allow the santize comamnds to be tested with proposed Linux Kernel
support. Default value + no control of the security state will work for now.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 17 +
1 file changed, 17 insertions(+)
diff --git
From: Gregory Price
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
From: Davidlohr Bueso
Make use of the background operations through the sanitize command, per CXL
3.0 specs. Traditionally run times can be rather long, depending on the
size of the media.
Estimate times based on:
https://pmem.io/documents/NVDIMM_DSM_Interface-V1.8.pdf
Signed-off-by:
From: Davidlohr Bueso
Notify when the background operation is done. Note that for now background
commands are only supported on the main Type 3 mailbox.
Signed-off-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-device-utils.c | 10
From: Davidlohr Bueso
Support background commands in the mailbox, and update
cmd_infostat_bg_op_sts() accordingly. This patch does not implement mbox
interrupts upon completion, so the kernel driver must rely on polling to
know when the operation is done.
Signed-off-by: Davidlohr Bueso
Add this command for both the Switch CCI and the MCTP CCI found
in switch upstream ports.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c
For now, provide this command on type 3 main mailbox only.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 26fb0192a9..d9785f324a
Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_downstream.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/pci-bridge/cxl_downstream.c
CXL switch CCIs were added in CXL r3.0. They are a PCI function,
identified by class code that provides a CXL mailbox (identical
to that previously defined for CXL type 3 memory devices) over which
various FM-API commands may be used. Whilst the intent of this
feature is enable switch control from
Enable it for MCTP CCI for the switch. Will shortly be enabled for switch
CCI as well.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl.h | 6
hw/cxl/cxl-mailbox-utils.c | 65 ++
hw/pci-bridge/cxl_downstream.c | 4 +--
3 files changed,
Add initial documentation for the MCTP over I2C management device. At
current time this can only be used with the Aspeed I2C controller which
is only available in aspeed SoCs, though can be added to other
emulated boards.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 27
Add this command that is only available via out of band CCIs. It replicates
information that can be discovered inband via PCI config space.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 48 ++
1 file changed, 48 insertions(+)
diff --git
The CCI and Fabric Manager APIs are used to configure CXL switches and
devices. DMTF has defined an MCTP binding specification to carry these
messages. The end goal of this work is to hook this up to emulated CXL
switches and devices to allow control of the configuration.
Since this relies on
To avoid repetition of switch upstream port specific data in the
CXLDeviceState structure it will be necessary to access the switch USP
specific data from mailbox callbacks. Hence move it to cxl_device.h so it
is no longer an opaque structure.
Signed-off-by: Jonathan Cameron
---
Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own
state and command list, so they can't share a single structure.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 45 ++
hw/cxl/cxl-device-utils.c | 31 +---
By moving the parts of the mailbox command handling that are CCI type
specific out to the caller, make the main handling code generic. Rename it
to cxl_process_cci_message() to reflect this new generality.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 5 +++-
New CCI types that will be supported shortly do not have a single buffer
used in both directions. As such, split it up. For CXL mailboxes the two
pointers will be aliases of the same memory so all callbacks must allow
for that.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h |
Putting the pointer in the structure for command handling puts a single
variable element inside an otherwise constant structure. Move it out as
a directly passed variable and take the cxl_cmd structures constant.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 13
Based on: [PATCH] hw/cxl: Fix local variable shadowing of cap_hdrs
Based on: [PATCH v2 0/3] hw/cxl: Add dummy ACPI QTG DSM
Based on: [PATCH V2] hw/pci-bridge/cxl-upstream: Add serial number extended
capability support
Based on: [PATCH v3 0/4] hw/cxl: Line length reduction and related
Based on:
Rename the version not burried in the macro to cap_h.
Signed-off-by: Jonathan Cameron
---
I had another instance of this in a series I'll post later today.
Cleaned that up the same way.
hw/cxl/cxl-device-utils.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On Mon, 25 Sep 2023 11:03:28 -0300
Jason Gunthorpe wrote:
> On Mon, Sep 25, 2023 at 02:54:40PM +0100, Jonathan Cameron wrote:
>
> > Possible the ASWG folk would say this is fine and I'm reading too much into
> > the spec, but I'd definitely suggest asking them via the appropriate path,
> > or
On Thu, 21 Sep 2023 16:28:00 +1000
Alistair Francis wrote:
> On Mon, Sep 18, 2023 at 8:28 PM Jonathan Cameron
> wrote:
> >
> > On Mon, 18 Sep 2023 13:16:01 +1000
> > Alistair Francis wrote:
> >
> > > On Sat, Sep 16, 2023 at 1:19 AM Jonathan Cameron
> > > wrote:
> > > >
> > > > On Fri, 15
On Fri, 15 Sep 2023 16:48:41 +0200
Igor Mammedov wrote:
> On Fri, 15 Sep 2023 15:25:09 +0100
> Jonathan Cameron via wrote:
>
> > On Thu, 14 Sep 2023 19:45:56 -0700
> > wrote:
> >
> > > From: Ankit Agrawal
> > >
> > > The
On Fri, 22 Sep 2023 05:49:46 +
Ankit Agrawal wrote:
> Hi Jonathan
Hi Ankit,
>
> > > +if (pcidev->pdev.has_coherent_memory) {
> > > +uint64_t start_node = object_property_get_uint(obj,
> > > + "dev_mem_pxm_start", _abort);
> > > +
On Mon, 18 Sep 2023 13:36:56 -0400
Gregory Price wrote:
> Create a new device to emulate the SK hynix Niagara MHSLD platform.
>
> This device has custom CCI commands that allow for applying isolation
> to each memory block between hosts. This enables an early form of
> dynamic capacity, whereby
On Thu, 14 Sep 2023 11:53:40 +0200
Klaus Jensen wrote:
> This adds a generic MCTP endpoint model that other devices may derive
> from.
>
> Also included is a very basic implementation of an NVMe-MI device,
> supporting only a small subset of the required commands.
>
> Since this all relies on
On Wed, 20 Sep 2023 08:08:39 +0300
Michael Tokarev wrote:
> 19.09.2023 12:34, Jonathan Cameron via wrote:
> > Establishing that only register accesses of size 4 and 8 can occur
> > using these functions requires looking at their callers. Make it
> > easier to see that by us
These crossed with the previous fix to get rid of examples
using aarch64 for which support is not yet upstream.
Reviewed-by: Fan Ni
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1892
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 4 ++--
1 file changed, 2
This has been missing from the start. Assume it should match
with cxl/cxl-component-utils.c as both were part of early
postings from Ben.
Suggested-by: Philippe Mathieu-Daudé
Acked-by: Dave Jiang
Acked-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v2:
- Add similar
v2:
- Tag collection.
- Patch 2 discussion on appropriate license concluded that this should
have originally only been accepted on GPL-v2 and later. However, I've
left it as GPL-v2-only as that is what was used for other CXL files and
for the license to be usefully relaxed we need to do
From: Dmitry Frolov
According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
array is iterated from 0 to 15. But it is statically declared of length 8.
Thus, out of bound array access may occur.
Fixes:
On Tue, 19 Sep 2023 09:47:06 +0100
Daniel P. Berrangé wrote:
> On Mon, Sep 18, 2023 at 02:14:40PM -0700, Ira Weiny wrote:
> > Jonathan Cameron wrote:
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell wrote:
> > >
> > > > On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > > >
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Reviewed-by: Michael Tokarev
Signed-off-by: Jonathan Cameron
---
v3: Put removed space back in and rewrap some
On Mon, 18 Sep 2023 18:38:10 +0100
Peter Maydell wrote:
> On Mon, 18 Sept 2023 at 18:26, Dave Jiang wrote:
> >
> >
> >
> > On 9/18/23 10:00, Jonathan Cameron wrote:
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell wrote:
> > >
> > >> On Mon, 18 Sept 2023 at 16:04, Jonathan
Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fan Ni
---
include/hw/cxl/cxl_pci.h | 6 ++---
hw/cxl/cxl-component-utils.c | 49
Bring this read function inline with the others that do
check for unexpected size values.
Also reduces line lengths to sub 80 chars.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fan Ni
---
hw/cxl/cxl-device-utils.c | 11 +++
1 file changed, 7
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
matching size, allowing fixed values to be used for
v3:
- Fix an odd spacing change that Fan Ni noticed in review.
- Picked up tags.
Suggested-by: Michael S. Tsirkin
Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.
This series is focused on tidying
On Mon, 18 Sep 2023 16:48:45 +
Fan Ni wrote:
> On Fri, Sep 15, 2023 at 06:04:18PM +0100, Jonathan Cameron wrote:
> > Michael Tsirkin observed that there were some unnecessarily
> > long lines in the CXL code in a recent review.
> > This patch is intended to rectify that where it does not
> >
On Mon, 18 Sep 2023 17:31:38 +0100
Peter Maydell wrote:
> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> wrote:
> >
> > This has been missing from the start. Assume it should match
> > with cxl/cxl-component-utils.c as both were part of early
> > postings from Ben.
>
> Sounds plausible --
These crossed with the previous fix to get rid of examples
using aarch64 for which support is not yet upstream.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/devices/cxl.rst
This has been missing from the start. Assume it should match
with cxl/cxl-component-utils.c as both were part of early
postings from Ben.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 9 +
1 file changed, 9 insertions(+)
diff --git
On Mon, 18 Sep 2023 13:41:20 +0100
Peter Maydell wrote:
> On Mon, 19 Jun 2023 at 10:58, Jonathan Cameron via
> wrote:
> >
> > On Fri, 16 Jun 2023 14:10:24 -0400
> > Gregory Price wrote:
> > >
> > > Last I tested cxl-2023-05-25 branch of Johnathan's
Misc set of trivial fixes. No conflicts with other sets outstanding
so can go with main CXL patches or perhaps via the trivial tree.
Dmitry Frolov (1):
hw/cxl: Fix out of bound array access
Jonathan Cameron (2):
hw/mem/cxl_type3: Add missing copyright and license notice
docs/cxl: Cleanout
From: Dmitry Frolov
According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
array is iterated from 0 to 15. But it is staticaly declared of length 8.
Thus, out of bound array access may occur.
Fixes:
On Thu, 14 Sep 2023 15:54:54 +0300
Michael Tokarev wrote:
> 13.09.2023 18:05, Jonathan Cameron via wrote:
> > Indexing has to be done into an array with the right size elements.
> > As such, the size parameter always matches the array element size
> > and can be used i
On Mon, 18 Sep 2023 13:16:01 +1000
Alistair Francis wrote:
> On Sat, Sep 16, 2023 at 1:19 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 15 Sep 2023 21:27:22 +1000
> > Alistair Francis wrote:
> >
> > > From: Huai-Cheng Kuo
> >
> > Great to see you taking this forwards!
> >
> >
> > >
> > >
On Fri, 15 Sep 2023 18:01:30 +0100
Jonathan Cameron via wrote:
> On Thu, 14 Sep 2023 15:57:55 +0300
> Michael Tokarev wrote:
>
> > 13.09.2023 18:05, Jonathan Cameron via wrote:
> > > Michael Tsirkin observed that there were some unnecessarily
> > > long
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Reviewed-by: Michael Tokarev
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h | 3 ++-
Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/cxl/cxl_pci.h | 6 ++---
hw/cxl/cxl-component-utils.c | 49
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
matching size, allowing fixed values to be used for
Bring this read function inline with the others that do
check for unexpected size values.
Also reduces line lengths to sub 80 chars.
Signed-off-by: Jonathan Cameron
Reviewed-by: Philippe Mathieu-Daudé
---
hw/cxl/cxl-device-utils.c | 11 +++
1 file changed, 7 insertions(+), 4
v2:
Replace patch 2 with a change to use switch statements and some asserts
to improve code readability at same time as dealing with the overly
long lines.
Suggested-by: Michael S. Tsirkin
Michael observed that the CXL code regularly went above the 80 character
recommendation and in many
On Thu, 14 Sep 2023 15:57:55 +0300
Michael Tokarev wrote:
> 13.09.2023 18:05, Jonathan Cameron via wrote:
> > Michael Tsirkin observed that there were some unnecessarily
> > long lines in the CXL code in a recent review.
> > This patch is intended to rectify that where
On Fri, 15 Sep 2023 21:27:22 +1000
Alistair Francis wrote:
> From: Huai-Cheng Kuo
Great to see you taking this forwards!
>
> SPDM enables authentication, attestation and key exchange to assist in
> providing infrastructure security enablement. It's a standard published
> by the DMTF [1].
>
On Fri, 15 Sep 2023 21:27:23 +1000
Alistair Francis wrote:
> From: Wilfred Mallawa
>
> Setup Data Object Exchance (DOE) as an extended capability for the NVME
> controller and connect SPDM to it (CMA) to it.
>
> Signed-off-by: Wilfred Mallawa
> Signed-off-by: Alistair Francis
A few comments
On Fri, 15 Sep 2023 21:27:21 +1000
Alistair Francis wrote:
> Add all of the defined protocols/features from the PCIe-SIG
> "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
Which version of the specification? These references can rot.
Obviously it's below, but who knows if
On Thu, 14 Sep 2023 19:45:58 -0700
wrote:
> From: Ankit Agrawal
>
> During bootup, Linux kernel parse the ACPI SRAT to determine the PXM ids.
> This allows for the creation of NUMA nodes for each unique id.
>
> Insert a series of the unique PXM ids in the VM SRAT ACPI table. The
> range of
On Thu, 14 Sep 2023 19:45:56 -0700
wrote:
> From: Ankit Agrawal
>
> The CPU cache coherent device memory can be added as a set of
> NUMA nodes distinct from the system memory nodes. The Qemu currently
> do not provide a mechanism to support node creation for a vfio-pci
> device.
>
> Introduce
On Wed, 13 Sep 2023 16:22:28 +0300
Dmitry Frolov wrote:
> According to cxl_interleave_ways_enc(),
> fw->num_targets is allowed to be up to 16.
> This also corresponds to CXL specs.
> So, the fw->target_hbs[] array is iterated from 0 to 15.
> But it is staticaly declared of length 8.
> Thus, out
On Wed, 13 Sep 2023 13:36:46 +0200
Philippe Mathieu-Daudé wrote:
> Hi Dmitry,
>
> On 13/9/23 12:10, Dmitry Frolov wrote:
> > According to cxl_interleave_ways_enc(),
> > fw->num_targets is allowed to be up to 16.
> > This also corresponds to CXL specs.
> > So, the fw->target_hbs[] array is
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h | 3 ++-
include/hw/cxl/cxl_device.h| 5
Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_pci.h | 6 ++---
hw/cxl/cxl-component-utils.c | 49 --
Indexing has to be done into an array with the right size elements.
As such, the size parameter always matches the array element size
and can be used in place of the longer sizeof(*array)
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 8
1 file changed, 4
Suggested-by: Michael S. Tsirkin
Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.
This series is focused on tidying this up for the existing code so that
we can maintain the preferred formatting
Bring this read function inline with the others that do
check for unexpected size values.
Also reduces line lengths to sub 80 chars.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
Will be needed so there is a defined serial number for
information queries via the Switch CCI.
Signed-off-by: Jonathan Cameron
---
v2: Thanks to Philippe for review.
- Keep to a fixed offset for the serial number capability.
If it's not present then there will be a hole which is fine
Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
and CXL Type 3 end points.
Signed-off-by: Jonathan Cameron
---
v3: Factor out the hdm_inc changes to previous patch.
Fix use of encoded hdm count as if it were decoded in cxl-host.
Minor refactoring to make that path
In order to avoid having the size of the per HDM decoder register block
repeated in lots of places, create the register definitions for HDM
decoder 1 and use the offset between the first registers in HDM decoder 0 and
HDM decoder 1 to establish the offset.
Calculate in each function as this is
As an encoded version of these key configuration parameters is available
in a register, provide functions to extract it again so as to avoid
the need for duplicating the storage.
Whilst here update the _enc() function to include additional values
as defined in the CXL 3.0 specification. Whilst
There is no strong justification for keeping these in the header
so push them down into the associated cxl-component-utils.c file.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h |
v4: Thanks to Fan and Philippe for reviews.
- Add specification reference for interleave ways encodings
- Gathered tags.
Note I'm sending this out quicker than I normally would because I want
to post another series on top of it and the additional comment will add
some fuzz for that.
For
On Wed, 13 Sep 2023 13:10:56 +0300
Dmitry Frolov wrote:
> According to cxl_interleave_ways_enc(),
> fw->num_targets is allowed to be up to 16.
> This also corresponds to CXL specs.
> So, the fw->target_hbs[] array is iterated from 0 to 15.
> But it is staticaly declared of length 8.
> Thus, out
On Tue, 12 Sep 2023 18:08:44 +
Fan Ni wrote:
> On Mon, Sep 11, 2023 at 12:43:13PM +0100, Jonathan Cameron wrote:
>
> > Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
> > and CXL Type 3 end points.
> >
> > Signed-off-by: Jonathan Cameron
> >
> > ---
>
> One
On Wed, 13 Sep 2023 08:53:55 +0200
Philippe Mathieu-Daudé wrote:
> On 11/9/23 13:43, Jonathan Cameron wrote:
> > In order to avoid having the size of the per HDM decoder register block
> > repeated in lots of places, create the register definitions for HDM
> > decoder 1 and use the offset
On Tue, 12 Sep 2023 17:20:05 +
Fan Ni wrote:
> On Mon, Sep 11, 2023 at 12:43:11PM +0100, Jonathan Cameron wrote:
>
> > As an encoded version of these key configuration parameters is available
> > in a register, provide functions to extract it again so as to avoid
> > the need for
On Tue, 12 Sep 2023 21:12:45 +
Fan Ni wrote:
> On Mon, Sep 04, 2023 at 05:18:46PM +0100, Jonathan Cameron wrote:
>
> > From: Dave Jiang
> >
> > Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
> > ID value of 0 in all cases. The enabling is for _DSM plumbing
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