Hi Alex,
I've tried to use
make check-tcg CORE=test_kc705_be CROSS_CC_GUEST=xtensa-test_kc705_be-elf-gcc
to run TCG tests for a big-endian xtensa core. I thought the following change
would be sufficient to do it:
---8<---
diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
On Fri, Oct 1, 2021 at 10:15 AM Richard Henderson
wrote:
>
> The fallback code in raise_sigsegv is sufficient for xtensa.
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.h
On Tue, Sep 14, 2021 at 7:35 AM Daniel P. Berrangé wrote:
>
> Change the "info tlb" implementation to use the format_tlb callback.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> target/xtensa/cpu.h| 2 +-
> target/xtensa/mmu_helper.c | 126 +
>
On Wed, Sep 15, 2021 at 12:32 AM Philippe Mathieu-Daudé wrote:
> On 9/14/21 4:20 PM, Daniel P. Berrangé wrote:
> > if ((flags & CPU_DUMP_FPU) &&
> > xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
> > -qemu_fprintf(f, "\n");
> > +
On Mon, Aug 2, 2021 at 9:15 PM Richard Henderson
wrote:
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.c| 2 +-
> target/xtensa/helper.c | 30 +++---
> 2 files changed, 16 insertions(+), 16 deletions(-)
A
; 1 file changed, 39 insertions(+), 45 deletions(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
On Sun, Jun 20, 2021 at 6:34 PM Richard Henderson
wrote:
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/translate.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
insertions(+)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
inux-user/qemu.h| 7 +++
> linux-user/elfload.c | 17 +
> linux-user/signal.c | 3 +++
> 3 files changed, 27 insertions(+)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
On Tue, Jun 15, 2021 at 6:12 PM Richard Henderson
wrote:
>
> Create and record the rt signal trampoline.
> Use it when the guest does not use SA_RESTORER.
>
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> linux-user/xtensa/target_signal.h | 2 ++
>
updates for v6.1:
- don't generate extra EXCP_DEBUG on exception
- fix l32ex access ring
- clean up unaligned access
Max Filippov (3):
target/xtensa: don't generate extra EXCP_DEBUG on exception
target/xtensa: fix access
in
an exception when the correct implementation would've succeeded.
In no case it would allow memory access that would've raised an
exception in the correct implementation.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Max Filippov
---
Changes v1->v2:
- add correctness/secur
and
alignment requirements in single parameter.
Drop condition from xtensa_cpu_do_unaligned_access and replace it with
assertion.
Add a test.
Suggested-by: Philippe Mathieu-Daudé
Suggested-by: Richard Henderson
Signed-off-by: Max Filippov
---
Changes v3->v4:
- do additional clea
l32ex does memory access as all regular load/store operations at CRING
level. Fix apparent pasto from l32e that caused it to use RING instead.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Richard,
On Tue, May 18, 2021 at 1:11 PM Richard Henderson
wrote:
> On 5/17/21 3:52 PM, Max Filippov wrote:
> > @@ -1784,10 +1770,11 @@ static void translate_l32e(DisasContext *dc, const
> > OpcodeArg arg[],
> > const uint32_t par[])
>
.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Max Filippov
---
Changes v2->v3:
- drop assertion for !XTENSA_OPTION_HW_ALIGNMENT from
xtensa_cpu_do_unaligned_access to correctly handle acquire/release
intsructions;
- add tests for acquire/release instructions.
Changes v1->v2:
- cor
.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Max Filippov
---
Changes v1->v2:
- correctly handle case of !XCHAL_UNALIGNED_*_EXCEPTION in the test
target/xtensa/helper.c | 14 +--
target/xtensa/translate.c | 108
tests/tcg/xtensa/test_load_store.S |
.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Max Filippov
---
target/xtensa/helper.c | 14 +--
target/xtensa/translate.c | 108 ++--
tests/tcg/xtensa/test_load_store.S | 156 +
3 files changed, 217 insertions(+), 61 deletions
On Mon, May 17, 2021 at 9:54 AM Philippe Mathieu-Daudé wrote:
>
> On 5/17/21 5:35 PM, Max Filippov wrote:
> > On Mon, May 17, 2021 at 8:25 AM Max Filippov wrote:
> >>
> >> On Mon, May 17, 2021 at 6:10 AM Philippe Mathieu-Daudé
> >> wrote:
> >&g
On Mon, May 17, 2021 at 8:25 AM Max Filippov wrote:
>
> On Mon, May 17, 2021 at 6:10 AM Philippe Mathieu-Daudé
> wrote:
> >
> > On 5/17/21 2:11 PM, Max Filippov wrote:
> > > On Mon, May 17, 2021 at 4:50 AM Max Filippov wrote:
> > >>
> > >>
On Mon, May 17, 2021 at 6:10 AM Philippe Mathieu-Daudé wrote:
>
> On 5/17/21 2:11 PM, Max Filippov wrote:
> > On Mon, May 17, 2021 at 4:50 AM Max Filippov wrote:
> >>
> >> Hi Philippe,
> >>
> >> On Sun, May 16, 2021 at 10:05 PM Philip
On Mon, May 17, 2021 at 4:50 AM Max Filippov wrote:
>
> Hi Philippe,
>
> On Sun, May 16, 2021 at 10:05 PM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Max,
> >
> > On Mon, Jan 14, 2019 at 8:52 AM Max Filippov wrote:
> > >
> > > Move re
Hi Philippe,
On Sun, May 16, 2021 at 10:05 PM Philippe Mathieu-Daudé
wrote:
>
> Hi Max,
>
> On Mon, Jan 14, 2019 at 8:52 AM Max Filippov wrote:
> >
> > Move remaining non-HELPER functions from op_helper.c to helper.c.
> > No functional changes.
>
ecise single-stepping after an exception")
ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt")
Drop exception state tracking/extra EXCP_DEBUG generation code.
Signed-off-by: Max Filippov
---
This patch depends on the "target/xtensa: Make sure that tb->size
On Thu, Apr 15, 2021 at 8:03 AM Peter Maydell wrote:
>
> On Thu, 15 Apr 2021 at 02:24, Max Filippov wrote:
> > I see a few places where target/xtensa may do that. E.g. it does that on
> > entry
> > to an exception handler to allow for debugging its first instruct
> 1 file changed, 3 insertions(+)
Tested-by: Max Filippov
Acked-by: Max Filippov
--
Thanks.
-- Max
On Wed, Apr 14, 2021 at 12:43 PM Richard Henderson
wrote:
>
> On 4/14/21 11:03 AM, Max Filippov wrote:
> > On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote:
> >> On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote:
> >>> Did you double-check the xten
On Wed, Apr 14, 2021 at 9:51 AM Ilya Leoshkevich wrote:
> On Wed, 2021-04-14 at 16:48 +0200, David Hildenbrand wrote:
> > Did you double-check the xtensa issue?
>
> Oh, I'm sorry, I completely forgot about that one. I just ran the
> test locally, and apparently it fails because of this new
up all available xtensa core definitions;
- don't modify Makefile.objs in import_core.sh;
- add sed rule to import_core.sh to make xtensa_modules variable static.
Max Filippov (2):
target/xtensa: fix meson.build rule for xtensa
import_core.sh tries to change Makefile.objs when importing new xtensa
core, but that file no longer exists. Rewrite meson.build rule to pick
up all source files that match core-*.c pattern and drop commands that
change Makefile.objs.
Cc: qemu-sta...@nongnu.org # v5.2.0
Signed-off-by: Max
On Tue, Mar 30, 2021 at 1:32 PM Richard Henderson
wrote:
> On 3/30/21 1:30 AM, Max Filippov wrote:
> > -grep -q core-${NAME}.o "$BASE"/Makefile.objs || \
> > -echo "obj-y += core-${NAME}.o" >> "$BASE"/Makefile.objs
> > +grep
import_core.sh was not updated to change meson.build when new xtensa
core is imported. Fix that.
Cc: qemu-sta...@nongnu.org # v5.2.0
Signed-off-by: Max Filippov
---
target/xtensa/import_core.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/xtensa/import_core.sh
xtensa_modules variable defined in each xtensa-modules.c.inc is only
used locally by the including file. Make it static.
Signed-off-by: Max Filippov
---
target/xtensa/import_core.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh
es.c.inc | 2 +-
> .../xtensa-modules.c.inc | 2 +-
> .../core-test_kc705_be/xtensa-modules.c.inc | 2 +-
> .../core-test_mmuhifi_c3/xtensa-modules.c.inc | 2 +-
> 21 files changed, 125 insertions(+), 127 deletions(-)
For the xtensa part:
Acked-by: Ma
;
> -intisa->interface_lookup_table = 0;
> -}
> +g_free(intisa->interface_lookup_table);
> +intisa->interface_lookup_table = 0;
Ditto.
>
> -if (intisa->funcUnit_lookup_table) {
> -free(intisa->funcUnit_lookup_table);
> -intisa->funcUnit_lookup_table = 0;
> -}
> +g_free(intisa->funcUnit_lookup_table);
> +intisa->funcUnit_lookup_table = 0;
Ditto.
With the above changes:
Acked-by: Max Filippov
--
Thanks.
-- Max
fi01_get_memory() helper.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/xtensa/xtfpga.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
>
> Add a default value for 'rf' to prevented the warning.
I don't see it doing default build with gcc 8.3. But then I don't see
-Wmaybe-uninitialized in the compiler command line either.
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
> ---
> Cc: Max Filippov
> ---
Linux userspace always sees coprocessors as enabled. CPENABLE register
and coprocessor exceptions are used internally by the kernel to manage
lazy coprocessor context switch. None of it is needed for linux-user.
Always enable all coprocessors for user emulation.
Signed-off-by: Max Filippov
On Mon, Aug 24, 2020 at 2:33 PM Peter Maydell wrote:
> On Sat, 22 Aug 2020 at 20:48, Max Filippov wrote:
> > On Sat, Aug 22, 2020 at 3:20 AM Philippe Mathieu-Daudé
> > wrote:
> > >
> > > Where does that come from?
> >
> > Generated by xtensa process
On Sat, Aug 22, 2020 at 3:20 AM Philippe Mathieu-Daudé wrote:
> On 8/21/20 10:50 PM, Max Filippov wrote:
> > please pull the following batch of updates for target/xtensa.
>
> 3.12MiB of generated data...
>
> Where does that come from?
Generated by xtensa processor gene
FPU.
----
Max Filippov (24):
target/xtensa: make opcode properties more dynamic
target/xtensa: implement NMI support
softfloat: make NO_SIGNALING_NANS runtime property
softfloat: pass float_status pointer to pick
On Fri, Aug 21, 2020 at 9:24 AM Peter Maydell wrote:
> On Thu, 13 Aug 2020 at 00:24, Max Filippov wrote:
> > please pull the following batch of updates for target/xtensa.
>
> Hi; this conflicts with the meson buildsystem merge, I'm
> afraid -- can you rebase and res
implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.
Max Filippov (24):
target/xtensa: make opcode properties more dynamic
target/xtensa: implement NMI support
On Thu, Jul 23, 2020 at 2:25 PM Max Filippov wrote:
>
> On Thu, Jul 23, 2020 at 2:04 PM Filip Bozuta wrote:
> >
> > This patch introduces missing target types ('target_flag_t', 'target_cc_t',
> > 'target_speed_t') in a few 'termibts.h' header files. Also, two missing
&
On Thu, Jul 23, 2020 at 2:04 PM Filip Bozuta wrote:
>
> This patch introduces missing target types ('target_flag_t', 'target_cc_t',
> 'target_speed_t') in a few 'termibts.h' header files. Also, two missing
> values ('TARGET_IUTF8' and 'TARGET_EXTPROC') were also added. These values
> were also
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 47 +++--
1 file changed, 34 insertions(+), 13
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 123
1 file changed, 123 insertions(+)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 9d59c1815a9e
Test exact division/sqrt DFPU sequences.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_div.S | 82
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +
2 files changed, 158 insertions(+)
create mode 100644 tests/tcg/xtensa
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_conv.S | 299 ---
1 file changed, 155 insertions(+), 144 deletions(-)
diff --git a/tests
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/fpu.h| 142
tests/tcg/xtensa/test_fp0_arith.S | 178 ++
2
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp1.S | 62 -
1 file
Test that madd doesn't do rounding after multiplication.
Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for FPU2000 and DFPU
tests/tcg/xtensa/test_fp0_arith.S | 104 ++
1 f
precision opcodes. Add 64-bit register file.
Add 64-bit values dumping to the xtensa_cpu_dump_state.
Signed-off-by: Max Filippov
---
Changes v3->v4:
- split into two patches
- add single-precision helpers that call set_use_first_nan
- call fpu2k helpers or the new helper depending on whether D
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b
Add test for basic double precision opcode properties.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for DFPU
- fix test names in test_dfp0_arith.S
tests/tcg/xtensa/test_dfp0_arith.S | 162 +
1 file changed, 162 insertions(+)
create m
BR registers used in FPU comparison opcodes are available as opcode
arguments for translators. Use them. This simplifies comparison helpers
interface and makes them usable in FLIX bundles.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/fpu_helper.c | 42
accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov
---
Changes v3->v4:
- new patch split from the next one
target/xtensa/cpu.h |
, most of them as nops, but the results of
div/sqrt sequences is preserved.
Signed-off-by: Max Filippov
---
target/xtensa/fpu_helper.c | 24 +
target/xtensa/helper.h | 4 ++
target/xtensa/translate.c | 104 +
3 files changed, 132 insertions
Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 64 +++
1 file changed, 32 insertions(+), 32 deletions(-)
diff
FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.
Signed-off-by: Max Filippov
Add _s suffix to all FPU2000 opcode translators and helpers that also
have double-precision variant to unify naming and allow adding DFPU
implementations. Add _fpu2k_ to the names of helpers that will have
different implementation for the DFPU .
Reviewed-by: Richard Henderson
Signed-off-by: Max
Register file name may not uniquely identify a register file in the set
of configurations. E.g. floating point registers may have different size
in different configurations. Use register file geometry as additional
identifier.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 2
y: Richard Henderson
Signed-off-by: Max Filippov
---
fpu/softfloat-specialize.inc.c | 30 --
fpu/softfloat.c | 2 +-
include/fpu/softfloat-helpers.h | 5 +
include/fpu/softfloat-types.h | 1 +
4 files changed, 31 insertions(+), 7 deletions(-)
diff -
implementations coexist.
Cc: Peter Maydell
Cc: "Alex Bennée"
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
Changes v1->v2:
- use inline function for no_signaling_nans property to allow for
con
istent with other
core names
Changes v1->v2:
- use inline function for no_signaling_nans property to allow for
constant folding on architectures that have this property fixed.
Max Filippov (22):
softfloat: make NO_SIGNALING_NANS runtime property
softfloat: pass float_status pointer t
flag is always set when (a * b) produces NaN.
Cc: Peter Maydell
Cc: "Alex Bennée"
Cc: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
Changes v2->v3:
- handle infzero case in pickNaNMulAdd properly and reword commit
message
fpu/softfloat-speciali
On Wed, Jul 8, 2020 at 5:19 PM Richard Henderson
wrote:
> Do I read that right,
[...]
> means that if DFP is present, float64 has use_first_nan, but float32 does
> not?!?
That's correct. And float64 madd.d/msub.d again don't have it.
> What in the world is going on?
My thoughts exactly. What
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 123
1 file changed, 123 insertions(+)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 9d59c1815a9e
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/fpu.h| 142
tests/tcg/xtensa/test_fp0_arith.S | 178 ++
2
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b
Register file name may not uniquely identify a register file in the set
of configurations. E.g. floating point registers may have different size
in different configurations. Use register file geometry as additional
identifier.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 2
flag is always set when (a * b) produces NaN.
Cc: Peter Maydell
Cc: "Alex Bennée"
Cc: Richard Henderson
Signed-off-by: Max Filippov
---
Changes v2->v3:
- handle infzero case in pickNaNMulAdd properly and reword commit
message
fpu/softfloat-specialize.inc.c | 26
Pass float_status structure pointer to the pickNaN so that
machine-specific settings are available to NaN selection code.
Add use_first_nan property to float_status and use it in Xtensa-specific
pickNaN.
Cc: Peter Maydell
Cc: "Alex Bennée"
Reviewed-by: Alex Bennée
Signed-off-by: Ma
implementations coexist.
Cc: Peter Maydell
Cc: "Alex Bennée"
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Max Filippov
---
Changes v1->v2:
- use inline function for no_signaling_nans property to allow for
constant folding on architectures that have
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 47 +++--
1 file changed, 34 insertions(+), 13
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp1.S | 62 -
1 file
Add test for basic double precision opcode properties.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for DFPU
- fix test names in test_dfp0_arith.S
tests/tcg/xtensa/test_dfp0_arith.S | 162 +
1 file changed, 162 insertions(+)
create m
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_conv.S | 299 ---
1 file changed, 155 insertions(+), 144 deletions(-)
diff --git a/tests
precision opcodes. Add 64-bit register file.
Add 64-bit values dumping to the xtensa_cpu_dump_state.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.c |4 +
target/xtensa/cpu.h |4 +
target/xtensa/fpu_helper.c | 252 +++-
target/xtensa/helper.h | 29
Add _s suffix to all FPU2000 opcode translators and helpers that also
have double-precision variant to unify naming and allow adding DFPU
implementations. Add _fpu2k_ to the name of wur_fcr helper to make space
for the DFPU wur_fcr helper.
Reviewed-by: Richard Henderson
Signed-off-by: Max
Test exact division/sqrt DFPU sequences.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_div.S | 82
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +
2 files changed, 158 insertions(+)
create mode 100644 tests/tcg/xtensa
, most of them as nops, but the results of
div/sqrt sequences is preserved.
Signed-off-by: Max Filippov
---
target/xtensa/fpu_helper.c | 24 +
target/xtensa/helper.h | 4 ++
target/xtensa/translate.c | 104 +
3 files changed, 132 insertions
Test that madd doesn't do rounding after multiplication.
Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for FPU2000 and DFPU
tests/tcg/xtensa/test_fp0_arith.S | 104 ++
1 f
BR registers used in FPU comparison opcodes are available as opcode
arguments for translators. Use them. This simplifies comparison helpers
interface and makes them usable in FLIX bundles.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/fpu_helper.c | 42
Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 64 +++
1 file changed, 32 insertions(+), 32 deletions(-)
diff
FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.
Signed-off-by: Max Filippov
>v2:
- use inline function for no_signaling_nans property to allow for
constant folding on architectures that have this property fixed.
Max Filippov (21):
softfloat: make NO_SIGNALING_NANS runtime property
softfloat: pass float_status pointer to pickNaN
softfloat: add xtensa speciali
On Wed, Jul 8, 2020 at 9:07 AM Richard Henderson
wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > pickNaNMulAdd logic on Xtensa is the same as pickNaN when applied to
> > the expression (a * b) + c. So with two pickNaN variants there must be
> > two pickNaNMulAdd va
On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
> > +{
> > +set_use_first_nan(true, >fp_status);
> > +return float64_add(a, b, >f
On Wed, Jul 8, 2020 at 9:14 AM Richard Henderson
wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > +if (arg_copy[i].arg->num_bits <= 32) {
> > +temp = tcg_temp_local_new_i32();
> > +tcg_gen
Switch to the prebuilt xtensa toolchains release 2020.07.
Drop csp toolchain as the csp core is not a part of QEMU.
Add de233_fpu and dsp3400 toolchains to enable DFPU and FPU2000 tests.
Signed-off-by: Max Filippov
---
tests/docker/dockerfiles/debian-xtensa-cross.docker | 6 +++---
1 file
On Tue, Jul 7, 2020 at 12:21 PM Alex Bennée wrote:
> Well it ran some xtensa tests thanks to the docker cross compiler
> support. Do you know what toolchains we need?
>
> Currently we have the following:
>
> ENV CPU_LIST csp dc232b dc233c
> ENV TOOLCHAIN_RELEASE 2018.02
>
> RUN for cpu in
NULL to ignore these values. Remove such unused variables and
> pass NULL instead from callers that don't need these.
>
> Signed-off-by: BALATON Zoltan
> ---
[...]
> hw/xtensa/sim.c| 3 +--
> hw/xtensa/xtfpga.c | 3 +--
For Xtensa parts:
Acked-by: Max Filippov
--
Thanks.
-- Max
implementations coexist.
Cc: Peter Maydell
Cc: "Alex Bennée"
Signed-off-by: Max Filippov
---
Changes v1->v2:
- use inline function for no_signaling_nans property to allow for
constant folding on architectures that have this property fixed.
fpu/softfloat-specialize
On Tue, Jul 7, 2020 at 4:31 AM Alex Bennée wrote:
> I've only looked at the softfloat bits as I'm not familiar with xtensa
Thanks for taking a look!
> at all. However you can have a vague:
>
> Tested-by: Alex Bennée
>
> for the series - congratulations you pass your own tests ;-)
Unless
Add test for basic double precision opcode properties.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_dfp0_arith.S | 153 +
1 file changed, 153 insertions(+)
create mode 100644 tests/tcg/xtensa/test_dfp0_arith.S
diff --git a/tests/tcg/xtensa
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 123
1 file changed, 123 insertions(+)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 9d59c1815a9e
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp1.S | 62 -
1 file
Test exact division/sqrt DFPU sequences.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_div.S | 82
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +
2 files changed, 158 insertions(+)
create mode 100644 tests/tcg/xtensa
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b
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