for the upper interval boundary and once for the lower. Fix
that by excluding lower interval boundary from the condition.
This doesn't have user-visible effect, because CCOMPARE reload always
causes CCOUNT increment followed by current timer interrupt reset.
Signed-off-by: Max Filippov jcmvb...@gmail.com
There's new interrupt type in the recent Xtensa releases that may appear
in configuration overlay. Add definition so that new cores that use it
could be automatically imported.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 1 +
target-xtensa/overlay_tool.h | 1
configuration and pass it through the C preprocessor.
While at it clean up tabs and align the initial stack on 16 bytes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/Makefile| 10 +++-
tests/tcg/xtensa/linker.ld | 112 -
tests/tcg/xtensa
Hi Peter,
On Fri, Sep 12, 2014 at 6:23 AM, Peter Maydell peter.mayd...@linaro.org wrote:
The current implementation of watchpoints requires that they
have a power of 2 length which is not greater than TARGET_PAGE_SIZE
and that their address is a multiple of their length. Watchpoints
on ARM
With commit 05068c0dfb5b 'exec.c: Relax restrictions on watchpoint length
and alignment' it's no longer possible to set 1-byte-long watchpoint
because of incorrect address range check.
Fix that by changing condition that checks for address wraparound.
Signed-off-by: Max Filippov jcmvb
Hi Peter,
On Fri, Sep 12, 2014 at 11:04 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
GDB assumes that watchpoint set via the gdbstub remote protocol will
behave in the same way as hardware watchpoints for the target. In
particular, whether the CPU stops with the PC before or after the
On Sat, Sep 13, 2014 at 9:45 AM, Richard Henderson r...@twiddle.net wrote:
Cc: Max Filippov jcmvb...@gmail.com
Signed-off-by: Richard Henderson r...@twiddle.net
---
cpu-exec.c | 6 --
target-xtensa/cpu-qom.h | 1 +
target-xtensa/cpu.c | 1 +
target-xtensa/helper.c
| 6 ++
3 files changed, 17 insertions(+), 5 deletions(-)
Reviewed-by: Max Filippov jcmvb...@gmail.com
--
Thanks.
-- Max
On Mon, Sep 15, 2014 at 9:15 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 15 September 2014 20:59, Max Filippov jcmvb...@gmail.com wrote:
I've tested xtensa part and have noticed no difference with or without
this patch:
gdb connected to qemu gdbstub always stops right after
, 3 insertions(+), 3 deletions(-)
Acked-by: Max Filippov jcmvb...@gmail.com
--
Thanks.
-- Max
movcond has its cond argument first, not last. Fix that in
documentation.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tcg/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/README b/tcg/README
index a550ff1..69f3456 100644
--- a/tcg/README
+++ b/tcg/README
movcond and brcond have its cond argument first. Fix that in
documentation.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Changes v1 - v2:
- fix similar brcond issue
tcg/README | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/README b/tcg/README
index a550ff1
On Tue, Sep 9, 2014 at 4:12 PM, Richard Henderson r...@twiddle.net wrote:
On 09/09/2014 04:02 PM, Max Filippov wrote:
movcond has its cond argument first, not last. Fix that in
documentation.
No. The README is supposed to be documenting the *opcode* argument ordering,
which really does
Hi Alex,
On Thu, Aug 21, 2014 at 1:16 PM, Alexander Graf ag...@suse.de wrote:
On 12.08.14 06:22, Max Filippov wrote:
load_uimage_at loads kernel image at the specified address instead of
the address recorded in the uImage header.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb
On Tue, Aug 12, 2014 at 8:22 AM, Max Filippov jcmvb...@gmail.com wrote:
Hi,
this series fixes loading uImage kernels on MMUv2 xtensa cores.
U-boot for xtensa always treats uImage load address as virtual address.
This is important when booting uImage on xtensa core with MMUv2, because
MMUv2
Extract uImage header loader and allow using it from the rest of the
code.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/core/loader.c| 37 +
include/hw/loader.h | 2 ++
2 files changed, 31 insertions(+), 8 deletions
load_uimage_at loads kernel image at the specified address instead of
the address recorded in the uImage header.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/core/loader.c| 25 +++--
include/hw/loader.h | 2 ++
2 files changed, 21
at the translated address. This fixes booting uImage kernels
on dc232b and other MMUv2 cores.
Cc: qemu-sta...@nongnu.org
Reported-by: Waldemar Brodkorb m...@waldemar-brodkorb.de
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtfpga.c | 9 -
1 file changed, 8 insertions(+), 1
new functions: load_uboot_image_header that loads uImage header
and load_uimage_at that loads uImage at the specified address, and use them
to query uImage load address and load uImage at the correctly translated
address.
Max Filippov (3):
hw/core/loader: implement load_uboot_image_header
hw/core
Hi Bastian,
On Mon, Jul 7, 2014 at 10:13 PM, Bastian Koppelmann
kbast...@mail.uni-paderborn.de wrote:
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub/mov and sh.
Signed-off-by: Bastian Koppelmann
On Sun, Jun 29, 2014 at 7:43 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 28 June 2014 23:49, Max Filippov jcmvb...@gmail.com wrote:
Hi Peter,
please pull my current target-xtensa patch queue.
The following changes since commit d4cba13bdf251baeedb36b87c1e9f6766773e380:
tcg/ppc
to boot region for KC705;
- clean up boot parameters passing;
- add uImage, DTB and initrd support.
Max Filippov (10):
hw/xtensa/xtfpga: fix FLASH mapping to boot region for KC705
hw/xtensa: remove extraneous xtensa_ prefix
On KC705 bootloader area is located at FLASH offset 0x0600, not 0 as
on older xtfpga boards.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtensa_lx60.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/xtensa/xtensa_lx60
Import bootparam tag names from linux/arch/xtensa/include/asm/bootparam.h
No functional changes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/bootparam.h | 10 ++
hw/xtensa/xtfpga.c| 6 +++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/xtensa
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtfpga.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 01825d6..a2dff5a 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -180,6 +180,7 @@ static
Provide a simple bootloader code at the reset address that jumps to the
loaded image entry point when it's not equal to the reset address. This
is needed because the old method of setting pc doesn't work due to cpu
reset done after the machine setup.
Signed-off-by: Max Filippov jcmvb...@gmail.com
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtfpga.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 0e0d825..01825d6 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -37,6 +37,7 @@
#include hw
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/sim.c| 6 --
hw/xtensa/xtfpga.c | 10 ++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index 89da43c..9642bf5 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtfpga.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 75bc479..0aa3eeb 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -174,9 +174,10 @@ static void
While at it rename lx60 (named after the first board of the family) to
more generic xtfpga (the family name).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/Makefile.objs | 4 ++--
hw/xtensa/{xtensa_bootparam.h = bootparam.h} | 0
hw/xtensa/{xtensa_sim.c
Hi,
this series refactors boot parameters handling for xtensa xtfpga boards
and implements uImage, FDT and initrd loading.
Max Filippov (9):
hw/xtensa: remove extraneous xtensa_ prefix from file names
hw/xtensa: replace fprintfs with error_report
hw/xtensa/xtfpga: retrieve parameters from
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/bootparam.h | 9 +
hw/xtensa/xtfpga.c| 9 -
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/xtensa/bootparam.h b/hw/xtensa/bootparam.h
index e839bee..955f4e8 100644
--- a/hw/xtensa/bootparam.h
+++ b
Separate filling first/last tag and size calculation from the kernel
command line setup.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/bootparam.h | 5 +
hw/xtensa/xtfpga.c| 28
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git
cross-page jumps/calls at the end of TB;
- add tests for TBs and instructions crossing page boundary.
Max Filippov (3):
target-xtensa: fix cross-page jumps/calls at the end of TB
target-xtensa: completely clean TLB between
Move cross-page jump check to gen_jump_slot and use tb-pc instead of
dc-pc to check for cross-page jumps.
When TB ends at the page boundary dc-pc points to the next page
allowing chaining to TBs in it.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa
On Tue, May 20, 2014 at 3:17 PM, Max Filippov jcmvb...@gmail.com wrote:
Move cross-page jump check to gen_jump_slot and use tb-pc instead of
dc-pc to check for cross-page jumps.
When TB ends at the page boundary dc-pc points to the next page
allowing chaining to TBs in it.
Cc: qemu-sta
Hi,
this series fixes cross-page TB linking bug in target-xtensa that managed
to survive for a major release period. With this bug fixed it is finally
possible to build linux kernel under xtensa linux running in system mode
QEMU (but it may take a couple of days to complete).
Max Filippov (3
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/test_mmu.S | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S
index 099031f..37174b9 100644
--- a/tests/tcg/xtensa/test_mmu.S
Use tb-pc instead of dc-pc to check for cross-page jumps.
When TB translation stops at the page boundary dc-pc points to the next
page allowing chaining to TBs in it, which is wrong.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 4
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/test_mmu.S | 220
1 file changed, 220 insertions(+)
diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S
index 37174b9..58c5bca 100644
--- a/tests/tcg/xtensa
On Thu, May 15, 2014 at 11:16 AM, Li, ZhenHua zhen-h...@hp.com wrote:
Maybe it should be 4 bytes for 4096 (0x1000).
I'd say that 2 bytes should be enough, but actually I don't see
why anybody would care in that function how many bytes it is.
On 05/13/2014 04:19 PM, Max Filippov wrote:
On Tue
On Tue, May 13, 2014 at 11:09 AM, Li, Zhen-Hua zhen-h...@hp.com wrote:
From: Li, ZhenHua zhen-h...@hp.com
There is some runtime check for max cpu count. Make them support 4096 cpus.
Signed-off-by: Li, ZhenHua zhen-h...@hp.com
---
hw/i386/acpi-build.c | 8
1 file changed, 4
On Fri, Apr 18, 2014 at 12:48 PM, Pavel Dovgaluk
pavel.dovga...@ispras.ru wrote:
You can insert tracing code into the functions from the
“include\exec\softmmu_template.h” file: like helper_le_ld_name,
helper_le_st_name and so on.
It's not enough, you also need to disable memory access fast
Hi Andreas,
On Mon, Mar 10, 2014 at 4:15 AM, Andreas Färber afaer...@suse.de wrote:
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 4265378..8641e5d 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -54,7 +54,7 @@ static void
On Mon, Mar 10, 2014 at 4:15 AM, Andreas Färber afaer...@suse.de wrote:
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 624ef54..612d3bf 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -730,21 +730,24 @@ void xtensa_tlb_set_entry_mmu(const
Cc: Max Filippov jcmvb...@gmail.com
Signed-off-by: Stefan Weil s...@weilnetz.de
---
coroutine-win32.c |1 +
include/net/eth.h |2 +-
include/sysemu/os-win32.h |3 +--
target-xtensa/xtensa-semi.c |1 +
ui/vnc-enc-tight.c |1 +
5 files
.
Max Filippov (10):
hw/xtensa: add support for ML605 and KC705 FPGA board
opencores_eth: flush queue whenever can_receive can go from false to true
target-xtensa: add RRRI4 opcode format fields
target-xtensa: add basic checks to dcache opcodes
Hello,
this series collapses standard core configuration statements into a single
macro and adds support for two new special registers.
Max Filippov (2):
target-xtensa: refactor standard core configuration
target-xtensa: provide HW confg ID registers
target-xtensa/core-dc232b.c | 8
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.c | 2 ++
target-xtensa/cpu.h | 4
target-xtensa/overlay_tool.h | 9 -
target-xtensa/translate.c| 9 +++--
4 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/target-xtensa
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/core-dc232b.c | 8 +---
target-xtensa/core-dc233c.c | 8
Hi,
On Thu, Feb 13, 2014 at 11:34 AM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
Hi!
I am debugging spapr-vlan and hit the following issue.
When I run QEMU as below, the kernel's DHCP client does not continue till I
hit any key in console. If I replace spapr-vlan with
On Thu, Feb 13, 2014 at 2:34 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 02/13/2014 07:40 PM, Max Filippov wrote:
Hi,
On Thu, Feb 13, 2014 at 11:34 AM, Alexey Kardashevskiy a...@ozlabs.ru
wrote:
Hi!
I am debugging spapr-vlan and hit the following issue.
When I run QEMU as below
On Thu, Feb 13, 2014 at 5:42 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 02/13/2014 11:23 PM, Max Filippov wrote:
On Thu, Feb 13, 2014 at 2:34 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 02/13/2014 07:40 PM, Max Filippov wrote:
Hi,
On Thu, Feb 13, 2014 at 11:34 AM, Alexey
On Thu, Feb 13, 2014 at 6:06 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 02/14/2014 01:02 AM, Max Filippov wrote:
On Thu, Feb 13, 2014 at 5:42 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 02/13/2014 11:23 PM, Max Filippov wrote:
On Thu, Feb 13, 2014 at 2:34 PM, Alexey Kardashevskiy
This encoding is used by cache instructions.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dc5e78f..b0b7fa0 100644
--- a/target-xtensa
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Signed-off-by: Max Filippov jcmvb...@gmail.com
Hello,
this series adds basic checks (privilege level, address validity, windowed
register validation) to all cache opcodes. This improves emulation quality
and allows to debug cache-related issues that happen on real hardware.
Max Filippov (6):
target-xtensa: add RRRI4 opcode format fields
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/macros.inc | 4
tests/tcg/xtensa/test_mmu.S | 4 ++--
2 files changed, 6 insertions(+), 2
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/Makefile | 11 +++
tests/tcg/xtensa/macros.inc | 2 ++
tests/tcg
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/Makefile | 1 +
tests/tcg/xtensa/test_cache.S | 97 +++
2
On Tue, Feb 11, 2014 at 6:35 PM, Samuel Thibault
samuel.thiba...@gnu.org wrote:
Eric Blake, le Tue 11 Feb 2014 06:50:54 -0700, a écrit :
On 02/11/2014 06:08 AM, Samuel Thibault wrote:
This is a respin of IPv6 in Qemu -net user mode.
When sending a new revision of a long series, it's easier
On Tue, Feb 11, 2014 at 6:42 PM, Max Filippov jcmvb...@gmail.com wrote:
On Tue, Feb 11, 2014 at 6:35 PM, Samuel Thibault
samuel.thiba...@gnu.org wrote:
Eric Blake, le Tue 11 Feb 2014 06:50:54 -0700, a écrit :
On 02/11/2014 06:08 AM, Samuel Thibault wrote:
This is a respin of IPv6 in Qemu
On Sun, Feb 2, 2014 at 1:50 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 02/02/2014 02:47, Max Filippov ha scritto:
Hello,
is there any way to notify networking core that adapter's
NetClientInfo::can_receive return value is about to change from 0 to 1?
Yes, qemu_flush_queued_packets
arrives but the
current RX descriptor is not empty.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/net/opencores_eth.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c
index 4118d54
Hello,
is there any way to notify networking core that adapter's
NetClientInfo::can_receive return value is about to change from 0 to 1?
I'm trying to talk to DHCP server from the recent (2014.01) u-boot running
in the xtensa system emulation over the tap interface. On the guest I see
the
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa/xtensa_lx60.c | 51 +
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/hw/xtensa/xtensa_lx60.c b/hw/xtensa/xtensa_lx60.c
index 22e124d..49c58d1 100644
--- a/hw/xtensa
Hi Xin,
On Thu, Jan 23, 2014 at 11:49 PM, Xin Tong trent.t...@gmail.com wrote:
[...]
diff --git a/cputlb.c b/cputlb.c
index b533f3f..03a048a 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -34,6 +34,22 @@
/* statistics */
int tlb_flush_count;
+/* swap the 2 given TLB entries as well as their
On Fri, Jan 24, 2014 at 1:29 AM, Xin Tong trent.t...@gmail.com wrote:
+/* swap the 2 given TLB entries as well as their corresponding IOTLB */
+inline void swap_tlb(CPUTLBEntry *te, CPUTLBEntry *se, hwaddr *iote,
+ hwaddr *iose)
+{
+ hwaddr iotmp;
+ CPUTLBEntry t;
+
Hi Varad,
On Mon, Nov 18, 2013 at 5:49 PM, Varad Gautam varadgau...@gmail.com wrote:
Hi! I'm new here, and am working on my first bug. I have posted a patch
for Bug#603872 [1]. It's incomplete right now, but please have a look and
tell me if I'm headed in the right direction. (I don't know if
android
emulator only for ARM.
You can add
#include elf.h
into cputlb.c and then decide based on ELF_MACHINE symbol, like
#if ELF_MACHINE == EM_ARM
On Wed, Nov 13, 2013 at 1:59 AM, Max Filippov jcmvb...@gmail.com wrote:
On Wed, Nov 13, 2013 at 11:26 AM, Fardin fardina...@yahoo.com wrote:
Hi
On Wed, Nov 13, 2013 at 11:26 AM, Fardin fardina...@yahoo.com wrote:
Hi everyone,
My question might look very stupid but the answer would really help me.
I am working on Android emulator which is using QEMU. I need to print out
the value of env-cp15.c13_fcse everytime the void
On Mon, Nov 11, 2013 at 8:50 PM, Eric Blake ebl...@redhat.com wrote:
Quick - identify the bug in this code (from ui/curses.c):
static void curses_winch_handler(int signum)
{
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
unsigned short ws_xpixel;
.
Max Filippov (2):
exec: fix breakpoint_invalidate when pc may not be translated
target-xtensa: add missing DEBUG section to dc233c config
exec.c | 6 --
target-xtensa/core-dc233c.c | 1 +
2 files
On Mon, Oct 28, 2013 at 4:43 AM, Max Filippov jcmvb...@gmail.com wrote:
This fixes qemu abort with the following message:
include/qemu/int128.h:22: int128_get64: Assertion `!a.hi' failed.
which happens due to attempt to invalidate breakpoint by virtual address
for which
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks for a zero offset and
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
At the end of the TLB miss handler a tlb_flush of QEMUs TLB
is executed which is exactly what we want to avoid.
As long as there is no
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
Hi,
This is the second part of the patches to make the openrisc target faster
and more reliable.
Hi Sebastian,
this series doesn't apply cleanly to the current qemu git head,
what tree is it based on?
--
Thanks.
--
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
srf is a boolean variable.
Therefore the instruction should check for != 0 and not for != SR_F
Signed-off-by: Sebastian Macke sebast...@macke.de
---
target-openrisc/translate.c | 2 +-
1 file changed, 1
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
Instead of testing the overflow exception dynamically every time
The flag will be reckognized by the tcg as changed code and
will recompile the code with the correct checks.
Signed-off-by: Sebastian Macke
On Wed, Oct 30, 2013 at 1:53 AM, Sebastian Macke sebast...@macke.de wrote:
On 29/10/2013 2:01 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de
wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
At the end
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke sebast...@macke.de wrote:
On 29/10/2013 1:05 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de
wrote:
Additional this patch solves a severe bug for the softmmu emulation.
The pc has to be saved
/archive/html/qemu-devel/2013-09/msg04582.html
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
exec.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 2e31ffc..9150430 100644
--- a/exec.c
+++ b/exec.c
@@ -409,8 +409,10
On Tue, Oct 22, 2013 at 8:15 PM, Sebastian Macke sebast...@macke.de wrote:
On 22/10/2013 9:01 AM, Max Filippov wrote:
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke sebast...@macke.de
wrote:
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have to
compile
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke sebast...@macke.de wrote:
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have to
compile the image for QEMU anyhow.
http://opencores.org/or1k/OpenRISC_GNU_tool_chain
Then it's just an make make test in the
This fixes missing debug feature opcodes of dc233c core variant.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/core-dc233c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-xtensa/core-dc233c.c b/target-xtensa/core-dc233c.c
index 11acbf3
On Fri, Sep 27, 2013 at 11:36 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 27/09/2013 20:29, Max Filippov ha scritto:
Hi,
I'm getting said assertion failure debugging linux userspace
application through the qemu gdbstub. The backtrace looks like this:
qemu-system-xtensa: include/qemu
)
xtensa queue 2013-10-15
Max Filippov (1):
target-xtensa: add in_asm logging
target-xtensa/translate.c | 8
1 file changed, 8 insertions(+)
--
1.8.1.4
of
cpu_get_phys_page debug in the breakpoint_invalidate:
--- 8 ---
commit cb3f9f90688be062b8a1f12b116f3d48c7ded232
Author: Max Filippov jcmvb...@gmail.com
Date: Fri Sep 27 22:19:16 2013 +0400
exec: fix breakpoint_invalidate when pc may not be translated
This fixes qemu abort with the following
got any
measurable performance change. From op,out_asm output most
TBs got longer by 1-4 instructions and all temp indices got
doubled.
---8---
From 73300be7dd6b3d31cbfa45225714d5e43c52f077 Mon Sep 17 00:00:00 2001
From: Max Filippov jcmvb...@gmail.com
Date: Sun, 22 Sep 2013 18:54:53 +0400
Subject
On Thu, Sep 12, 2013 at 11:49 AM, Xie Xianshan xi...@cn.fujitsu.com wrote:
Hi Max,
Thanks for your patience and help.
I`ve tried to do what you said, but the problem doesn`t go away.
And actually i cannot add a new register to the fpga device, because the
fpga device i`m emulating
On Thu, Sep 12, 2013 at 2:51 PM, Xie Xianshan xi...@cn.fujitsu.com wrote:
Dear Max,
Does it mean an IRQ to be edge-triggered?
No, it is a level-sensitive and active-high interrupt.
This is why i tried to use qemu_irq_raise() to trigger IRQ.
Ok, back to your original question:
I`m
On Wed, Sep 11, 2013 at 12:12 PM, Xie Xianshan xi...@cn.fujitsu.com wrote:
I want to add a new device fpga for e500, and trigger an interrupt IRQ3
while the register BB_INTR_REG which belongs to device fpga is wrote by
the device driver of fpga.
For e500, IRQ3 is an external interrupt irq.
On Tue, Sep 10, 2013 at 11:25 AM, Xie Xianshan xi...@cn.fujitsu.com wrote:
hi everyone,
I`m getting the nobody cared disabling IRQ error, when i raised external
interrupts IRQ3 to the Openpic in QEMU.
(Actually, any external interrupts irq i raised can reproduce this error,
but internal
-by: Max Filippov jcmvb...@gmail.com
--
Thanks.
-- Max
)
and write to that register from your driver's ISR.
Or you can choose an edge-triggered IRQ to play with.
2013/8/27 Max Filippov jcmvb...@gmail.com
On Tue, Aug 27, 2013 at 3:55 PM, she roy she.min@gmail.com wrote:
How to lower it? Thank you very much!
qemu_set_irq(gPl061-irq, 0
is always signalled by level.
You need to update GPIOIC register from your driver's ISR to clear it.
2013/8/28 Max Filippov jcmvb...@gmail.com
On Wed, Aug 28, 2013 at 12:01 PM, she roy she.min@gmail.com wrote:
I tested qemu_irq_pulse(gPl061-irq); the guest did not generate an
interrupt
On Wed, Aug 28, 2013 at 12:27 PM, Max Filippov jcmvb...@gmail.com wrote:
On Wed, Aug 28, 2013 at 12:19 PM, she roy she.min@gmail.com wrote:
PL061 has a register GPIOIS to control if the interrupt is lever-triggered
or edge-triggered, I will try this. Thanks.
This register defines which
On Tue, Aug 27, 2013 at 3:36 PM, she roy she.min@gmail.com wrote:
Is there somebody can help me to trigger a gpio interrupt inside qemu? I
wrote a simple function to trigger a interrupt in pl061.c as follow:
PL061State *gPl061;
void pl061_raise_irq()
{
qemu_set_irq(gPl061-irq, 1);
}
On Mon, Aug 26, 2013 at 2:58 AM, Ákos Kovács akoskov...@gmx.com wrote:
The new CONFIG_* definitions added to the default-configs/arm-softmmu.mak
Signed-off-by: Ákos Kovács akoskov...@gmx.com
---
default-configs/arm-softmmu.mak | 13 +
hw/arm/Makefile.objs| 35
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