Re: [PATCH v10 1/9] mm: Introduce memfd_restricted system call to create restricted user memory

> +static struct file *restrictedmem_file_create(struct file *memfd) > +{ > + struct restrictedmem_data *data; > + struct address_space *mapping; > + struct inode *inode; > + struct file *file; > + > + data = kzalloc(sizeof(*data), GFP_KERNEL); > + if (!data) > +

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 15/08/22 18:34, Chao Peng wrote: > On Fri, Aug 12, 2022 at 02:18:43PM +0530, Nikunj A. Dadhania wrote: >> >> >> On 12/08/22 12:48, Gupta, Pankaj wrote: >>> >>>>>>>> >>>>>>>> However, fallocate() preallocates full

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 12/08/22 12:48, Gupta, Pankaj wrote: > >> >> However, fallocate() preallocates full guest memory before starting the >> guest. >> With this behaviour guest memory is *not* demand pinned. Is there a way >> to >> prevent fallocate() from reserving full guest memory?

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 11/08/22 19:02, Chao Peng wrote: > On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote: >>> >>> While debugging an issue with SEV+UPM, found that fallocate() returns >>> an error in QEMU which is not handled (EINTR). With the below handling >>> of EINTR subsequent fallocate()

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 11/08/22 19:02, Chao Peng wrote: > On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote: >> Test To test the new functionalities of this patch TDX patchset is needed. Since TDX patchset has not been merged so I did two kinds of test: - Regresion

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 11/08/22 17:00, Gupta, Pankaj wrote: > >>> This is the v7 of this series which tries to implement the fd-based KVM >>> guest private memory. The patches are based on latest kvm/queue branch >>> commit: >>> >>>    b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU >>> split_desc_cache

Re: [PATCH v7 00/14] KVM: mm: fd-based approach for supporting KVM guest private memory

On 06/07/22 13:50, Chao Peng wrote: > This is the v7 of this series which tries to implement the fd-based KVM > guest private memory. The patches are based on latest kvm/queue branch > commit: > > b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU > split_desc_cache only by default

Re: [PATCH] x86: cpu: Error out if memory exceeds addressable range

On 7/18/2022 7:15 PM, Joao Martins wrote: > On 7/18/22 14:10, Nikunj A. Dadhania wrote: >> On 7/18/2022 6:12 PM, Igor Mammedov wrote: >>> On Mon, 18 Jul 2022 13:47:34 +0530 >>> Nikunj A Dadhania wrote: >>> >>>> Currently it is poss

Re: [PATCH] x86: cpu: Error out if memory exceeds addressable range

On 7/18/2022 6:12 PM, Igor Mammedov wrote: > On Mon, 18 Jul 2022 13:47:34 +0530 > Nikunj A Dadhania wrote: > >> Currently it is possible to start a guest with memory that is beyond >> the addressable range of CPU and QEMU does not even warn about it. >> The defa

[PATCH] x86: cpu: Error out if memory exceeds addressable range

. Reported-by: Shaju Abraham Signed-off-by: Nikunj A Dadhania --- target/i386/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a57ef13af..1afbdbac7d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6376,6 +6376,7

Re: [PATCH v6 6/8] KVM: Handle page fault for private memory

On 5/19/2022 9:07 PM, Chao Peng wrote: > A page fault can carry the information of whether the access if private > or not for KVM_MEM_PRIVATE memslot, this can be filled by architecture > code(like TDX code). To handle page faut for such access, KVM maps the > page only when this private property

Re: [Qemu-devel] [PATCH v2] target/ppc/kvm: set vcpu as online/offline

David Gibson writes: > On Tue, Sep 04, 2018 at 11:00:39AM +0530, Nikunj A Dadhania wrote: >> Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is >> online(1) or offline(0) >> >> KVM will use this information to set the RWMR register,

[Qemu-devel] [PATCH v2] target/ppc/kvm: set vcpu as online/offline

Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is online(1) or offline(0) KVM will use this information to set the RWMR register, which controls the PURR and SPURR accumulation. CC: pau...@samba.org Signed-off-by: Nikunj A Dadhania --- hw/ppc/spapr_cpu_core.c | 1

[Qemu-devel] [PATCH v3] target/ppc/kvm: set vcpu as online/offline

Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is online(1) or offline(0) KVM will use this information to set the RWMR register, which controls the PURR and SPURR accumulation. CC: pau...@samba.org Signed-off-by: Nikunj A Dadhania --- hw/ppc/spapr_cpu_core.c | 1

Re: [Qemu-devel] [PATCH] target/ppc/kvm: set vcpu as online/offline

David Gibson <da...@gibson.dropbear.id.au> writes: > On Mon, Apr 23, 2018 at 11:43:02AM +0530, Nikunj A Dadhania wrote: >> Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is >> online(1) or offline(0) >> >> KVM will use this informatio

[Qemu-devel] [PATCH] target/ppc/kvm: set vcpu as online/offline

Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is online(1) or offline(0) KVM will use this information to set the RWMR register, which controls the PURR and SPURR accumulation. CC: pau...@samba.org Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> ---

Re: [Qemu-devel] Using new TCG Vector infrastructure in PowerPC

Richard Henderson <richard.hender...@linaro.org> writes: > On 03/16/2018 12:08 PM, Nikunj A Dadhania wrote: >> @@ -1078,8 +1079,8 @@ struct CPUPPCState { >> /* Altivec registers */ >> ppc_avr_t avr[32]; >> uint32_t vscr; >> -/* V

Re: [Qemu-devel] Using new TCG Vector infrastructure in PowerPC

Richard Henderson <richard.hender...@linaro.org> writes: > On 03/07/2018 06:03 PM, Nikunj A Dadhania wrote: >> Hi Richard, >> >> I was working to get TCG vector support for PowerPC[1]. Started with >> converting logical operations like vector AND/OR/XOR and co

[Qemu-devel] Using new TCG Vector infrastructure in PowerPC

Hi Richard, I was working to get TCG vector support for PowerPC[1]. Started with converting logical operations like vector AND/OR/XOR and compare instructions. Found some inconsistency during my testing on x86 laptop emulating PowerPC: zero = max =

[Qemu-devel] [PATCH] hw/ppc/spapr, e500: Use new property "stdout-path" for boot console

compatible with existing/older firmware. This older property can be deprecated after 5 years. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- hw/ppc/e500.c | 7 +++ hw/ppc/spapr.c | 7 +++ 2 files changed, 14 insertions(+) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c

Re: [Qemu-devel] [PATCH v2 3/4] spapr/rtas: fix reboot of a SMP TCG guest

interrupt in the LPCR for > the secondaries. > > Based on previous work from Nikunj A Dadhania <nik...@linux.vnet.ibm.com> > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> > --- > hw/ppc/spapr_cpu_core.c |

Re: [Qemu-devel] [PATCH 0/2] disable the decrementer interrupt when a CPU is unplugged

Benjamin Herrenschmidt <b...@kernel.crashing.org> writes: > On Fri, 2017-10-06 at 11:40 +0530, Nikunj A Dadhania wrote: >> Cédric Le Goater <c...@kaod.org> writes: >> >> > Hello, >> > >> > When a CPU is stopped with the 'stop-sel

Re: [Qemu-devel] [PATCH 0/2] disable the decrementer interrupt when a CPU is unplugged

Cédric Le Goater writes: > Hello, > > When a CPU is stopped with the 'stop-self' RTAS call, its state > 'halted' is switched to 1 and, in this case, the MSR is not taken into > account anymore in the cpu_has_work() routine. Only the pending > hardware interrupts are checked with

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

Cédric Le Goater <c...@kaod.org> writes: > On 09/22/2017 08:00 AM, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >>>>>> >>>>>> As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

ps for multiple sockets When the user does not provide the cpu topology, e.g. "-smp 4", machine fails to initialize 4 cpus. QEMU assumes smp_threads and smp_cores both as 1. Make sure that we initialize multiple chips for this. Remove the user-settable property num_chips

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Sep 20, 2017 at 12:48:55PM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Wed, Sep 20, 2017 at 12:10:48PM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Sep 20, 2017 at 12:10:48PM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Wed, Sep 20, 2017 at 10:43:19AM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: >> >> >>> >> I think the current approach is the simplest and less intrusive, as we >>> >> are handling a case where user has not bothered to provide a detailed >>> >> top

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Sep 20, 2017 at 10:43:19AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Wed, Sep 20, 2017 at 09:50:24AM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Sep 20, 2017 at 09:50:24AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Fri, Sep 15, 2017 at 02:39:16PM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Fri, Sep 15, 2017 at 02:39:16PM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Fri, Sep 15, 2017 at 01:53:15PM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Fri, Sep 15, 2017 at 01:53:15PM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> >> >> >> I thought, I am doing the same here for PowerNV, numb

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson writes: >> >> I thought, I am doing the same here for PowerNV, number of online cores >> is equal to initial online vcpus / threads per core >> >>int boot_cores_nr = smp_cpus / smp_threads; >> >> Only difference that I see in PowerNV is that we

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Jul 19, 2017 at 09:20:52AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote: >> &g

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Mon, Sep 11, 2017 at 10:40:10AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Wed, Sep 06, 2017 at 01:57:48PM +0530, Nikunj A Dadhania wrote: >>

Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

David Gibson <da...@gibson.dropbear.id.au> writes: > On Wed, Sep 06, 2017 at 01:57:48PM +0530, Nikunj A Dadhania wrote: >> When the user does not provide the cpu topology, e.g. "-smp 4", machine >> fails to >> initialize 4 cpus. Compute the chip per cores

[Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus

When the user does not provide the cpu topology, e.g. "-smp 4", machine fails to initialize 4 cpus. Compute the chip per cores depending on the number of chips and smt threads. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- hw/ppc/pnv.c | 20 ++--

Re: [Qemu-devel] [PATCH v3 1/5] ppc: spapr: Register and handle HCALL to receive updated RTAS region

David Gibson writes: > On Wed, Aug 16, 2017 at 02:42:13PM +0530, Aravinda Prasad wrote: >> Receive updates from SLOF about the updated rtas-base. >> A separate patch for SLOF [1] adds functionality to invoke >> a private HCALL whenever OS issues instantiate-rtas with

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson <da...@gibson.dropbear.id.au> writes: > On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote: >&

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson <da...@gibson.dropbear.id.au> writes: > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote: >> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG. >> >> When reset happens, all the CPUs are in halted state. First CPU is

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson <da...@gibson.dropbear.id.au> writes: > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote: >> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG. >> >> When reset happens, all the CPUs are in halted state. First CPU is

Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

David Gibson <da...@gibson.dropbear.id.au> writes: > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote: >> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG. >> >> When reset happens, all the CPUs are in halted state. First CPU is

[Qemu-devel] [PATCH v3] spapr: disable decrementer during reset

by rtas start-cpu call. Reported-by: Bharata B Rao <bhar...@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- hw/ppc/spapr_cpu_core.c | 9 + hw/ppc/spapr_rtas.c | 8 2 files changed, 17 insertions(+) diff --git a/hw/ppc/spapr_cpu

[Qemu-devel] [PATCH v2] spapr: ignore decr interrupts when MSR_EE is disabled

= 4bd8 ERROR: Flatten device tree not available! exception 300 SRR0 = 60e4 SRR1 = 80008000 SPRG2 = 0040 SPRG3 = 4bd8 Reported-by: Bharata B Rao <bhar...@linux.vnet.ibm.com> Tested-by: Cédric Le Goater <c...@kaod.org> Signed-of

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC] spapr: ignore interrupts during reset state

Cédric Le Goater <c...@kaod.org> writes: > On 07/13/2017 11:10 AM, Nikunj A Dadhania wrote: >> Cédric Le Goater <c...@kaod.org> writes: >> >>> On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote: >>>> Cédric Le Goater <c...@kaod.org> writes:

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC] spapr: ignore interrupts during reset state

Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > Cédric Le Goater <c...@kaod.org> writes: > >> On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote: >>> Cédric Le Goater <c...@kaod.org> writes: >>> >>>>>> How a

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC] spapr: ignore interrupts during reset state

Cédric Le Goater <c...@kaod.org> writes: > On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote: >> Cédric Le Goater <c...@kaod.org> writes: >> >>>>> How about the following, we do not report work until MSR_EE is disabled: >>>> >>>>

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC] spapr: ignore interrupts during reset state

Cédric Le Goater writes: >>> How about the following, we do not report work until MSR_EE is disabled: >> >> With this fix, I could test the XIVE<->XICS transitions at reboot >> under TCG. However, the second boot is very slow for some reason. > > hmm, I am not sure this is

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC] spapr: ignore interrupts during reset state

Cédric Le Goater <c...@kaod.org> writes: > On 07/13/2017 06:38 AM, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >>> >>> Ok, but we definitely should be able to fix this without new >>> variables. I

Re: [Qemu-devel] [PATCH RFC] spapr: ignore interrupts during reset state

David Gibson <da...@gibson.dropbear.id.au> writes: > On Fri, Jun 09, 2017 at 10:32:25AM +0530, Nikunj A Dadhania wrote: >> David Gibson <da...@gibson.dropbear.id.au> writes: >> >> > On Thu, Jun 08, 2017 at 12:06:08PM +0530, Nikunj A Dadhania wrote: >&

Re: [Qemu-devel] [PATCH v4 0/6] spapr/xics: fix migration of older machine types

Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > Greg Kurz <gr...@kaod.org> writes: > >> On Sun, 11 Jun 2017 17:38:42 +0800 >> David Gibson <da...@gibson.dropbear.id.au> wrote: >> >>> On Fri, Jun 09, 2017 at 05:09:13PM +0200, Greg

Re: [Qemu-devel] [Qemu-ppc] [PATCH] target/ppc/excp_helper: Take BQL before calling cpu_interrupt()

Alex Bennée writes: > Thomas Huth writes: > >> Since the introduction of MTTCG, using the msgsnd instruction >> abort()s if being called without holding the BQL. So let's protect >> that part of the code now with qemu_mutex_lock_iothread(). >> >>

Re: [Qemu-devel] [PATCH v4 0/6] spapr/xics: fix migration of older machine types

David Gibson <da...@gibson.dropbear.id.au> writes: > On Tue, Jun 13, 2017 at 01:59:29PM +0530, Nikunj A Dadhania wrote: >> Greg Kurz <gr...@kaod.org> writes: >> >> > On Sun, 11 Jun 2017 17:38:42 +0800 >> > David Gibson <da...@gibson.dropbear.id.au&

Re: [Qemu-devel] [PATCH v4 0/6] spapr/xics: fix migration of older machine types

lper=/usr/libexec/qemu-bridge-helper \ >> > -device virtio-blk,drive=drive0,id=blk0 \ >> > -drive file=/home/greg/images/sle12-sp1-ppc64le.qcow2,id=drive0,if=none \ >> > -machine type=pseries,accel=tcg -cpu POWER8 Strangely, your command line does not have multiple

Re: [Qemu-devel] [PATCH RFC] spapr: ignore interrupts during reset state

David Gibson <da...@gibson.dropbear.id.au> writes: > On Thu, Jun 08, 2017 at 12:06:08PM +0530, Nikunj A Dadhania wrote: >> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG. > > Ouch. When exactly did this happen? Broken since long > I know that smp

[Qemu-devel] [PATCH RFC] spapr: ignore interrupts during reset state

= 4bd8 ERROR: Flatten device tree not available! exception 300 SRR0 = 60e4 SRR1 = 80008000 SPRG2 = 0040 SPRG3 = 4bd8 Reported-by: Bharata B Rao <bhar...@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nik...@linux.vne

Re: [Qemu-devel] [PATCH risu] ppc64.risu: Fix broken constraints

Peter Maydell writes: > Commit c10b97092 changed some field names in rldicr and rldimi patterns > but forgot to update the constraints to match the change. Since the > field (previously 'rb' and now 'sh') is an immediate rather than a > register number, the correct fix

Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions

Peter Maydell <peter.mayd...@linaro.org> writes: > On 30 May 2017 at 16:39, Peter Maydell <peter.mayd...@linaro.org> wrote: >> On 30 May 2017 at 16:26, Nikunj A Dadhania <nik...@linux.vnet.ibm.com> wrote: >>> Sandipan Das <sandipandas1...@gmail.com> write

Re: [Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions

s <sandipandas1...@gmail.com> Reviewed-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> > --- > ppc64.risu | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/ppc64.risu b/ppc64.risu > index 28df9da..dd304e2 100644 > --- a/ppc64.risu &g

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

G 3 writes: > On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote: > > Hello I have also done some work risu. My patches add ppc32 support. > Well my patches were made to work with Mac OS X but they are required > to work with Linux. Do you think you

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

Sandipan Das writes: > The patterns for the following instructions are fixed: > * Rotate Left Doubleword then Clear Right (rldcr[.]) > * Rotate Left Doubleword Immediate then Clear Right (rldicr[.]) > * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.]) >

[Qemu-devel] [PATCH] target/ppc: reset reservation in do_rfi()

For transitioning back to userspace after the interrupt. Suggested-by: Richard Henderson <r...@twiddle.net> Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- target/ppc/excp_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/ppc/excp_helper.c

Re: [Qemu-devel] [PATCH 7/8] target/ppc: optimize various functions using extract op

Philippe Mathieu-Daudé writes: > Applied using Coccinelle script. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/ppc/translate.c | 9 +++-- > target/ppc/translate/vsx-impl.inc.c | 21 +++-- > 2 files changed, 10

[Qemu-devel] [PATCH v3 6/6] target/ppc: do not reset reserve_addr in exec_enter

; But by the time it return back, the reservation is erased and the code fails, this continues forever and the lock is never taken. Instead set this in powerpc_excp() Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do, let us get rid of the function. Signed-off-by: Nikunj A Da

[Qemu-devel] [PATCH v3 3/6] target/ppc: Generate fence operations

Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <r...@twiddle.net> --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 50b6d4d..4a1f24a 100644 ---

[Qemu-devel] [PATCH v3 4/6] cpus: Fix CPU unplug for MTTCG

From: Bharata B Rao <bhar...@linux.vnet.ibm.com> Ensure that the unplugged CPU thread is destroyed and the waiting thread is notified about it. This is needed for CPU unplug to work correctly in MTTCG mode. Signed-off-by: Bharata B Rao <bhar...@linux.vnet.ibm.com> Signed-of

[Qemu-devel] [PATCH v3 1/6] target/ppc: Emulate LL/SC using cmpxchg helpers

Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> Reviewed-by: R

[Qemu-devel] [PATCH v3 2/6] cputlb: handle first atomic write to the page

In case where the conditional write is the first write to the page, TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as a special case and set the dirty bit. After that fall through to the actual atomic instruction below. Signed-off-by: Nikunj A Dadhania <

[Qemu-devel] [PATCH v3 5/6] tcg: enable MTTCG by default for PPC64 on x86

This enables the multi-threaded system emulation by default for PPC64 guests using the x86_64 TCG back-end. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> Reviewed-by: Alex Bennée <alex.ben...@linaro.org> --- configure| 2 ++ target/ppc/cpu.h | 2 ++ 2 file

[Qemu-devel] [PATCH v3 0/6] The series enables Multi-Threaded TCG on PPC64

turn value after exit_atomic * Fixed a bug in ppc_cpu_exec_enter(), which was resetting the reserve_addr, this should be done in powerpc_excp() v1: * Rewrote store_conditional as suggested by Richard Bharata B Rao (1): cpus: Fix CPU unplug for MTTCG Nikunj A Dadhania (5): target/ppc: Emu

[Qemu-devel] [PATCH] target/ppc: do not reset reserve_addr in exec_enter

; But by the time it return back, the reservation is erased and the code fails, this continues forever and the lock is never taken. Instead set this in powerpc_excp() Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do, let us get rid of the function. Signed-off-by: Nikunj A Da

Re: [Qemu-devel] [PATCH] tcg: Initialize return value after exit_atomic

Richard Henderson <r...@twiddle.net> writes: > Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize > the output. Even though this code is dead, it gets translated, and > without the initialization we encounter a tcg_error. > > Reported-by: N

Re: [Qemu-devel] [PATCH] tcg: Initialize return value after exit_atomic

Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > aNikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > >> Richard Henderson <r...@twiddle.net> writes: >> >>> On 04/25/2017 01:21 PM, Nikunj A Dadhania wrote: >>>> Richa

Re: [Qemu-devel] [PATCH] tcg: Initialize return value after exit_atomic

aNikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > Richard Henderson <r...@twiddle.net> writes: > >> On 04/25/2017 01:21 PM, Nikunj A Dadhania wrote: >>> Richard Henderson <r...@twiddle.net> writes: >>> >>>> Users o

Re: [Qemu-devel] [PATCH] tcg: Initialize return value after exit_atomic

Richard Henderson <r...@twiddle.net> writes: > Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize > the output. Even though this code is dead, it gets translated, and > without the initialization we encounter a tcg_error. > > Reported-by: N

Re: [Qemu-devel] [PATCH RFC] configure: fix clang failure for libatomic

Peter Maydell <peter.mayd...@linaro.org> writes: > On 25 April 2017 at 09:58, Nikunj A Dadhania <nik...@linux.vnet.ibm.com> > wrote: >> I was trying out the program in the configure script with clang and I do >> get errors without libatomic: >> >> $

Re: [Qemu-devel] [PATCH RFC] configure: fix clang failure for libatomic

Peter Maydell <peter.mayd...@linaro.org> writes: > On 25 April 2017 at 09:35, Nikunj A Dadhania <nik...@linux.vnet.ibm.com> > wrote: >> Travis builds failure was reported for powernv boot-serial test with >> qemu built with clang. >> >> Debugging revea

[Qemu-devel] [PATCH RFC] configure: fix clang failure for libatomic

. libatomic is required to successfully test atomic64 and atomic128 for clang. Introduced newer checks for the same. And on failure default to single threaded tcg support in PPC64. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- Reference: https://lists.gnu.org/archive/html/qemu-pp

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC v1 0/3] Enable MTTCG on PPC64

Cédric Le Goater <c...@kaod.org> writes: > On 04/10/2017 06:44 PM, Nikunj A Dadhania wrote: >> Cédric Le Goater <c...@kaod.org> writes: >> >>> On 04/07/2017 08:07 AM, Cédric Le Goater wrote: >>>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrot

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC v1 0/3] Enable MTTCG on PPC64

Cédric Le Goater <c...@kaod.org> writes: > On 04/07/2017 08:07 AM, Cédric Le Goater wrote: >> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote: >>> Cédric Le Goater <c...@kaod.org> writes: >>> >>>> Hello Nikunj, >>>> >>>>

[Qemu-devel] [PATCH for 2.10] tcg: enable MTTCG by default for PPC64 on x86

This enables the multi-threaded system emulation by default for PPC64 guests using the x86_64 TCG back-end. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- Depends on following patch which fixes the define name: https://patchwork.ozlabs.org/patch/748840/ --- con

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/3] Enable MTTCG on PPC64

Alex Bennée <alex.ben...@linaro.org> writes: > Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > >> Alex Bennée <alex.ben...@linaro.org> writes: >> >>> luigi burdo <intermedi...@hotmail.com> writes: >>> >>>

[Qemu-devel] [PATCH fix for-2.9] cpus: fix wrong define name

While the configure script generates TARGET_SUPPORTS_MTTCG define, one of the define is cpus.c is checking wrong name: TARGET_SUPPORT_MTTCG Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- cpus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpus.c b/

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/3] Enable MTTCG on PPC64

Alex Bennée writes: > luigi burdo writes: > >> Hi David and Nikuji, >> >> can i suggest to remove the message: >> >> >> Guest not yet converted to MTTCG - you may get unexpected results >> where the mttcg is enabled? > > Have you declared the

[Qemu-devel] [PATCH v2 3/3] target/ppc: Generate fence operations

Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 50b6d4d..4a1f24a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -

[Qemu-devel] [PATCH v2 0/3] Enable MTTCG on PPC64

. * More testing for corner cases. Nikunj A Dadhania (3): target/ppc: Emulate LL/SC using cmpxchg helpers cputlb: handle first atomic write to the page target/ppc: Generate fence operations cputlb.c | 8 +++- target/ppc/translate.c | 37

[Qemu-devel] [PATCH v2 1/3] target/ppc: Emulate LL/SC using cmpxchg helpers

Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- targ

[Qemu-devel] [PATCH v2 2/3] cputlb: handle first atomic write to the page

In case where the conditional write is the first write to the page, TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as a special case and set the dirty bit. After that fall through to the actual atomic instruction below. Signed-off-by: Nikunj A Dadhania <

Re: [Qemu-devel] [PATCH RFC v1 1/3] target/ppc: Emulate LL/SC using cmpxchg helpers

David Gibson <da...@gibson.dropbear.id.au> writes: > [ Unknown signature status ] > On Thu, Apr 06, 2017 at 03:52:47PM +0530, Nikunj A Dadhania wrote: >> Emulating LL/SC with cmpxchg is not correct, since it can suffer from >> the ABA problem. However, portable parallel

Re: [Qemu-devel] [Qemu-ppc] [PATCH RFC v1 0/3] Enable MTTCG on PPC64

Cédric Le Goater <c...@kaod.org> writes: > Hello Nikunj, > > On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote: >> The series enables Multi-Threaded TCG on PPC64 >> >> Patch 01: Use atomic_cmpxchg in store conditional >> 02: Handle first write to p

Re: [Qemu-devel] [PATCH RFC v1 3/3] target/ppc: Generate fence operations

Richard Henderson <r...@twiddle.net> writes: > On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote: >> @@ -3028,6 +3030,7 @@ static void gen_##name(DisasContext *ctx) >> \ >> tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop);

Re: [Qemu-devel] [PATCH RFC v1 1/3] target/ppc: Emulate LL/SC using cmpxchg helpers

Richard Henderson <r...@twiddle.net> writes: > On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote: >> tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); >> l1 = gen_new_label(); >> tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); >> -tcg_gen_ori_i

Re: [Qemu-devel] [PATCH RFC v1 1/3] target/ppc: Emulate LL/SC using cmpxchg helpers

Richard Henderson <r...@twiddle.net> writes: > On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote: >> +TCGv_i32 tmp = tcg_temp_local_new_i32(); >> +TCGv t0; >> >> +tcg_gen_movi_i32(tmp, 0); >> tcg_gen_trunc_tl_i32(cpu_crf[

[Qemu-devel] [PATCH RFC v1 1/3] target/ppc: Emulate LL/SC using cmpxchg helpers

Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- targ

[Qemu-devel] [PATCH RFC v1 2/3] cputlb: handle first atomic write to the page

In case where the conditional write is the first write to the page, TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as a special case and set the dirty bit. After that fall through to the actual atomic instruction below. Signed-off-by: Nikunj A Dadhania <

[Qemu-devel] [PATCH RFC v1 0/3] Enable MTTCG on PPC64

: ./ppc64-softmmu/qemu-system-ppc64 -cpu POWER8 -vga none -nographic -machine pseries,usb=off -m 2G -smp 8,cores=8,threads=1 -accel tcg,thread=multi f23.img Todo: * Enable other machine types and PPC32. * More testing for corner cases. Nikunj A Dadhania (3): target/ppc: Emulate LL/SC using

[Qemu-devel] [PATCH RFC v1 3/3] target/ppc: Generate fence operations

Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com> --- target/ppc/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a9c733d..87b4fe4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

Alex Bennée <alex.ben...@linaro.org> writes: > Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > >> Richard Henderson <r...@twiddle.net> writes: >> >>> On 09/12/2016 06:47 AM, Alex Bennée wrote: >>>>> > +/* Notice an IO acc

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

Alex Bennée <alex.ben...@linaro.org> writes: > Nikunj A Dadhania <nik...@linux.vnet.ibm.com> writes: > >> Richard Henderson <r...@twiddle.net> writes: >> >>> On 09/12/2016 06:47 AM, Alex Bennée wrote: >>>>> > +/* Notice an IO acc

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

Richard Henderson writes: > On 09/12/2016 06:47 AM, Alex Bennée wrote: >>> > +/* Notice an IO access, or a notdirty page. */ >>> > +if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { >>> > +/* There's really nothing that can be done to >>> > + support this

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