by x86_cpu_list_entry(), e.g. '-cpu
help'.
QMP 'query-cpu-definitions' will also return a bool value indicating the
deprecation status.
Signed-off-by: Robert Hoo
---
Changelog
v3:
Make the deprecation implementation CPUClass generic.
v2:
Move deprecation check from parse_cpu_option() to machine_run_board_init
On Mon, 2020-09-14 at 13:38 +, Eduardo Habkost wrote:
> On Mon, Sep 14, 2020 at 06:50:09PM +0800, Robert Hoo wrote:
> > On Fri, 2020-09-11 at 10:00 -0400, Eduardo Habkost wrote:
> > > On Fri, Sep 11, 2020 at 02:22:51PM +0800, Robert Hoo wrote:
> > > > On Wed, 2020
On Fri, 2020-09-11 at 10:00 -0400, Eduardo Habkost wrote:
> On Fri, Sep 11, 2020 at 02:22:51PM +0800, Robert Hoo wrote:
> > On Wed, 2020-09-09 at 14:15 -0400, Eduardo Habkost wrote:
> > > Hi,
> > >
> > >
> > > > @@ -1129,6 +1130,12 @@ void mach
On Wed, 2020-09-09 at 14:15 -0400, Eduardo Habkost wrote:
> Hi,
>
> Thanks for the patch, and sorry for taking so long to review
> this. I'm finally getting to the patches that were postponed to
> 5.2.
>
> Comments and questions below:
>
> On Thu, Jun 11, 2020 at 1
Hi, Ping for comments:)
On Thu, 2020-06-11 at 10:47 +0800, Robert Hoo wrote:
> Complement versioned CPU model framework with the ability of marking
> some
> versions deprecated. When that CPU model is chosen, get some warning.
> The
> warning message is customized, e.g. telling
Going to obsolete Icelake-Client CPU models in the future.
(No changes in v2)
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0d8638a..47a11b5 100644
--- a/target/i386
documentation. Thanks Eric for comment and guidance on qapi.
Signed-off-by: Robert Hoo
---
hw/core/machine.c| 11 +--
include/hw/core/cpu.h| 1 +
qapi/machine-target.json | 7 ++-
target/i386/cpu.c| 45 +++--
4 files changed, 59
On Fri, 2020-06-05 at 08:47 -0500, Eric Blake wrote:
> On 6/4/20 9:47 PM, Robert Hoo wrote:
> > On Thu, 2020-06-04 at 06:59 -0500, Eric Blake wrote:
> > > On 6/4/20 3:07 AM, Robert Hoo wrote:
> > >
> > > > > > +++ b/qapi/mac
On Thu, 2020-06-04 at 06:59 -0500, Eric Blake wrote:
> On 6/4/20 3:07 AM, Robert Hoo wrote:
>
> > > > +++ b/qapi/machine-target.json
> > > > @@ -309,7 +309,8 @@
> > > >'static': 'bool',
> > > >'*unavailable-
On Wed, 2020-06-03 at 09:11 -0500, Eric Blake wrote:
> On 6/3/20 6:47 AM, Robert Hoo wrote:
> > Complement versioned CPU model framework with the ability of
> > marking some
> > versions deprecated. When that CPU model is chosen, get some
> > warning. The
> > w
by x86_cpu_list_entry(), e.g. '-cpu
help'.
QMP 'query-cpu-definitions' will also return a bool value indicating the
deprecation status.
Signed-off-by: Robert Hoo
---
exec.c | 3 +++
include/hw/core/cpu.h| 1 +
qapi/machine-target.json | 3 ++-
target/i386/cpu.c| 45
Going to obsolete Icelake-Client CPU models in the future.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d7ac22f..6c34ea3 100644
--- a/target/i386/cpu.c
+++ b/target/i386
On Wed, 2020-05-20 at 10:17 +0100, Daniel P. Berrangé wrote:
> On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote:
> > There are no Icelake Desktop products in the market. Remove the
> > Icelake-Client CPU model.
>
> QEMU has been shipping this CPU model for 2 years now. Regardless
> of
On Sat, 2020-03-28 at 11:06 +0800, Chenyi Qiang wrote:
> Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID
> feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX.
>
> Signed-off-by: Chenyi Qiang
> ---
> target/i386/cpu.c | 10 ++
> 1 file changed, 10
On Thu, 2020-03-26 at 08:26 -0500, Eric Blake wrote:
> On 3/25/20 9:09 PM, Hu, Robert wrote:
> > (Don't know why my Linux-Evolution missed this mail.)
> > > -Original Message-
> > > Long line; it's nice to wrap commit messages around column 70 or
> > > so (because
> > > reading 'git log'
By increasing avx2 length_to_accel to 128, we can simplify its logic and reduce
a
branch.
The authorship of this patch actually belongs to Richard Henderson
,
I just fix a boudary case on his original patch.
Suggested-by: Richard Henderson
Signed-off-by: Robert Hoo
---
util/bufferiszero.c
Because in unit test, init_accel() will be called several times, each with
different accelerator type.
Signed-off-by: Robert Hoo
---
util/bufferiszero.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index 6639035..b801253 100644
--- a/util
-programming-reference.pdf
Signed-off-by: Robert Hoo
Reviewed-by: Richard Henderson
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
--- a/configure
+++ b/configure
@@ -1395,6 +1395,11
ase in select_accel_fn(), and have a
global variable alongside buffer_accel)
3. Changes avx512f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configure: add configure option avx512f_opt
u
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 74 +---
2 files changed, 67 insertions(+), 10 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245 100644
On Fri, 2020-02-28 at 18:09 -0800, Richard Henderson wrote:
> On 2/27/20 6:24 PM, Robert Hoo wrote:
> > if ((bv & 6) == 6 && (b & bit_AVX2)) {
> > cache |= CACHE_AVX2;
> > }
> > +
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 67 +---
2 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245 100644
-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
--- a/configure
+++ b/configure
@@ -1395,6 +1395,11 @@ for opt do
;;
--enable-avx2
12f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configure: add configure option avx512f_opt
util: add util function buffer_zero_avx512()
configure|
.
buffer_zero_avx2()).
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 64
2 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245
/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 41 +
1 file changed, 41 insertions(+)
diff --git a/configure b/configure
index d57261e..a0b41ce 100755
dle the case in select_accel_fn(), and have a
global variable alongside buffer_accel)
3. Changes avx512f configuration option's default status to disabled.
4. Ran 'make check-unit' on this patch, on both a Ivybridge machine and a
CascadeLake machine.
Robert Hoo (2):
configure: add configure opt
On Mon, 2020-02-24 at 08:13 -0800, Richard Henderson wrote:
> On 2/23/20 11:07 PM, Robert Hoo wrote:
> > Inspired by your suggestion, I'm thinking go further: use immediate
> > rather than a global variable, so that saves 1 memory(/cache)
> > access.
> >
&g
Thanks Richard:-)
Sorry for late reply.
On Thu, 2020-02-13 at 10:20 -0800, Richard Henderson wrote:
> On 2/12/20 11:52 PM, Robert Hoo wrote:
> > And initialize buffer_is_zero() with it, when Intel AVX512F is
> > available on host.
> >
> > This function utiliz
On Thu, 2020-02-13 at 11:30 +0100, Paolo Bonzini wrote:
> On 13/02/20 08:52, Robert Hoo wrote:
> > +
> > +}
> > +#pragma GCC pop_options
> > +#endif
> > +
> > +
> > /* Note that for test_buffer_is_zero_next_accel, the most
> > prefer
-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 39 +++
1 file changed, 39 insertions(+)
diff --git a/configure b/configure
index 115dc38..9bf8de0 100755
--- a/configure
+++ b/configure
@@ -1382,6 +1382,11 @@ for opt do
;;
--enable-avx2
And initialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
perform over previous AVX2 instructions.
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 56
1. Add avx512_opt option and enable it when host has the ability
2. Implement new buffer_zero_avx512() with AVX512F instructions
Robert Hoo (2):
configure: add configure option avx512f_opt
util: add function buffer_zero_avx512()
configure| 39
impact.
>
> Include a test case that should detect the problem if we introduce
> a similar bug again.
>
> Fixes: c7a88b52f62b ("i386: Add new model of Cascadelake-Server")
> Fixes: 8a11c62da914 ("i386: Add new CPU model Icelake-
> {Server,Client}")
On Sat, 2018-12-22 at 10:13 +0100, Paolo Bonzini wrote:
> On 22/12/18 02:01, Robert Hoo wrote:
> > On Fri, 2018-12-21 at 16:27 +0100, Paolo Bonzini wrote:
> > > On 21/12/18 16:22, Philippe Mathieu-Daudé wrote:
> > > > Hi Paolo,
> > > >
> &
On Fri, 2018-12-21 at 16:27 +0100, Paolo Bonzini wrote:
> On 21/12/18 16:22, Philippe Mathieu-Daudé wrote:
> > Hi Paolo,
> >
> > On 12/21/18 7:30 AM, Paolo Bonzini wrote:
> > > From: Robert Hoo
> > >
> > > Processor tracing is not yet imple
On Fri, 2018-12-21 at 16:03 +0100, Paolo Bonzini wrote:
> On 21/12/18 15:04, Robert Hoo wrote:
> > > So this series is correct and I will follow up with one for
> > > INTEL_PT;
> > > however, this begs the question of how the patches are being
> > > tested.
On Fri, 2018-12-21 at 07:27 +0100, Paolo Bonzini wrote:
> On 20/12/18 13:50, Robert Hoo wrote:
> > On Thu, 2018-12-20 at 13:38 +0100, Paolo Bonzini wrote:
> > > On 20/12/18 01:18, Robert Hoo wrote:
> > > > I think the sooner, the better. Take the time window th
On Thu, 2018-12-20 at 13:38 +0100, Paolo Bonzini wrote:
> On 20/12/18 01:18, Robert Hoo wrote:
> > On Wed, 2018-12-19 at 14:01 +, Daniel P. Berrangé wrote:
> > > On Wed, Dec 19, 2018 at 09:44:40PM +0800, Robert Hoo wrote:
> > > > Signed-off-by: Robert Hoo
&g
On Wed, 2018-12-19 at 14:01 +, Daniel P. Berrangé wrote:
> On Wed, Dec 19, 2018 at 09:44:40PM +0800, Robert Hoo wrote:
> > Signed-off-by: Robert Hoo
> > ---
> > target/i386/cpu.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff
This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b.
For new instruction 'PCONFIG' will not be exposed to guest.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 677a3bd..b6113d0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2613,8 +2613,7 @@ static X86CPUDefinition builtin_x86_defs
PCONFIG is not supposed to be exposed to guest. These 2 patches fix this.
Robert Hoo (2):
i386: remove the new CPUID 'PCONFIG' from Icelake-Server CPU model
Revert "i386: Add CPUID bit for PCONFIG"
target/i386/cpu.c | 5 ++---
target/i386/cpu.h | 1 -
2 files changed, 2 insert
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 205 --
target/i386
(sprintf).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Changes in v6: filter out MSR features whose dependent CPUID enumeration is not
there.
Signed-off-by: Robert Hoo
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 31
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
Reviewed-by: Eduardo Habkost
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 80
On Wed, 2018-10-24 at 07:06 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert
On Wed, 2018-10-24 at 07:06 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert
On Wed, 2018-10-24 at 07:16 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:24PM +0800, Robert Hoo wrote:
> > Add FeatureWordType indicator in struct FeatureWordInfo.
> > Change feature_word_info[] accordingly.
> > Change existing functions that refer
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 188 +++---
1 file changed
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 31 ++-
target/i386/cpu.h | 8
target/i386/kvm.c | 11 +++
3 files changed, 49 insertions(+), 1
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 80
2
wrapper (g_strdup_printf) instead of native
(sprintf).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data struc
On Thu, 2018-09-20 at 14:18 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 05:55:48PM +0800, Robert Hoo wrote:
> > On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> > > On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > > >
On Thu, 2018-09-20 at 14:22 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 03:45:42PM +0800, Robert Hoo wrote:
> [...]
> > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > > index a252c26..0160e97 100644
> > > > --- a/target/
On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert Ho
On Thu, 2018-09-20 at 00:07 -0300, Eduardo Habkost wrote:
> Hi,
>
> Thanks for the patch and sorry for taking so long to review it.
Never mind. I understand you're really busy. :-)
>
> On Sun, Sep 02, 2018 at 07:46:06PM +0800, Robert Hoo wrote:
> > Add kvm_get_supported_
On Sun, 2018-09-02 at 19:46 +0800, Robert Hoo wrote:
Ping ... :-)
> KVM side has added the framework (kvm.git:d1d93fa90) to support MSR
> based features.
> Here is the QEMU part, including data structure changes/expanding,
> referring
> functions changes, and the
more important that you follow the backwards-
> > > compatibility rules and
> > > not rename or delete any previously-mandatory members, since
> > > libvirt CAN'T
> > > introspect if such changes have happened.
> > >
> >
> > [Robert Hoo]
> > Oh,
On Fri, 2018-08-17 at 17:52 +0200, Paolo Bonzini wrote:
> On 10/08/2018 16:06, Robert Hoo wrote:
> > x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only.
>
> This should also grow support for MSR feature words.
>
> My suggestion is that you add another patch after
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 172 +-
1 file changed
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 27 ++-
target/i386/cpu.h | 12
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target/i386
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/cpu.c| 7 ++---
target/i386/kvm.c| 72
).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and
KVM_GET_MSRS system ioctl
x86: de
On Thu, 2018-08-23 at 14:11 -0300, Eduardo Habkost wrote:
> On Thu, Aug 23, 2018 at 02:28:28PM +0800, Robert Hoo wrote:
> > On Sat, 2018-08-18 at 12:05 -0300, Eduardo Habkost wrote:
> [...]
> > > We don't want QEMU to refuse to run if the kernel doesn't have
> > > KVM
On Sat, 2018-08-18 at 12:05 -0300, Eduardo Habkost wrote:
> > > >
> > > > int kvm_has_pit_state2(void)
> > > > {
> > > > @@ -420,6 +421,41 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s,
> > > > uint32_t function,
> > > > return ret;
> > > > }
> > > >
> > > > +uint32_t
On Fri, 2018-08-17 at 17:52 +0200, Paolo Bonzini wrote:
> On 10/08/2018 16:06, Robert Hoo wrote:
> > x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only.
>
> This should also grow support for MSR feature words.
>
> My suggestion is that you add another patch after
On Fri, 2018-08-17 at 10:28 -0300, Eduardo Habkost wrote:
> On Fri, Aug 10, 2018 at 10:06:29PM +0800, Robert Hoo wrote:
> > Add an util function feature_word_description(), which help construct the
> > string
> > describing the feature word (bot
On Fri, 2018-08-17 at 10:18 -0300, Eduardo Habkost wrote:
> Thanks for the patch, comments below:
>
> On Fri, Aug 10, 2018 at 10:06:28PM +0800, Robert Hoo wrote:
> > Add kvm_get_supported_feature_msrs() to get supported MSR feature index
> > list.
> > Add kvm_arc
On Sat, 2018-08-18 at 11:10 +0800, Robert Hoo wrote:
> On Fri, 2018-08-17 at 00:10 -0300, Eduardo Habkost wrote:
> [trim...]
> > > +
> > > typedef struct FeatureWordInfo {
> > > -/* feature flags names are taken from "Intel Processor
> > > Ide
On Fri, 2018-08-17 at 00:10 -0300, Eduardo Habkost wrote:
[trim...]
> > +
> > typedef struct FeatureWordInfo {
> > -/* feature flags names are taken from "Intel Processor Identification
> > and
> > +FeatureWordType type;
> > + /* feature flags names are taken from "Intel Processor
On Fri, 2018-08-10 at 10:17 -0500, Eric Blake wrote:
> On 08/10/2018 09:06 AM, Robert Hoo wrote:
>
> In the subject: s/funcitons/functions/
>
> Also, it may be worth using a topic prefix (most of our commit messages
> resemble:
>
> topic: Description of patch
>
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2 files
mp;3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
----
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change o
by
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 79
2 files changed, 81 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..97d8d9d 100644
--- a/include/sysemu/kvm.h
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 77 +--
1 file changed, 58 insertions(+), 19 deletions
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2 files
style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change other funcitons referring to feature_word_info[]
include/sysemu
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
by
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
KVM side has added the framework (kvm.git:d1d93fa90) to support MSR based
features.
Here is the QEMU part, including data structure changes/expanding, referring
functions changes, and the implementations on
KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl.
Robert Hoo (3):
x86
by
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2 files
On Fri, 2018-07-13 at 10:11 -0400, konrad.w...@oracle.com wrote:
> (Apologies if this comes out as HTML, using Thunderbird instead of mutt
> here)..
>
> > +uint64_t pred_cmd;
> > +uint64_t arch_capabilities;
>
> Could this be 'arch_cap' ?
>
> >
> > /* End of state preserved by
On Tue, 2018-07-03 at 08:00 -0300, Eduardo Habkost wrote:
> On Tue, Jul 03, 2018 at 03:35:13PM +0800, Robert Hoo wrote:
> > On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> > > On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > > > Suppor
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 ++-
target/i386/cpu.h | 1 +
2 files changed, 3 insertions(+), 1 deletion
expression frame work from CPUID features
only to MSR bit included as well.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5
del itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
target/i386/c
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 878b1ce..b83d0a9 100644
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a/target/i386
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
del itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
target/i386/c
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b0b87c3..7f787ef 100644
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f787ef..9407071 100644
On Tue, 2018-07-03 at 15:38 +0200, Paolo Bonzini wrote:
> On 03/07/2018 13:07, Robert Hoo wrote:
> >> FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
> >> FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> >> +FEATURE_WORDS_NUM_CPUID,
>
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