The upper 16 bits of kvm_userspace_memory_region::slot are
address space id. Parse it separately in trace_kvm_set_user_memory().
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c| 5 +++--
accel/kvm/trace-events | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/accel
On 7/23/2021 1:54 AM, Connor Kuehl wrote:
On 7/7/21 7:55 PM, isaku.yamah...@gmail.com wrote:
From: Isaku Yamahata
In TDX CPU state is also protected, thus vcpu state can't be reset by
VMM.
It assumes -action reboot=shutdown instead of silently ignoring vcpu
reset.
TDX module spec version
On 7/23/2021 1:53 AM, Connor Kuehl wrote:
On 7/7/21 7:55 PM, isaku.yamah...@gmail.com wrote:
From: Isaku Yamahata
Signed-off-by: Isaku Yamahata
---
include/sysemu/tdx.h | 1 +
target/i386/kvm/kvm.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/include/sysemu/tdx.h
On 8/26/2021 6:24 PM, Gerd Hoffmann wrote:
On Wed, Jul 07, 2021 at 05:54:37PM -0700, isaku.yamah...@gmail.com wrote:
From: Sean Christopherson
Ignore get/put state of TDX VMs as accessing/mutating guest state of
producation TDs is not supported.
Why silently ignore instead of returning an
On 7/23/2021 1:53 AM, Connor Kuehl wrote:
On 7/7/21 7:54 PM, isaku.yamah...@gmail.com wrote:
From: Xiaoyao Li
Reuse -cpu,tsc-frequency= to get user wanted tsc frequency and pass it
to KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity
On 8/26/2021 6:22 PM, Gerd Hoffmann wrote:
On Wed, Jul 07, 2021 at 05:54:36PM -0700, isaku.yamah...@gmail.com wrote:
From: Xiaoyao Li
Introduce a machine property, kvm-type, to allow the user to create a
Trusted Domain eXtensions (TDX) VM, a.k.a. a Trusted Domain (TD), e.g.:
# $QEMU
On 10/18/2021 11:46 AM, Xiaoyao Li wrote:
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fix
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
set (from ICX) for any CPU model o
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
set (from ICX) for any CPU model o
On 10/16/2021 12:04 AM, Eduardo Habkost wrote:
Hi,
Apologies for the delay. Comments below:
On Thu, Sep 09, 2021 at 10:41:47PM +0800, Xiaoyao Li wrote:
CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and
capability of Intel PT.
Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX
Ping...
Eduardo, could you please take a look at this series.
Thanks!
-Xiaoyao
On 9/9/2021 10:41 PM, Xiaoyao Li wrote:
Initial Intel PT support was added by making it as fixed feature set as
ICX's capabilities, which allowed different CPU model with PT enabled
live migration on ICX host
For IceLake-server, it's just the same as using the default PT
feature set since the default one is exact taken from ICX.
For Snowridge, define it according to real SNR silicon capabilities.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 20
1 file changed, 20
Some CPUID leaves have meaningful subleaf index. Print the subleaf info
in feature_word_description for CPUID features.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
named CPU model, e.g., Sapphire Rapids, can define
its own PT feature set by setting @has_specific_intel_pt_feature_set to
true and defines it's own FEAT_14_0_EBX, FEAT_14_0_ECX, FEAT_14_1_EAX
and FEAT_14_1_EBX.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 106 --
break live migration.
Xiaoyao Li (5):
target/i386: Print CPUID subleaf info for unsupported feature
target/i386: Introduce FeatureWordInfo for Intel PT CPUID leaf 0xD
target/i386: Enable host pass through of Intel PT
target/i386: Define specific PT feature set for IceLake-server and
KVM only allows userspace to access legal number of MSR_IA32_RTIT_ADDRn,
which is enumrated by guest's CPUID(0x14,0x1):EAX[2:0], i.e.,
env->features[FEAT_14_1_EAX] & INTEL_PT_ADDR_RANGES_NUM_MASK
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 1 -
target/i386/cpu.h | 2 ++
as special handling for FEAT_14_1_EAX[2:0], because the 3 bits as a
whole represents the number of PT ADDRn_CFG ranges. Thus it has special
handling in mark_unavailable_features() and x86_cpu_filter_features().
Signed-off-by: Xiaoyao Li
---
target/i386/
On 8/26/2021 4:48 AM, Eduardo Habkost wrote:
On Wed, Aug 25, 2021 at 02:59:37PM +0800, Xiaoyao Li wrote:
Hi Eduardo,
I have some question regrading Intel PT live migration.
Commit "e37a5c7fa459 (i386: Add Intel Processor Trace feature support)"
expose Intel PT with a fixed ca
Hi Eduardo,
I have some question regrading Intel PT live migration.
Commit "e37a5c7fa459 (i386: Add Intel Processor Trace feature support)"
expose Intel PT with a fixed capabilities of CPUID 0x14 for live
migration. And the fixed capabilities are the value reported on
ICX(IceLake). However,
On 4/21/2021 11:18 PM, Eduardo Habkost wrote:
On Wed, Apr 21, 2021 at 10:50:10PM +0800, Xiaoyao Li wrote:
On 4/21/2021 10:12 PM, Eduardo Habkost wrote:
On Wed, Apr 21, 2021 at 02:26:42PM +0800, Chenyi Qiang wrote:
Hi, Eduardo, thanks for your comments!
On 4/21/2021 12:34 AM, Eduardo Habkost
On 4/21/2021 10:12 PM, Eduardo Habkost wrote:
On Wed, Apr 21, 2021 at 02:26:42PM +0800, Chenyi Qiang wrote:
Hi, Eduardo, thanks for your comments!
On 4/21/2021 12:34 AM, Eduardo Habkost wrote:
Hello,
Thanks for the patch. Comments below:
On Tue, Apr 20, 2021 at 05:37:36PM +0800, Chenyi
On 3/19/2021 10:59 AM, Chenyi Qiang wrote:
Hi Marcelo,
Thank you for your comment.
On 3/19/2021 1:32 AM, Marcelo Tosatti wrote:
On Wed, Mar 17, 2021 at 04:47:09PM +0800, Chenyi Qiang wrote:
Virtual Machines can exploit bus locks to degrade the performance of
system. To address this kind of
On 3/17/2021 4:47 PM, Chenyi Qiang wrote:
[...]
MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
{
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -4236,6 +4271,11 @@ MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct
kvm_run *run)
} else {
env->eflags &= ~IF_MASK;
On 8/25/2020 10:01 PM, Eduardo Habkost wrote:
On Tue, Aug 25, 2020 at 08:20:35AM +0800, Xiaoyao Li wrote:
On 8/25/2020 6:07 AM, Eduardo Habkost wrote:
On Wed, Dec 25, 2019 at 02:30:18PM +0800, Xiaoyao Li wrote:
It lacks VMX features and two security feature bits (disclosed recently
On 8/25/2020 6:07 AM, Eduardo Habkost wrote:
On Wed, Dec 25, 2019 at 02:30:18PM +0800, Xiaoyao Li wrote:
It lacks VMX features and two security feature bits (disclosed recently) in
MSR_IA32_ARCH_CAPABILITIES in current Cooperlake CPU model, so add them.
Fixes: 22a866b6166d ("i386: Add ne
On 7/16/2020 11:14 PM, Eduardo Habkost wrote:
On Thu, Jul 16, 2020 at 04:20:19PM +0800, Xiaoyao Li wrote:
When setting up XSAVE components, it needs to mask off those unsupported
by KVM.
Signed-off-by: Xiaoyao Li
We must never disable CPUID features silently based on host
capabilities
On 7/16/2020 11:15 PM, Eduardo Habkost wrote:
On Thu, Jul 16, 2020 at 04:20:18PM +0800, Xiaoyao Li wrote:
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
Can you explain what's the bug you are trying
Two simple fixes for XSAVE component features, please see each one
for details.
Xiaoyao Li (2):
i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available
i386/cpu: Mask off unsupported XSAVE components
target/i386/cpu.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions
When setting up XSAVE components, it needs to mask off those unsupported
by KVM.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f5f11603e805..efc92334b7b1 100644
--- a/target
Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the
processor provides no further enumeration through CPUID function 0DH.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1e5123251d74
On 5/10/2020 9:42 AM, Yang Weijiang wrote:
CET SHSTK/IBT MSRs can be saved/restored with XSAVES/XRSTORS, but
currently the related feature words are not supported, so add the
new entries. XSAVES/RSTORS always use compacted storage format, which
means the supervisor states' offsets are always 0,
On 5/10/2020 9:42 AM, Yang Weijiang wrote:
CET feature SHSTK and IBT are enumerated via CPUID(EAX=0x7,0):ECX[bit 7]
and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in
MSR_IA32_XSS to support XSAVES/XRSTORS. CPUID(EAX=0xd, 1):ECX[bit 11] and
ECX[bit 12] correspond to CET
sm")
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9812d5747f35..fb1de1bd6165 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6370,7 +6370,6 @@ static void x86_cpu_expand_features(X8
Patch 1 fixes the env->features set by versioned CPU model.
Patch 2 fixed the env->features set by unavailable_features due to
feature_dependencies[] checking.
Xiaoyao Li (2):
i368/cpu: Clear env->user_features after loading versioned CPU model
i386/cpu: Don't add unavailable_featur
to
env->user_features later in x86_cpu_expand_features().
Cc: Chenyi Qiang
Suggested-by: Eduardo Habkost
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1e5123251d74..9812d5747f35 100644
--- a/ta
On 7/13/2020 10:44 PM, Eduardo Habkost wrote:
On Mon, Jul 13, 2020 at 03:45:55PM +0800, Xiaoyao Li wrote:
On 7/13/2020 3:23 PM, Chenyi Qiang wrote:
On 7/11/2020 12:48 AM, Eduardo Habkost wrote:
On Fri, Jul 10, 2020 at 09:45:49AM +0800, Chenyi Qiang wrote:
On 7/10/2020 6:12 AM, Eduardo
On 7/13/2020 3:23 PM, Chenyi Qiang wrote:
On 7/11/2020 12:48 AM, Eduardo Habkost wrote:
On Fri, Jul 10, 2020 at 09:45:49AM +0800, Chenyi Qiang wrote:
On 7/10/2020 6:12 AM, Eduardo Habkost wrote:
I'm very sorry for taking so long to review this. Question
below:
On Fri, Jun 19, 2020 at
On 3/28/2020 11:06 AM, Chenyi Qiang wrote:
Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID
feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX.
Signed-off-by: Chenyi Qiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: Xiaoyao Li
MSR_TEST_CTRL is needed and accessed by feature split lock detection.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 13 +
target/i386/machine.c | 20
3 files changed, 35 insertions(+)
diff --git a/target
Intel SDM updates the name of MSR CORE_CAPABILITY to CORE_CAPABILITIES,
so updating it QEMU.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 12 ++--
target/i386/cpu.h | 6 +++---
target/i386/kvm.c | 6 +++---
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target
Patch 1 renames core_capability to core_capabilities to align with the
latest SDM.
Patch 2 adds MSR_TEST_CTRL support.
Patch 3 prints info when guest is going to be killed due to split lock #AC
Xiaoyao Li (3):
target/i386: Rename CORE_CAPABILITY to CORE_CAPABILITIES
target/i386: Add support
Tell why guest exits from kvm to user space due to #AC, so user knows
what happened.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 411402aa29fa..36bc1485d478 100644
ion to add the .note ?
Maybe you can add it when queue?
Thanks,
-Xiaoyao
On 3/16/2020 5:56 PM, Xiaoyao Li wrote:
Current Icelake-Server CPU model lacks all the features enumerated by
MSR_IA32_ARCH_CAPABILITIES.
Add them, so that guest of "Icelake-Server" can see all of them.
Signed-off-by
Current Icelake-Server CPU model lacks all the features enumerated by
MSR_IA32_ARCH_CAPABILITIES.
Add them, so that guest of "Icelake-Server" can see all of them.
Signed-off-by: Xiaoyao Li
---
v2:
- Add it as a new version.
---
target/i386/cpu.c | 13 +
1 file c
Current Icelake-Server CPU model lacks all the features enumerated by
MSR_IA32_ARCH_CAPABILITIES.
Add them, so that guest of "Icelake-Server" can see all of them.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --gi
On Tue, 2020-01-07 at 11:32 +0100, Paolo Bonzini wrote:
> On 28/12/19 11:43, Xiaoyao Li wrote:
> > Commit 11bc4a13d1f4 ("kvm: convert "-machine kernel_irqchip" to an
> > accelerator property") moves kernel_irqchip property from "-machine" to
> &
On Sat, 2019-12-28 at 10:57 +, Paolo Bonzini wrote:
>
>
> Il sab 28 dic 2019, 10:24 Xiaoyao Li ha scritto:
> > BTW, it seems that this patch makes kernel_irqchip default on to workaround
> > the
> > bug.
> > However, when explicitly configuring kern
so cleaning up the three useless members (kernel_irqchip_allowed,
kernel_irqchip_required, kernel_irqchip_split) in struct MachineState.
Fixes: 11bc4a13d1f4 ("kvm: convert "-machine kernel_irqchip" to an accelerator
property")
Reported-by: Vitaly Kuznetsov
Signed-off-by: Xiaoyao Li
On Sat, 2019-12-28 at 10:02 +, Paolo Bonzini wrote:
>
>
> Il sab 28 dic 2019, 09:48 Xiaoyao Li ha scritto:
> > Commit 11bc4a13d1f4 ("kvm: convert "-machine kernel_irqchip" to an
> > accelerator property") moves kernel_irqchip property from "
so cleaning up the three useless members (kernel_irqchip_allowed,
kernel_irqchip_required, kernel_irqchip_split) in struct MachineState.
Fixes: 11bc4a13d1f4 ("kvm: convert "-machine kernel_irqchip" to an accelerator
property")
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c | 3 +++
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
for some security issues. Add the definitions for them to be used by named
CPU models.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.h | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target
It lacks VMX features and two security feature bits (disclosed recently) in
MSR_IA32_ARCH_CAPABILITIES in current Cooperlake CPU model, so add them.
Fixes: 22a866b6166d ("i386: Add new CPU model Cooperlake")
Signed-off-by: Xiaoyao Li
---
target/i386/
Current Cooperlake CPU model lacks VMX features which are introduced by Paolo
several months ago, and it also lacks 2 security features in
MSR_IA32_ARCH_CAPABILITIES disclosed recently.
Xiaoyao Li (2):
target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
target/i386: Add missed
-by: Cathy Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Tao Xu
Message-Id: <1571729728-23284-4-git-send-email-cathy.zh...@intel.com>
Reviewed-by: Bruce Rogers
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 60 +++
1 file chang
On 12/2/2019 2:32 PM, Tao Xu wrote:
This series of patches will remove MPX from Denverton, remove Remove
monitor from some CPU models. Add additional information for -cpu help
to indicate the changes in this version of CPU model.
The output is as follows:
x86_64-softmmu/qemu-system-x86_64 -cpu
On 12/2/2019 2:32 PM, Tao Xu wrote:
Add which features are added or removed in this version. Remove the
changed model-id in versioned CPU models.
Signed-off-by: Tao Xu
---
target/i386/cpu.c | 50 +++
1 file changed, 25 insertions(+), 25
On Sat, 2019-10-12 at 01:56 -0700, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20191012024748.127135-1-xiaoyao...@intel.com/
>
>
>
> Hi,
>
> This series failed the docker-mingw@fedora build test. Please find the testing
> commands and
> their output below. If you
Add new version of Snowridge CPU model that removes MPX feature.
MPX support is being phased out by Intel. GCC has dropped it, Linux kernel
and KVM are also going to do that in the future.
Signed-off-by: Xiaoyao Li
---
Changes in v3:
- Remove the .alias field (ehabkost)
Changes in v2
On 10/12/2019 9:21 AM, Eduardo Habkost wrote:
On Sat, Oct 12, 2019 at 09:15:56AM +0800, Xiaoyao Li wrote:
On 10/12/2019 2:21 AM, Eduardo Habkost wrote:
On Fri, Oct 11, 2019 at 10:53:49PM +0800, Xiaoyao Li wrote:
Add new version of Snowridge CPU model that removes MPX feature.
MPX support
On 10/12/2019 2:21 AM, Eduardo Habkost wrote:
On Fri, Oct 11, 2019 at 10:53:49PM +0800, Xiaoyao Li wrote:
Add new version of Snowridge CPU model that removes MPX feature.
MPX support is being phased out by Intel. GCC has dropped it, Linux kernel
and kvm are also going to do that in the future
Add new version of Snowridge CPU model that removes MPX feature.
MPX support is being phased out by Intel. GCC has dropped it, Linux kernel
and kvm are also going to do that in the future.
Signed-off-by: Xiaoyao Li
---
Changes in v2:
- Use CPU model versioning mechanism instead of machine
On Fri, 2019-10-11 at 09:57 -0300, Eduardo Habkost wrote:
> On Fri, Oct 11, 2019 at 03:18:44PM +0800, Xiaoyao Li wrote:
> > MPX support is being phased out by Intel. Following other CPU models
> > like Skylake, Icelake and Cascadelake, do not enable it by default.
> >
>
MPX support is being phased out by Intel. Following other CPU models
like Skylake, Icelake and Cascadelake, do not enable it by default.
Signed-off-by: Xiaoyao Li
---
I'm not sure is there anyone already use Snowridge CPU model and whether to
add it in pc_compat_4_1, since Snowridge has not been
On 7/18/2019 9:56 AM, Tao Xu wrote:
On 7/18/2019 2:38 AM, Eduardo Habkost wrote:
On Wed, Jul 17, 2019 at 01:39:01PM +0800, Tao Xu wrote:
Hi Eduardo,
Could I ask a question about introducing a old CPU model? Maybe not
so old
because it was launched in 2017. It is the former generation (Atom
On Tue, 2019-07-09 at 22:27 +0800, Tao Xu wrote:
> On 7/9/2019 4:39 PM, Xiaoyao Li wrote:
> > On 7/9/2019 12:44 PM, Tao Xu wrote:
> > > Denverton-Server is the Atom Processor of Intel Harrisonville platform.
> > >
> > > For more information:
> > >
On 7/9/2019 12:44 PM, Tao Xu wrote:
Denverton-Server is the Atom Processor of Intel Harrisonville platform.
For more information:
https://ark.intel.com/content/www/us/en/ark/products/\
codename/63508/denverton.html
Signed-off-by: Tao Xu
---
target/i386/cpu.c | 45
Hi, Eduardo
On 7/2/2019 11:35 PM, Eduardo Habkost wrote:
Add new version of Cascadelake-Server CPU model, setting
stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
with some flags.
The new feature will introduce a new host software requirement,
breaking our CPU model runnability promises.
On 6/28/2019 8:28 AM, Eduardo Habkost wrote:
Add new version of Cascadelake-Server CPU model, setting
stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
with some flags.
The new feature will introduce a new host software requirement,
breaking our CPU model runnability promises. This means
/1909
Signed-off-by: Xiaoyao Li
---
Changelog:
v2
Add definition of MSR_CORE_CAP_SPLIT_LOCK_DETECT for SNR cpu model
---
target/i386/cpu.c | 22 +-
target/i386/cpu.h | 5 +
target/i386/kvm.c | 9 +
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git
On 6/16/2019 11:35 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Patches 15-17 of kvm are exposing this feature to guest.
If host has split lock detection feature, we can expose it to guest by
using '-cpu host' with this patch and kernel's patches.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 22 +-
target/i386/cpu.h | 3 +++
target
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