Hi Paolo,
On Mon, Dec 14, 2015 at 11:17 AM, Paolo Bonzini wrote:
>
>
> On 14/12/2015 11:04, alvise rigo wrote:
>> In any case, what I proposed in the mttcg based v5 was:
>> - A LL ensures that the TLB_EXCL flag is set on all the CPU's TLB.
>> This is done by
Hi Andreas,
On Mon, Dec 14, 2015 at 11:09 PM, Andreas Tobler wrote:
> Alvise,
>
> On 14.12.15 09:41, Alvise Rigo wrote:
>>
>> This is the sixth iteration of the patch series which applies to the
>> upstream branch of QEMU (v2.5.0-rc3).
>>
>> Changes versus
Hi Paolo,
Thank you for your feedback.
On Mon, Dec 14, 2015 at 10:33 AM, Paolo Bonzini wrote:
>
>
>
> On 14/12/2015 09:41, Alvise Rigo wrote:
> > In theory, the provided implementation of TCG LoadLink/StoreConditional
> > can be used to properly handle atomic instruct
ed-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 20 +++-
softmmu_llsc_template.h | 25 ++---
softmmu_template.h | 38 --
3 files changed, 45 insertions(+), 38 deletions(-)
diff --git a/cpu
Add a simple helper function to emulate the CLREX instruction.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 6 ++
target-arm/translate.c | 1 +
3 files changed, 9 insertions(+)
diff --git
.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/translate.c | 101 +++--
1 file changed, 97 insertions(+), 4 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5d22879..e88d8a3
ility to forget the EXCL bit set.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 32 ++--
include/qom/cpu.h | 3 +++
softmmu_llsc_template.h | 2 ++
3 files changed, 27 insertions(+), 10 dele
Introduce a set of new runtime helpers do handle exclusive instructions.
This helpers are used as hooks to call the respective LL/SC helpers in
softmmu_llsc_template.h from TCG code.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
Makefile.target
Attempting to simplify the helper_*_st_name, wrap the code relative to a
RAM access into an inline function.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 110 +
1 file changed
; can be a store made by *any* vCPU
(although, some implementations allow stores made by the CPU that issued
the LoadLink).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 3 ++
softmmu_llsc_templa
usive range in
case of collision.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 20 +---
include/exec/memory.h | 1 +
softmmu_llsc_template.h | 11 ---
softmmu_template.h | 22
Add a new TLB flag to force all the accesses made to a page to follow
the slow-path.
In the case we remove a TLB entry marked as EXCL, we unset the
corresponding exclusive bit in the bitmap.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c
Attempting to simplify the helper_*_st_name, wrap the
do_unaligned_access code into an inline function.
Remove also the goto statement.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 96
n % 8.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
exec.c | 8 --
include/exec/memory.h | 3 +-
include/exec/ram_addr.h | 76 +
3 files changed, 84 insertions(+), 3 deletions
Attempting to simplify the helper_*_st_name, wrap the MMIO code into an
inline function.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 64 +-
1 file changed, 44 insertions
Use the new slow path for atomic instruction translation when the
softmmu is enabled.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index b9552fd..cc3891a 100755
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
include/qom/cpu.h | 4
qom/cpu.c | 7 +++
2 files changed, 11 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index c6bb6b6..9e409ce 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -175,6 +175,10
s from Richard Henderson to improve the logic in
softmmu_template.h and to simplify the methods generation through
softmmu_llsc_template.h
- Added initial implementation of qemu_{ldlink,stcond}_i32 for tcg/i386
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rig
On Wed, Sep 30, 2015 at 10:42 PM, Richard Henderson wrote:
>
> On 09/30/2015 07:46 PM, alvise rigo wrote:
>>
>> On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson wrote:
>>>
>>> Why would you need to indicate that another cpu has started an exclusive
>
On Wed, Sep 30, 2015 at 1:09 PM, Peter Maydell wrote:
> On 30 September 2015 at 10:24, alvise rigo
> wrote:
>> On Wed, Sep 30, 2015 at 5:34 AM, Richard Henderson wrote:
>>> (1) I don't see why EXCL support should differ whether MMIO is set or not.
>>> Eith
On Wed, Sep 30, 2015 at 6:03 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> Introduce a set of new runtime helpers do handle exclusive instructions.
>> This helpers are used as hooks to call the respective LL/SC helpers in
>> softmmu_ll
On Wed, Sep 30, 2015 at 6:05 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> Use the new slow path for atomic instruction translation when the
>> softmmu is enabled.
>
>
> Um... why? TCG_USE_LDST_EXCL would appear to be 100% r
On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> The new helpers rely on the legacy ones to perform the actual read/write.
>>
>> The LoadLink helper (helper_ldlink_name) prepares the way for the
>> fo
On Wed, Sep 30, 2015 at 5:34 AM, Richard Henderson wrote:
> On 09/24/2015 06:32 PM, Alvise Rigo wrote:
>>
>> +if (unlikely(!(te->addr_write & TLB_MMIO) && (te->addr_write &
>> TLB_EXCL))) {
>> +/* We are removing an exclusive entry, set
Hi Paolo,
On Wed, Sep 30, 2015 at 6:44 AM, Paolo Bonzini wrote:
>
>
> On 24/09/2015 10:32, Alvise Rigo wrote:
>> The implementation heavily uses the software TLB together with a new
>> bitmap that has been added to the ram_list structure which flags, on a
>> per-CPU
On Sat, Sep 26, 2015 at 7:15 PM, Richard Henderson wrote:
> On 09/24/2015 01:32 AM, Alvise Rigo wrote:
> > +if (cpu == smp_cpus) {
> > +if (smp_cpus >= EXCL_BITMAP_CELL_SZ) {
> > +return bitmap[EXCL_BITMAP_GET_BYTE_OFFSET(add
Use the new slow path for atomic instruction translation when the
softmmu is enabled.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
configure | 11 +++
1 file changed, 11 insertions(+)
diff --git a/configure b/configure
index cd219d8
Add a new TLB flag to force all the accesses made to a page to follow
the slow-path.
In the case we remove a TLB entry marked as EXCL, we unset the
corresponding exclusive bit in the bitmap.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c
n % 8.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
exec.c | 8 --
include/exec/memory.h | 3 +-
include/exec/ram_addr.h | 75 +
3 files changed, 83 insertions(+), 3 deletions
ion of qemu_{ldlink,stcond}_i32 for tcg/i386
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rigo (6):
exec.c: Add new exclusive bitmap to ram_list
softmmu: Add new TLB_EXCL flag
softmmu: Add helpers for a new slowpath
target-arm: Create new runtime helpers for
.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/translate.c | 121 +++--
1 file changed, 117 insertions(+), 4 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 69ac18c..fa85455
; can be a store made by *any* vCPU
(although, some implementations allow stores made by the CPU that issued
the LoadLink).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 3 ++
softmmu_llsc_templa
Introduce a set of new runtime helpers do handle exclusive instructions.
This helpers are used as hooks to call the respective LL/SC helpers in
softmmu_llsc_template.h from TCG code.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/helper.h
Hi Alex,
On Thu, Sep 10, 2015 at 6:19 PM, Alex Bennée wrote:
>
> alvise rigo writes:
>
>> Hi Paolo,
>>
>> A brief update on this. I have a first implementation of the idea you
>> proposed, though it's not working really well. The failing rate of SCs
>&
s I'm missing some advantages of your proposal except the
less aggressive memory consumption, I would go with this design.
Regards,
alvise
On Wed, Aug 12, 2015 at 2:36 PM, Paolo Bonzini wrote:
>
>
> On 12/08/2015 09:31, alvise rigo wrote:
>> I think that tlb_flush_entry is no
Hi Frederic,
On Wed, Aug 26, 2015 at 2:18 PM, Frederic Konrad
wrote:
> Hi everybody,
>
> I'm trying to do the next version of the MTTCG work:
>
> I would like to rebase on Alvise atomic instruction branch:
> - Alvise can you rebase it on the 2.4.0 version without MTTCG support and
> then
>
mttcg
The [PATCH 6/6] is the first step to use runtime helpers in place of the
TCG load/store instructions as suggested by Aurelien Jarno.
The patch-series addresses also some of the Paolo's comments, however
the exclusive bitmap is still using one bit for each vCPU.
Alvise Rigo (6):
cpus: a
Exploiting the tcg_excl_access_lock, port the helper_{le,be}_st_name to
work in real multithreading.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
softmmu_template.h | 36 ++--
1 file changed, 30 insertions(+), 6
ned-off-by: Alvise Rigo
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 11 +++
target-arm/translate.c | 12 +++-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index c77bf04..c4da74a 100644
--- a/target-arm/help
Signed-off-by: Alvise Rigo
---
include/exec/ram_addr.h | 61 +
1 file changed, 51 insertions(+), 10 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 6b678d6..34bb486 100644
--- a/include/exec/ram_addr.h
+++ b
In some unique situations a vCPU can be kicked even if it's not ready to
execute TCG code i.e. when current_tb has never been set before.
This can happen with the atomic stress test (not kvm-unit-test based),
where a vCPU can query some work to a not yet started vCPU.
Signed-off-by: Alvise
Introduce the new tlb_query_flush_cpu function to query a TLB flush
to a given vCPU.
The function takes care to check and set a new flag (pending_tlb_flush)
to avoid unnecessary flushes.
Signed-off-by: Alvise Rigo
---
cputlb.c| 21 -
include/exec/exec-all.h
addresses the same purpose.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 4
softmmu_llsc_template.h | 59 -
2 files changed, 48 insertions(+), 15 deletions(-)
diff --git a
On Wed, Aug 12, 2015 at 4:10 PM, Paolo Bonzini wrote:
>
>
> On 12/08/2015 16:04, alvise rigo wrote:
>>> > clear algorithm:
>>> >if bytemap[vaddr] == 254
>>> > bytemap[vaddr] = CPU_ID
>> Isn't this also required fo
On Wed, Aug 12, 2015 at 2:36 PM, Paolo Bonzini wrote:
>
>
> On 12/08/2015 09:31, alvise rigo wrote:
>> I think that tlb_flush_entry is not enough, since in theory another
>> vCPU could have a different TLB address referring the same phys
>> address.
>
> Yo
ini wrote:
>
>
> On 07/08/2015 19:03, Alvise Rigo wrote:
>> +
>> +/* For this vCPU, just update the TLB entry, no need to flush. */
>> +env->tlb_table[mmu_idx][index].addr_write |= TLB_EXCL;
>
> Couldn't this vCPU also have two aliasing entries in the TLB?
>
> Paolo
I think that tlb_flush_entry is not enough, since in theory another
vCPU could have a different TLB address referring the same phys
address.
alvise
On Tue, Aug 11, 2015 at 6:32 PM, Paolo Bonzini wrote:
>
>
> On 11/08/2015 18:11, alvise rigo wrote:
>>> > Why flush the entir
On Tue, Aug 11, 2015 at 5:55 PM, Paolo Bonzini wrote:
>
>
> On 11/08/2015 17:54, alvise rigo wrote:
>> This can lead to an excessive rate of flush requests, since for one
>> CPU that removes the TLB_EXCL flag, all the others that are competing
>> for the same excl add
On Tue, Aug 11, 2015 at 3:52 PM, Paolo Bonzini wrote:
>
>
> On 11/08/2015 15:32, alvise rigo wrote:
>>> > +#if DATA_SIZE > 1
>>> > +#define helper_ldlink_name glue(glue(helper_le_ldlink, USUFFIX),
>>> > MMUSUFFIX)
>>> > +#d
On Tue, Aug 11, 2015 at 3:52 PM, Paolo Bonzini wrote:
>
>
> On 07/08/2015 19:03, Alvise Rigo wrote:
>> +static inline int cpu_physical_memory_excl_atleast_one_clean(ram_addr_t
>> addr)
>> +{
>> +unsigned long *bitmap = ram_list.dirty_memory[DIRTY_MEMORY_EXCLU
On Tue, Aug 11, 2015 at 4:24 PM, Peter Maydell wrote:
> On 11 August 2015 at 14:52, Paolo Bonzini wrote:
>>
>> I don't think real hardware has ll/sc per CPU.
>
> On ARM, the exclusives are handled by the 'global monitor', which
> supports tracking an exclusive access per CPU.
>
>> Can we have th
On Fri, Aug 7, 2015 at 7:03 PM, Alvise Rigo
wrote:
> The new helpers rely on the legacy ones to perform the actual read/write.
>
> The LoadLink helper (helper_ldlink_name) prepares the way for the
> following SC operation. It sets the linked address and the size of the
> access.
Good point, I will look at the code you pointed.
If we really can avoid to modify every backend, than it's worth more
than a look.
Thanks,
alvise
On Sat, Aug 8, 2015 at 3:00 PM, Aurelien Jarno wrote:
> On 2015-08-07 19:03, Alvise Rigo wrote:
>> Implement exclusive variants of qem
Implement the exclusive variants of qemu_{ld,st}_{i32,i64} for
tcg-aarch64.
The lookup for the proper memory helper has been rewritten to take
into account the new exclusive helpers.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/aarch64/tcg
Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
exec.c | 7 +++--
include/exec/memory.h | 3 ++-
include/exec/ram_addr.h | 68 +
3 files changed, 75 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
; can be a store made by *any* vCPU
(although, some implementations allow stores made by the CPU that issued
the LoadLink).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 3 ++
softmmu_llsc_templa
Implement exclusive variants of qemu_{ld,st}_{i32,i64} for tcg-i386.
The lookup for the proper memory helper has been rewritten to take
into account the new exclusive helpers.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/i386/tcg-target.c | 148
Introduce the new --enable-tcg-ldst-excl configure option to enable the
LL/SC operations only for those backends that support them.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
configure | 21 +
1 file changed, 21 insertions
Implement the exclusive variants of qemu_{ld,st}_{i32,i64} for tcg-arm.
The lookup for the proper memory helper has been rewritten to take
into account the new exclusive helpers.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/arm/tcg-target.c
softmmu_template.h and to simplify the methods generation through
softmmu_llsc_template.h
- Added initial implementation of qemu_{ldlink,stcond}_i32 for tcg/i386
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rigo (9):
exec.c: Add new exclusive bitmap to ram_li
Use the TCG load and store exclusive operataions if QEMU has been
configured to do so.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/translate.c | 191 ++---
1 file changed, 183 insertions(+), 8
t the atomic slow path, then
including the qemu_stcond in the plain qemu_st will be much easier.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/tcg-be-ldst.h | 1 +
tcg/tcg-op.c | 65 +++
tc
Add a new TLB flag to force all the accesses made to a page to follow
the slow-path.
In the case we remove a TLB entry marked as EXCL, we unset the
corresponding exclusive bit in the bitmap.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c
On Mon, Aug 3, 2015 at 6:06 PM, Alex Bennée wrote:
>
> alvise rigo writes:
>
> > On Mon, Aug 3, 2015 at 12:30 PM, Alex Bennée
> wrote:
> >>
> >> alvise rigo writes:
> >>
> >>> Hi Alex,
> >>>
> >>
On Mon, Aug 3, 2015 at 12:30 PM, Alex Bennée wrote:
>
> alvise rigo writes:
>
>> Hi Alex,
>>
>> Nice set of tests, they are proving to be helpful.
>> One question below.
>>
>> On Fri, Jul 31, 2015 at 5:54 PM, Alex Bennée wrote:
>>> From: Ale
Hi Alex,
Nice set of tests, they are proving to be helpful.
One question below.
On Fri, Jul 31, 2015 at 5:54 PM, Alex Bennée wrote:
> From: Alex Bennée
>
> This test has been written mainly to stress multi-threaded TCG behaviour
> but will demonstrate failure by default on real hardware. The te
On Wed, Jul 22, 2015 at 3:56 PM, Alex Bennée wrote:
>
> alvise rigo writes:
>
>> On Mon, Jul 20, 2015 at 8:01 PM, Frederic Konrad
>> wrote:
>>> On 20/07/2015 19:41, alvise rigo wrote:
>>>>
>>>> Hi Alex,
>>>>
>>>>
On Mon, Jul 20, 2015 at 8:01 PM, Frederic Konrad
wrote:
> On 20/07/2015 19:41, alvise rigo wrote:
>>
>> Hi Alex,
>>
>> Thank you for this summary.
>> Some comments below.
>>
>> On Mon, Jul 20, 2015 at 6:17 PM, Alex Bennée
>> wrote:
>>>
Hi Alex,
Thank you for this summary.
Some comments below.
On Mon, Jul 20, 2015 at 6:17 PM, Alex Bennée wrote:
>
> Hi,
>
> Following this afternoons call I thought I'd summarise the state of the
> various patch series and their relative dependencies. We re-stated the
> aim should be to get what i
On Fri, Jul 17, 2015 at 5:57 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> Exploiting the tcg_excl_access_lock, port the helper_{le,be}_st_name to
>> work in real multithreading.
>>
>> - The macro lookup_cpus_ll_addr now uses directly the
>> env-&g
On Fri, Jul 17, 2015 at 5:27 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> Update the TCG LL/SC instructions to work in multi-threading.
>>
>> The basic idea remains untouched, but the whole mechanism is improved to
>> make use of the callback support to
On Fri, Jul 17, 2015 at 3:45 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> When a vCPU is about to set a memory page as exclusive, it needs to wait
>> that all the running vCPUs finish to execute the current TB and to be aware
>> of the exact moment when th
On Fri, Jul 17, 2015 at 2:56 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
>> qemu_stcond. For the time being only 32bit configurations are supported.
>>
>> Suggested-by: Jani Kokk
On Fri, Jul 17, 2015 at 2:51 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
>> qemu_stcond. For the time being only the 32bit instructions are supported.
>>
>> Suggested-by: J
You are right. I will fix this case as in gen_ldst_i32().
Thanks,
alvise
On Fri, Jul 17, 2015 at 11:49 AM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> Create a new pair of instructions that implement a LoadLink/StoreConditional
>> mechanism.
>>
>> It ha
On Thu, Jul 16, 2015 at 4:53 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
>> The new helpers rely on the legacy ones to perform the actual read/write.
>>
>> The StoreConditional helper (helper_le_stcond_name) returns 1 if the
>> store has to fail due to a c
On Thu, Jul 16, 2015 at 4:32 PM, Alex Bennée wrote:
>
>
> Alvise Rigo writes:
>
> > Add a new flag for the TLB entries to force all the accesses made to a
> > page to follow the slow-path.
> >
> > In the case we remove a TLB entry marked as EXCL, we unset th
On Fri, Jul 10, 2015 at 11:53 AM, Frederic Konrad
wrote:
> On 10/07/2015 11:47, alvise rigo wrote:
>>
>> I tried to use it, but it would then create a deadlock at a very early
>> stage of the stress test.
>> The problem is likely related to the fact that flush_queu
,
alvise
On Fri, Jul 10, 2015 at 11:36 AM, Paolo Bonzini wrote:
>
>
> On 10/07/2015 10:23, Alvise Rigo wrote:
>> In order to perfom "lazy" TLB invalidation requests, introduce a
>> queue of callbacks at every vCPU disposal that will be fired just
>> before ent
On Fri, Jul 10, 2015 at 10:39 AM, Frederic Konrad
wrote:
> On 10/07/2015 10:23, Alvise Rigo wrote:
>>
>> This is the third iteration of the patch series; starting from PATCH 007
>> there are the changes to move the whole work to multi-threading.
>> Changes versus p
core, are you saying that a typical
> boot is slower?
Slower than what?
Regards,
alvise
>
> Cheers
>
> Mark.
>
>> On 10 Jul 2015, at 10:23, Alvise Rigo wrote:
>>
>> * Performance considerations
>> This implementation shows good results while booti
d-off-by: Alvise Rigo
---
softmmu_template.h | 110 +++--
1 file changed, 89 insertions(+), 21 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index bc767f6..522454f 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -141,21
ldlink operation.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cpus.c| 5 +
exec.c| 45 +
include/qom/cpu.h | 16
3 files changed, 66 insertions(+)
diff --git a
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only the 32bit instructions are supported.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/translate.c
: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/tcg-be-ldst.h | 1 +
tcg/tcg-op.c | 23 +++
tcg/tcg-op.h | 3 +++
tcg/tcg-opc.h | 4
tcg/tcg.c | 2 ++
tcg/tcg.h | 18 ++
6 files changed, 43
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
include/exec/ram_addr.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 2766541..e51bd65 100644
--- a/include/exec
to EXCL of the page
- all the vCPUs will have the EXCL flag in the TLB entry for that
specific page *before* entering the next TB
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 2 +
include/exec/cpu-defs.h | 4
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only 32bit configurations are supported.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/i386/tcg-target.c
. Most of all, the
mutex is used to protect the env->exclusive_protected_hwaddr (one
mutex for all vCPUs).
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c | 4
1 file changed, 4 insertions(+)
diff --git a/cputlb.c b/cputlb.c
in
Richard Henderson to improve the logic in
softmmu_template.h and to simplify the methods generation through
softmmu_llsc_template.h
- Added initial implementation of qemu_{ldlink,stcond}_i32 for tcg/i386
This work has been sponsored by Huawei Technologies Duesseldorf GmbH.
Alvise Rigo (
Add a new way to query a TLB flush request for a given vCPU using the
new callback support.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c | 6 ++
include/qom/cpu.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/cputlb.c b
rily pause
the execution of the other vCPUs in order to update accordingly (flush)
the TLB cache.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 3 +
softmmu_llsc_templa
In order to perfom "lazy" TLB invalidation requests, introduce a
queue of callbacks at every vCPU disposal that will be fired just
before entering the next TB.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cpus.c
vCPU writes to the protected address.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 18 -
include/exec/cpu-all.h | 2 +
include/exec/cpu-defs.h | 4 +
softmmu_template.h | 189
have to
be so in a real multi-threading TCG.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
include/exec/memory.h | 3 ++-
include/exec/ram_addr.h | 22 ++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/include/exec
Hi Alex,
Let me just add one comment.
On Fri, Jun 12, 2015 at 6:37 PM, Alex Bennée wrote:
> Hi,
>
> One thing that Peter has been asking for is a design document for the
> way we are going to approach multi-threaded TCG emulation. I started
> with the information that was captured on the wiki an
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only 32bit configurations are supported.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/i386/tcg-target.c
Implement strex and ldrex instruction relying on TCG's qemu_ldlink and
qemu_stcond. For the time being only the 32bit instructions are supported.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
target-arm/translate.c
: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
tcg/tcg-be-ldst.h | 1 +
tcg/tcg-op.c | 23 +++
tcg/tcg-op.h | 3 +++
tcg/tcg-opc.h | 4
tcg/tcg.c | 2 ++
tcg/tcg.h | 18 ++
6 files changed, 43
vCPU writes to the protected address.
Suggested-by: Jani Kokkonen
Suggested-by: Claudio Fontana
Signed-off-by: Alvise Rigo
---
cputlb.c| 18 -
include/exec/cpu-all.h | 2 +
include/exec/cpu-defs.h | 4 ++
softmmu_template.h | 187
101 - 200 of 298 matches
Mail list logo
