On 2019/9/11 下午10:51, Chih-Min Chao wrote:
On Wed, Sep 11, 2019 at 2:35 PM liuzhiwei <mailto:zhiwei_...@c-sky.com>> wrote:
From: LIU Zhiwei mailto:zhiwei_...@c-sky.com>>
Signed-off-by: LIU Zhiwei mailto:zhiwei_...@c-sky.com>>
---
ta
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 37 +
target/riscv/insn_trans/trans_rvv.inc.c | 37 +
target/riscv/vector_helper.c| 3388 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvv.inc.c | 27 ++
target/riscv/vector_helper.c| 635
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 41 +
target/riscv/insn32.decode | 41 +
target/riscv/insn_trans/trans_rvv.inc.c | 41 +
target/riscv/vector_helper.c| 2838 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvv.inc.c | 17 +
target/riscv/vector_helper.c| 1275 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 29 +
target/riscv/insn32.decode | 29 +
target/riscv/insn_trans/trans_rvv.inc.c | 29 +
target/riscv/vector_helper.c| 2280 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 37 +
target/riscv/insn_trans/trans_rvv.inc.c | 37 +
target/riscv/vector_helper.c| 2645 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 40 +
target/riscv/insn32.decode | 40 +
target/riscv/insn_trans/trans_rvv.inc.c | 54 +
target/riscv/vector_helper.c| 2962 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 36 +
target/riscv/insn32.decode | 35 +
target/riscv/insn_trans/trans_rvv.inc.c | 49 +
target/riscv/vector_helper.c| 2335 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25 +
target/riscv/insn32.decode | 25 +
target/riscv/insn_trans/trans_rvv.inc.c | 25 +
target/riscv/vector_helper.c| 1477 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
linux-user/riscv/cpu_loop.c | 7 +
target/riscv/cpu_helper.c | 7 +
target/riscv/helper.h | 7 +
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 +
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 15 +
target/riscv/insn32.decode | 16 +
target/riscv/insn_trans/trans_rvv.inc.c | 15 +
target/riscv/vector_helper.c| 1068 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 46 +
target/riscv/insn_trans/trans_rvv.inc.c | 70 +
target/riscv/vector_helper.c| 2638 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/Makefile.objs | 2 +-
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 46
target/riscv/translate.c
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15
target/riscv/csr.c | 65 ++---
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 18 +
target/riscv/insn32.decode | 21 +
target/riscv/insn_trans/trans_rvv.inc.c | 36 +
target/riscv/vector_helper.c| 1467 +++
4 files changed,
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 2 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd..9f93ce7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 28
1 file changed, 28 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307..c992b1d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -93,9 +93,37 @@ typedef
Features:
* support specification
riscv-v-spec-0.7.1(https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf).
* support basic vector extension.
* support Zvlsseg.
On 2019/8/29 上午2:54, Richard Henderson wrote:
On 8/27/19 7:36 PM, liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
linux-user/riscv
On 2019/8/29 下午10:06, Chih-Min Chao wrote:
Hi Liuzhiwei,
Some comments:
1. vector extension allows flexible implementation. It is better
to describe the limitation of current implementation (such as
vlen/elen/slen) , supported sections and unsupported features.
Thanks! All mentioned
On 2019/8/29 下午11:09, Richard Henderson wrote:
On 8/29/19 5:45 AM, liuzhiwei wrote:
Even in qemu, it may be some situations that VSTART != 0. For example, a load
instruction leads to a page fault exception in a middle position. If VSTART ==
0, some elements that had been loaded before
On 2019/8/29 下午11:14, Richard Henderson wrote:
On 8/29/19 5:00 AM, liuzhiwei wrote:
Maybe there is some better test method or some forced test cases in QEMU. Could
you give me some advice for testing?
If you have hardware, or another simulator, RISU is very good
for testing these sorts
On 2019/8/30 上午5:50, Alistair Francis wrote:
On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote:
On 2019/8/29 上午5:34, Alistair Francis wrote:
On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu
Hi, Alex
On 2019/8/28 下午5:08, Alex Bennée wrote:
liuzhiwei writes:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
Changes to softfloat should
On 2019/8/29 上午4:43, Richard Henderson wrote:
On 8/28/19 11:54 AM, Richard Henderson wrote:
But it might be reasonable to include (VSTART == 0 && VL == VLMAX) as a
single bit.
BTW, it is reasonable to check VSTART == 0 always. Quoting the spec:
# Implementations are permitted to raise
On 2019/8/29 上午5:34, Alistair Francis wrote:
On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
linux-user
On 2019/8/22 上午3:31, Palmer Dabbelt wrote:
On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell
wrote:
On Thu, 15 Aug 2019 at 09:53, Aleksandar Markovic
wrote:
>
> > We can accept draft
> > extensions in QEMU as long as they
On 2019/8/20 上午12:38, Chih-Min Chao wrote:
On Mon, Aug 19, 2019 at 9:47 PM liuzhiwei <mailto:zhiwei_...@c-sky.com>> wrote:
On 2019/8/17 上午1:29, Alistair Francis wrote:
> On Thu, Aug 15, 2019 at 8:39 PM liuzhiweimailto:zhiwei_...@c-sky.com>> wrote:
On 2019/8/20 上午2:56, Alistair Francis wrote:
On Mon, Aug 19, 2019 at 6:44 AM liuzhiwei wrote:
On 2019/8/17 上午1:29, Alistair Francis wrote:
On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei wrote:
Hi, Palmer
When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail
list
On 2019/8/17 上午1:29, Alistair Francis wrote:
On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei wrote:
Hi, Palmer
When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail
list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 o
Hi, Palmer
When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail
list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
included even in QEMU 4.1.0.
As we have cpus using CLIC, I have to use
Hi all,
My workmate and I have been working on Vector & Dsp extension, and
I'd like to share develop status with folks.
The spec references for Vector extension is riscv-v-spec-0.7.1, and
riscv-p-spec-0.5 for DSP extension. The code of vector extension is
ready and under testing,
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