Hello,
I keep seeing these warnings on the latest master with GCC 9.3:
/home/pranith/qemu/hw/block/pflash_cfi01.c: In function
‘pflash_mem_read_with_attrs’:
/home/pranith/qemu/hw/block/pflash_cfi01.c:667:20: note: parameter passing
for argument of type ‘MemTxAttrs’ {aka ‘struct MemTxAttrs
to
> > generate callbacks.
>
> Well we have that now. At each TB generation event the callback is free to
> register
> as many or few callbacks as it likes dynamically.
But how does the plugin know that the TB being generated is the first
TB in the ROI?
Similarly the plugin needs to know the then end of ROI has been reached.
Also, please note that there can be multiple ROIs. It would be good to
know if we can assign ids to each ROI for the plugin.
Thanks,
--
Pranith
k
once it got the necessary callbacks.
* State saving API
An API to save the state of the VM from the plugin code.
Let me know your thoughts and any other ideas you might have.
Thanks,
--
Pranith
t id, unsigned int
> vcpu_idx,
> + int64_t num, int64_t ret);
> +
> +void
> +qemu_plugin_register_vcpu_syscall_ret_cb(qemu_plugin_id_t id,
> + qemu_plugin_vcpu_syscall_ret_cb_t
> cb);
> +
> +
> +/**
> + * qemu_plugin_vcpu_for_each() - iterate over the existing vCPU
> + * @id: plugin ID
> + * @cb: callback function
> + *
> + * The @cb function is called once for each existing vCPU.
> + *
> + * See also: qemu_plugin_register_vcpu_init_cb()
> + */
> +void qemu_plugin_vcpu_for_each(qemu_plugin_id_t id,
> + qemu_plugin_vcpu_simple_cb_t cb);
> +
> +void qemu_plugin_register_flush_cb(qemu_plugin_id_t id,
> + qemu_plugin_simple_cb_t cb);
> +
> +void qemu_plugin_register_atexit_cb(qemu_plugin_id_t id,
> +qemu_plugin_udata_cb_t cb, void
> *userdata);
> +
> +/* returns -1 in user-mode */
> +int qemu_plugin_n_vcpus(void);
> +
> +/* returns -1 in user-mode */
> +int qemu_plugin_n_max_vcpus(void);
> +
> +#endif /* QEMU_PLUGIN_API_H */
> --
> 2.20.1
>
>
--
Pranith
Minor nits.
On Fri, Jun 14, 2019 at 11:41 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> ---
> bsd-user/syscall.c | 9 +
> linux-user/syscall.c | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
Hi,
On Fri, Jun 14, 2019 at 10:21 AM Alex Bennée wrote:
>
> This is mostly extracted from Emilio's more verbose commit comments
> with some additional verbiage from me.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/index.rst | 1 +
> docs/devel/plugins.rst | 99
ault
~/quickht$ ./bench -t 2 -u 2
Comparisons: 23922
Buckets touched: 4933
Operations: 2000
--
Pranith
On second looks, running the benchmark on a RISCV processor is also
giving a seg fault. So may be there is something wrong with the
benchmark... OTOH, x86 version runs fine... hmm
Please ignore this report, I will try to investigate further.
Thanks,
On Mon, Sep 3, 2018 at 12:45 AM Pranith Kumar
Hi Michael,
qemu-riscv64 seg faults for me on a static binary. You can build the
binary from here: https://github.com/pranith/quickht
$ STATIC=1 RISCV=1 make
$ qemu-riscv64 ./bench -t 1 -u 1
Thanks,
--
Pranith
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1785734
Title:
movdqu partial write at page boundary
Status in QEMU:
Confirmed
Bug
Hi Alex,
On Tue, Sep 5, 2017 at 8:02 AM, Alex Bennée <alex.ben...@linaro.org> wrote:
>
> Pranith Kumar <bobby.pr...@gmail.com> writes:
>
>> Update the comment which is not true since MTTCG.
>
> What happened to the cover letter? We seem to have a mix of patche
On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson <r...@twiddle.net> wrote:
> On 08/29/2017 10:23 AM, Pranith Kumar wrote:
>> This patch increases the number of entries cached in the TLB. I went
>> over a few architectures to see if increasing it is problematic. Only
&
CC'ing stable for 2.10.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only applied to the left hand side of this bitwise oper
On Tue, Aug 29, 2017 at 5:16 PM, Emilio G. Cota <c...@braap.org> wrote:
> On Sun, Aug 27, 2017 at 18:15:50 -0400, Pranith Kumar wrote:
>> Hi Emilio,
>>
>> On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota <c...@braap.org> wrote:
>> > This will enable us t
I should have worded the subject better. The warning is pointing to an
actual bug.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only a
Fix the following warning:
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only
applied to the left hand side of this bitwise operator
[-Wlogical-not-parentheses]
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^ ~
/home/
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
On Tue, Aug 29, 2017 at 11:01 AM, Richard Henderson
<richard.hender...@linaro.org> wrote:
> On 08/28/2017 11:33 PM, Pranith Kumar wrote:
>> + * TODO: rewrite this comment
>> */
>> -#define CPU_TLB_BITS
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/ia64/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/s390/tcg-target.h| 2 ++
tcg/sparc/tcg-target.h | 2 ++
7
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/tcg-op.c | 16
1 file changed, 16 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 87f673ef49..688d91755b 100644
--- a/t
Update the comment which is not true since MTTCG.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/tra
error margins, however I think
the
patch is still worth. We can also explore atomics instead of taking a lock for
the work item pool.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
cpus-common.c | 75 +++
1 file changed, 60 inse
On Mon, Aug 28, 2017 at 3:05 PM, Emilio G. Cota <c...@braap.org> wrote:
> On Sun, Aug 27, 2017 at 23:53:25 -0400, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
&
On Mon, Aug 28, 2017 at 1:47 PM, Richard Henderson
<richard.hender...@linaro.org> wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
&
On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson <r...@twiddle.net> wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
>> index 55a46ac825..b41a248bee 100644
>> --- a/tcg/aarch64/tcg-target.h
>&g
Update the comment which is not true since MTTCG.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a/
oot+shutdown test).
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
cpus-common.c | 85 ---
1 file changed, 70 insertions(+), 15 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index 59f751ecf9..a1c4c7d1a3 100644
-
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/tc
Hi Emilio,
On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota wrote:
> This will enable us to decouple code translation from the value
> of parallel_cpus at any given time. It will also help us minimize
> TB flushes when generating code via EXCP_ATOMIC.
>
> Note that the declaration
On Thu, Aug 24, 2017 at 11:58 AM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
> This patch increases the number of entries cached in the TLB. I went
> over a few architectures to see if increasing it is problematic. Only
> armv6 seems to have a limitation that only 8 b
(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar <bobby
On Mon, Aug 7, 2017 at 7:07 AM, Eric Blake <ebl...@redhat.com> wrote:
> On 08/05/2017 01:52 PM, Pranith Kumar wrote:
>> FYI,
>>
>> This commit breaks the build with gcc-7:
>>
>> CC block/vvfat.o
>> qemu/block/vvfat.c: In function ‘read_di
> -}
> -
> -/* increment number */
> -for(j=7;j>0 && entry->name[j]=='9';j--)
> -entry->name[j]='0';
> -if(j>0) {
> -if(entry->name[j]<'0' || entry->name[j]>'9')
> -entry->name[j]='0';
> -else
> -entry->name[j]++;
> -}
> -}
> +entry = create_short_filename(s, filename, directory_start);
>
> /* calculate checksum; propagate to long name */
> if(entry_long) {
> --
> 2.11.0
>
>
--
Pranith
to a 4K-sized cache.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
include/exec/cpu-defs.h | 5 -
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 1 +
tcg/s390/tcg-target.h| 1 +
tcg/sparc/tcg-target.h | 1 +
6 files chang
On Wed, Jul 12, 2017 at 7:08 PM, Richard Henderson <r...@twiddle.net> wrote:
> On 07/12/2017 12:14 PM, Pranith Kumar wrote:
>>
>> Use ADR instruction for shorter jumps.
>>
>> I was going through rth's email and realized that I should have done
>> this the f
Use ADR instruction for shorter jumps.
I was going through rth's email and realized that I should have done
this the first time.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff
onz...@redhat.com>
CC: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
hw/i386/kvmvapic.c | 101 +--
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell <peter.mayd...@linaro.org>
CC: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match
register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0"
;alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
accel/tcg/translate-all.c| 2 +-
tcg/aarch64/tcg-target.inc.c | 36 ++--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/t
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 15 +
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Pranith Kum
On Fri, Jun 30, 2017 at 12:47 AM, Richard Henderson <r...@twiddle.net> wrote:
> On 06/29/2017 05:40 PM, Pranith Kumar wrote:
>>
>> void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
>> {
>> tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_ad
;alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
accel/tcg/translate-all.c| 2 +-
tcg/aarch64/tcg-target.inc.c | 34 +-
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/t
to remove
the code buffer size limitation altogether. However, I feel that 3GB
should be sufficient for now and hence did not change it ;). It
however enables the !USE_DIRECT_JUMP path on aarch64 hosts.
Thanks,
v3:
* Update with comments and reviews by Richard
Pranith Kumar (3):
tcg/aarch64
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Pranith Kum
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 15 +
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Richard Henderson <r...@twiddle.net>
CC: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 15 +--
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Richard Henderson <r...@twiddle.net>
CC: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.
;alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
accel/tcg/translate-all.c| 2 +-
tcg/aarch64/tcg-target.inc.c | 26 +-
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/tra
to remove
the code buffer size limitation altogether. However, I feel that 3GB
should be sufficient for now and hence did not change it ;). It
however enables the !USE_DIRECT_JUMP path on aarch64 hosts.
Thanks,
Pranith Kumar (3):
tcg/aarch64: Introduce and use long branch to register
tcg/aarch64
onz...@redhat.com>
CC: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
hw/i386/kvmvapic.c | 73 +++-
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell <peter.mayd...@linaro.org>
CC: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.
Hello,
Please find these two pending MTTCG fixes I have in my repo.
I've reworked the async_safe_* patch according to pbonzini's suggestion.
Thanks,
Pranith Kumar (2):
Revert "exec.c: Fix breakpoint invalidation race"
mttcg/i386: Patch instruction using async_safe_* framewor
I used the following patch to collect hit/miss TLB ratios for a few
benchmarks. The results can be found here: http://imgur.com/a/gee1o
Please note that these results also include boot/shutdown as the
per-region instrumentation patch came later.
Signed-off-by: Pranith Kumar <bobby
asm volatile ("msr pmuserenr_el0, %0" :: "r" (0xfa11dead));
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/arm/helper.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
The following two patches are what I use to instrument guest code and
collect TLB hit/miss information. These patches are for informational
and discussion purposes only.
Pranith Kumar (2):
[TEST] aarch64: Use pmuserenr_el0 register for instrumentation
[TEST] Collect TLB stats along
figured out! I tested it on the images I have
and it works. Please add:
Tested-by: Pranith Kumar <bobby.pr...@gmail.com>
>
> diff --git a/tcg-runtime.c b/tcg-runtime.c
> index 7fa90ce508..f4bfa9cea6 100644
> --- a/tcg-runtime.c
> +++ b/tcg-runtime.c
> @@ -147,30 +147,33 @@ u
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 1fa3bccc89..ab0a8caa03 100644
--- a/tcg/aarch64/tcg-target
Hi,
The following patches apply on top of tcg-next of rth's branch. These
patches make use of LDR (literal) on aarch64 and enable us to remove
the 128MB code buffer size limitation.
Pranith Kumar (3):
tcg/aarch64: Introduce and use jump to register
tcg/aarch64: Introdue LDR (literal
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
tcg/aarch64/tcg-target.inc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index ab0a8caa03..e488aacadb 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch
This enables indirect jump on aarch64 hosts. Tested by booting an x86 guest on
aarch64 host.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
include/exec/exec-all.h | 6 +-
tcg/aarch64/tcg-target.inc.c | 25 ++---
translate-all.c | 2
onz...@redhat.com>
CC: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
hw/i386/kvmvapic.c | 82 ++--
On Wed, Jun 7, 2017 at 2:09 PM, Alex Bennée <alex.ben...@linaro.org> wrote:
>
> Pranith Kumar <bobby.pr...@gmail.com> writes:
>
>> Can someone please pick this up?
>
> It needs to be re-posted with the review tag and ping Paolo re: async
> work for KVM.
>
Will do.
Thanks,
--
Pranith
Now that we have proper locking after MTTCG patches have landed, we
can revert the commit. This reverts commit
a9353fe897ca2687e5b3385ed39e3db3927a90e0.
CC: Peter Maydell <peter.mayd...@linaro.org>
CC: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Pranith Kumar <bobby.
Can someone please pick this up?
Thanks,
On Fri, Feb 24, 2017 at 12:42 AM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
> In mttcg, calling pause_all_vcpus() during execution from the
> generated TBs causes a deadlock if some vCPU is waiting for exclusive
> execution in start_e
ed-by: Richard Henderson <r...@twiddle.net>
> Suggested-by: Geert Martin Ijewski <gm.ijew...@web.de>
> Tested-by:Geert Martin Ijewski <gm.ijew...@web.de>
> Signed-off-by: Emilio G. Cota <c...@braap.org>
> ---
Reviewed-by: Pranith Kumar <bobby.pr...@gmail.com>
--
Pranith
On Mon, Jun 5, 2017 at 6:49 PM, Emilio G. Cota <c...@braap.org> wrote:
> Signed-off-by: Emilio G. Cota <c...@braap.org>
Reviewed-by: Pranith Kumar <bobby.pr...@gmail.com>
> ---
> tests/atomic_add-bench.c | 4 ++--
> tests/qht-bench.c| 2 +-
> 2
;);
> +if (fp == NULL) {
> +return -1;
> +}
> +if (!fscanf(fp, "%u", )) {
> +return -1;
> + }
> +return size;
> +}
> +#else
> +#error Cannot find host cache line size
> +#endif
> +EOF
Is there any reason not to use sysconf(_SC_LEVEL1_DCACHE_LINESIZE)?
Thanks,
--
Pranith
/2017-03/msg05172.html
> Subject: Re: GSoC 2017 Proposal: TCG performance enhancements
> Message-ID: <1e67644b-4b30-887e-d329-1848e94c9...@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.pr...@gmail.com>
Thanks for doing this Emilio. Do you plan to continue working on rth's
suggestions in that email? If so, can we co-ordinate our work?
--
Pranith
choices=['time', 'latency'],
> default='time')
What does latency here indicate? I tried this argument on a sample
trace file I generated, and it had three empty boxes.
> +parser.add_argument("events", type=str, help='trace file read from')
> +parser.add_argument("tracefile", type=str, help='trace file read from')
The help text for 'events' file here should be something like 'the
trace events file'.
Thanks,
--
Pranith
quot;
is converted to "lock; multi-byte nop; " due to code
alignment.
There were bugs reported regarding this:
https://bugs.chromium.org/p/nativeclient/issues/detail?id=3929
I am not sure we want to fix this, but I thought it would be easy
enough to cover this case.
Thanks,
--
Pranith
The instruction "lock nopl (%rax)" should raise an exception. However,
we don't do that since we do not check for lock prefix for nop
instructions. The following patch adds this check and makes the
behavior similar to hardware.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/1653384
Title:
Assertion failed with USB pass through with XHCI controller
Status in
emove -nodefaults is a sign that with it
> your single cpu may just not be getting scheduled again. Does the patch
> from Alex Bennée here[*] help?
>
> [*] https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg01743.html
>
This bug is still reproducible with the latest git.
--
Pranith
--
Pranith
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1653063
Title:
qemu-system-arm hangs with -icount and -nodefaults
Status in QEMU:
Confirmed
On Wed, Apr 19, 2017 at 10:26 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
> On Wed, Apr 19, 2017 at 06:03:01PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 5:33 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
>> > On Wed, Apr 19, 2017 at 05:25:2
On Wed, Apr 19, 2017 at 5:33 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
> On Wed, Apr 19, 2017 at 05:25:23PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 4:57 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
>> > On Wed, Apr 19, 2017 at 04:16:5
On Wed, Apr 19, 2017 at 4:57 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
> On Wed, Apr 19, 2017 at 04:16:53PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 4:13 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
>> > On Wed, Apr 19, 2017 at 04:00:4
On Wed, Apr 19, 2017 at 4:13 PM, Eduardo Habkost <ehabk...@redhat.com> wrote:
> On Wed, Apr 19, 2017 at 04:00:49PM -0400, Pranith Kumar wrote:
>> On Wed, Apr 19, 2017 at 3:54 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
>> > When we enable hyperthreading (using
On Wed, Apr 19, 2017 at 3:54 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
> When we enable hyperthreading (using threads smp argument), we warn
> the user if the cpu is an AMD cpu. This does not make sense on TCG and
> is also obsolete now that AMD Ryzen support hyperthr
.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/i386/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 13c0985f11..f34bb5ead7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -202,12 +
.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/i386/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 13c0985f11..f34bb5ead7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -202,12 +
** Changed in: qemu
Status: Incomplete => Confirmed
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https://bugs.launchpad.net/bugs/1681688
Title:
qemu live migration failed
Status in QEMU:
Confirmed
Bug description:
** Changed in: qemu
Status: New => Invalid
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https://bugs.launchpad.net/bugs/1682093
Title:
aarch64-softmmu "bad ram pointer" crash
Status in QEMU:
Invalid
Bug description:
** Changed in: qemu
Status: New => Incomplete
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https://bugs.launchpad.net/bugs/1681688
Title:
qemu live migration failed
Status in QEMU:
Incomplete
Bug description:
qemu
On Tue, Apr 18, 2017 at 5:56 AM, Paolo Bonzini <pbonz...@redhat.com> wrote:
>
>
> On 17/04/2017 20:55, Pranith Kumar wrote:
>>>> +/* ARM does not have a user-space readble cycle counter available.
>>>> + * This is a compromise to get monotonically increas
Tested and confirmed that the stretch i386 debian qcow2 image on a
raspberry pi 2 works.
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
include/qemu/timer.h | 5 ++---
1 file changed, 2 insertions(+),
On Mon, Apr 17, 2017 at 2:42 PM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 15 April 2017 at 20:29, Pranith Kumar <bobby.pr...@gmail.com> wrote:
>> Tested and confirmed that the stretch i386 debian qcow2 image on a
>> raspberry pi 2 works.
>
Tested and confirmed that the stretch i386 debian qcow2 image on a
raspberry pi 2 works.
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
include/qemu/timer.h | 10 ++
1 file changed, 10 insertions(+)
dc, as
Can you retry with the latest rc? There were some fixes regarding rr since rc0.
Thanks,
--
Pranith
TCG uses the AMD cpu which warns when we use hyperthreading. Disable
the warning for TCG since it is not necessary.
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386
On Mon, Mar 27, 2017 at 11:03 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote:
>
> If you think the project makes sense, I will add it to the GSoC wiki
> so that others can also apply for it. Please let me know if you are
> interested in mentoring it along with Alex.
>
One
Hi Paolo,
On Mon, Mar 27, 2017 at 7:32 AM, Paolo Bonzini <pbonz...@redhat.com> wrote:
>
>
> On 25/03/2017 17:52, Pranith Kumar wrote:
>> * Implement an LRU translation block code cache.
>>
>> In the current TCG design, when the translation cache fills up, we
he TB and the code, then we get exactly the right number
> of TBs allocated with no further effort.
>
> There will be some additional memory wastage, since we'll want to keep the
> code and the data in different cache lines and that means padding, but I
> don't think that'll be significant. Indeed, given the above over-allocation
> will probably still be a net savings.
>
If you think the project makes sense, I will add it to the GSoC wiki
so that others can also apply for it. Please let me know if you are
interested in mentoring it along with Alex.
Thanks,
--
Pranith
Hi Stefan,
On Mon, Mar 27, 2017 at 11:54 AM, Stefan Hajnoczi <stefa...@gmail.com> wrote:
> On Sat, Mar 25, 2017 at 12:52:35PM -0400, Pranith Kumar wrote:
>> Alex Bennée, who mentored me last year, has agreed to mentor me again this
>> time if the proposal is accepted.
>
&g
that are easily implementable to increase
TCG performance as part of this project or otherwise.
Thanks,
--
Pranith
eter.mayd...@linaro.org>
CC: Paolo Bonzini <pbonz...@redhat.com>
Reported-by: Jann Horn <ja...@google.com>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/translate.c b
<paolo.bonz...@redhat.com>
Reported-by: Jann Horn <ja...@google.com>
Signed-off-by: Pranith Kumar <bobby.pr...@gmail.com>
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 72c1b03a2a..1d137
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