From: Marc-André Lureau
I didn't remove it, as suggest by checkpatch, because it looks like it
may eventually be restored back.
Signed-off-by: Marc-André Lureau
Signed-off-by: Pranith Kumar
---
tests/tcg/linux-test.c | 8 ++--
tests/tcg/test-i386-fprem.c | 4
2 files ch
Enable tcg lock debug asserts in a debug build by default instead of
relying on DEBUG_LOCKING. None of the other DEBUG_* macros have
asserts, so this patch removes DEBUG_LOCKING and enable these asserts
in a debug build.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
On Wed, Nov 16, 2016 at 10:57 AM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> Unconditionally enable locking checks in debug builds so that we get
>> wider testing. Using tcg_debug_assert() allows us to remove
>> DEBUG_LOCKING define.
>
> Interesting. T
Unconditionally enable locking checks in debug builds so that we get
wider testing. Using tcg_debug_assert() allows us to remove
DEBUG_LOCKING define.
Signed-off-by: Pranith Kumar
---
translate-all.c | 50 +-
1 file changed, 17 insertions(+), 33
On Tue, Nov 15, 2016 at 2:48 AM, Richard Henderson wrote:
> On 11/15/2016 06:41 AM, Pranith Kumar wrote:
>>
>> Move the asserts in tb_lock/unlock() to DEBUG_LOCKING to avoid the
>> assert checking overhead in normal builds.
>
>
> I know DEBUG_LOCKING already exists i
Hi Alex,
This patch is causing some build errors on a 32-bit box:
In file included from /home/pranith/qemu/include/exec/exec-all.h:44:0,
from /home/pranith/qemu/cputlb.c:23:
/home/pranith/qemu/cputlb.c: In function ‘tlb_flush_page_by_mmuidx_async_work’:
/home/pranith/qemu
Hi Alex,
I have a merged branch with these changes but it needs more work. I
will post the next version soon(for some definition of soon :)
You can find the in-progress branch here:
https://github.com/pranith/qemu tcg_test_cleanup_v4
Thanks,
On Thu, Nov 3, 2016 at 9:35 AM, Alex Bennée wrote
The patch enables handling atomic code in the guest. This should be
preferably done in cpu_handle_exception(), but the current assumptions
regarding when we can execute atomic sections cause a deadlock.
Signed-off-by: Pranith Kumar
---
cpus.c | 9 +
1 file changed, 9 insertions
Alex Bennée writes:
> Pranith Kumar writes:
>
>> The patch enables handling atomic code in the guest. This should be
>> preferably done in cpu_handle_exception(), but the current assumptions
>> regarding when we can execute atomic sections cause a deadlock.
>>
&
The patch enables handling atomic code in the guest. This should be
preferably done in cpu_handle_exception(), but the current assumptions
regarding when we can execute atomic sections cause a deadlock.
Signed-off-by: Pranith Kumar
---
cpus.c | 7 +++
1 file changed, 7 insertions(+)
diff
Use __atomic_load_n() primitive saving a load and store to a local
variable.
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 878fa07..be44094
On Tue, Nov 1, 2016 at 10:44 AM, Paolo Bonzini wrote:
>
> Can you do the same for atomic_rcu_read__nocheck (both implementations)?
>
Sure, will send an updated patch.
--
Pranith
We can use __atomic_load_n() saving a store and load from the _val.
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 878fa07..6775603 100644
--- a/include/qemu
be something new in the
tree tripped this?
--
Pranith
a
> + * mmuidx bit mask we need to fail to build if we can't do that
> + */
> +QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS);
> +
FYI, this is causing a build error on my system with gcc 6.2.
CC aarch64-softmmu/cputlb.o
In file included from /home/pranith/devops/c
gested.
0 4
10 9.70
20 8.09
30 7.13
40 6.49
I am not sure why only 100% reader case is so low. Applying the
sequence lock cache alignment patch brings it back up to 13
MT/s/thread.
--
Pranith
Paolo Bonzini writes:
> On 25/10/2016 17:49, Pranith Kumar wrote:
>> But we are taking the seqlock of only the head bucket, while the
>> readers are reading hashes/pointers of the chained buckets.
>
> No, we aren't. See qht_lookup__slowpath.
I don't see it
On Tue, Oct 25, 2016 at 11:41 AM, Paolo Bonzini wrote:
>
>
> On 25/10/2016 17:35, Pranith Kumar wrote:
>> Using perf, I see that sequence lock is being a bottleneck since it is
>> being read by everyone. Giving it its own cache-line seems to help
>> things quite a bi
8.07 13.33 +65%
10 7.10 8.90 +25%
20 6.34 7.02 +10%
30 5.48 6.11 +9.6%
40 4.90 5.46 +11.42%
I am not able to see any significant increases for lower thread counts though.
Signed-off-by: Pranith Kumar
---
include/qemu/seqlock.h | 2 +-
util/qht.c
On Thu, Oct 20, 2016 at 3:02 PM, Richard Henderson wrote:
> On 10/20/2016 11:58 AM, Pranith Kumar wrote:
>>
>> Indeed, I was looking at atomic-6 on github. atomic-7 is not there yet :)
>
>
> I've rebased atomic-6 (no -7). It should be there.
>
Am I looking at the
On Thu, Oct 20, 2016 at 2:00 PM, Richard Henderson wrote:
> On 10/20/2016 10:51 AM, Pranith Kumar wrote:
>>>
>>> Added back
>>>
>>> /* Load/Store exclusive instructions are implemented by remembering
>>>the value/address loaded, and seein
r, &_val, __ATOMIC_SEQ_CST);\
> +__atomic_load(ptr, &_val, __ATOMIC_ACQUIRE);\
> _val; \
> })
>
Is there any reason we are not using __atomic_load_n() here?
--
Pranith
tore is performed. This should be sufficient to implement
>the architecturally mandated semantics, and avoids having to monitor
>regular stores. The compare vs the remembered value is done during
>the cmpxchg operation, but we must compare the addresses manually. */
>
FYI, I do not see this in your v7 series.
--
Pranith
ipping to the offset array entry where p is the start of the array of
> void* pointers.
>
Indeed. I missed that crucial detail. I would prefer explicitly casting to
'void **' for p, since that is not the type of what is being returned by
atomic_rcu_read().
The joys of void pointer arithmetic, TIL.
--
Pranith
gcc does not warn about the wrong type since it is a void pointer
which can be cast to any type.
Signed-off-by: Pranith Kumar
---
translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/translate-all.c b/translate-all.c
index 8ca393c..c77470a 100644
--- a/translate
Signed-off-by: Pranith Kumar
---
docs/rcu.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/docs/rcu.txt b/docs/rcu.txt
index c84e7f4..c177dcb 100644
--- a/docs/rcu.txt
+++ b/docs/rcu.txt
@@ -197,7 +197,9 @@ DIFFERENCES WITH LINUX
critical section to become an updater
s/presented/prevented/
Signed-off-by: Pranith Kumar
---
docs/rcu.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/rcu.txt b/docs/rcu.txt
index a70b72c..c84e7f4 100644
--- a/docs/rcu.txt
+++ b/docs/rcu.txt
@@ -145,7 +145,7 @@ The core RCU API is small:
and
On Sun, Oct 16, 2016 at 4:47 AM, Stefan Hajnoczi wrote:
> On Thu, Jul 14, 2016 at 04:20:20PM -0400, Pranith Kumar wrote:
>> Cc: Alexander Graf
>> Signed-off-by: Pranith Kumar
>> Signed-off-by: Richard Henderson
>> ---
>> tcg/s390/tcg-target.inc.c | 11 +
Ping, looks like this patch fell through.
On Tue, Aug 2, 2016 at 10:52 AM, Pranith Kumar wrote:
> Richard agreed to make odd fixes to PPC tcg parts[1]. This patch makes
> the change.
>
> [1] https://lists.gnu.org/archive/html/qemu-ppc/2016-03/msg00657.html
>
> CC: Richard Hende
Hi Stefan,
Stefan Hajnoczi writes:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
>
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case w
,7 @@ static inline void exit(int status)
>> : "=a" (__res) : "0" (__NR_exit),"c"
>> ((long)(status)));
>> }
>>
>> -static inline int write(int fd, const char * buf, int len)
>> +static inline size_t _write(int fd, const void * buf, size_t len)
>> {
>>int status;
>>__asm__ volatile ("pushl %%ebx\n"\
>> @@ -22,6 +23,6 @@ static inline int write(int fd, const char * buf, int
>> len)
>>
>> void _start(void)
>> {
>> -write(1, "Hello World\n", 12);
>> -exit(0);
>> +_write(1, "Hello World\n", 12);
>> +_exit(0);
>> }
>>
>
> This could be a seperate patch
>
OK, will do.
--
Pranith
Hi Marc,
Marc-André Lureau writes:
> Hi Pranith
>
> On Sat, Sep 17, 2016 at 6:05 PM Pranith Kumar wrote:
>
>> Hello,
>>
>> This patch series cleans up the tcg tests in tests/tcg folder.
>>
>>
> Incidentally, I was also looking at reorganizing test
Signed-off-by: Pranith Kumar
---
tests/Makefile.include | 1 +
tests/tcg/Makefile.include | 34 ++
2 files changed, 35 insertions(+)
create mode 100644 tests/tcg/Makefile.include
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 2f11064
Signed-off-by: Pranith Kumar
---
tests/tcg/alpha/Makefile | 38 +++--
tests/tcg/arm/Makefile | 28 +-
tests/tcg/cris/Makefile | 17 +++--
tests/tcg/i386/Makefile | 23 +-
tests
Signed-off-by: Pranith Kumar
---
tests/tcg/arm/Makefile| 45 +++
tests/tcg/{ => arm}/hello-arm.c | 0
tests/tcg/{ => arm}/test-arm-iwmmxt.s | 0
3 files changed, 45 insertions(+)
create mode 100644 tests/tcg/arm/Makefile
rename tes
Signed-off-by: Pranith Kumar
---
tests/tcg/misc/Makefile | 81 +++
tests/tcg/{ => misc}/linux-test.c | 3 ++
tests/tcg/{ => misc}/sha1.c | 0
tests/tcg/{ => misc}/test-mmap.c | 0
tests/tcg/{ => misc}/test_path.c | 0
tests/t
nning the tests
in docker containers are suggested ideas to make running the tests
easier.
v3:
- Update with review feedback from Alex Bennée.
v2:
- Add tests-tcg target to invoke native tests.
Pranith Kumar (6):
tests/tcg: Move i386 tests to arch specific folder
tests/tcg: Move arm test
Signed-off-by: Pranith Kumar
---
tests/tcg/Makefile | 156
tests/tcg/i386/Makefile | 88 ++
tests/tcg/{ => i386}/hello-i386.c | 9 +-
tests/tcg/{ => i386}/pi_10.com | Bin
tests/tcg/{ =
Signed-off-by: Pranith Kumar
---
tests/tcg/{ => mips}/hello-mips.c | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename tests/tcg/{ => mips}/hello-mips.c (100%)
diff --git a/tests/tcg/hello-mips.c b/tests/tcg/mips/hello-mips.c
similarity index 100%
rename from tests/tcg/hello-
c func, void *data);
> +
> +/**
> * qemu_get_cpu:
> * @index: The CPUState@cpu_index value of the CPU to obtain.
> *
I used the following diff on top(as suggested by bonzini) to fix a deadlock I
was seeing while testing.
Fix deadlock caused by holding BQL for safe work
On Thu, Sep 8, 2016 at 7:49 PM, Pranith Kumar
wrote:
>> On 09/08/2016 10:15 AM, Richard Henderson wrote:
>> Ho hum. I think I've mucked something up here too.
>> Please ignore this pull.
>>
>
> I think I found the error. It looks like the fence optimization
ion pass.
>
>
> Ho hum. I think I've mucked something up here too.
> Please ignore this pull.
>
I think I found the error. It looks like the fence optimization patch
is causing the error.
I will reply in that patch.
--
Pranith
FYI,
The KVM Forum 2016 videos are now online on youtube. You can find them here:
https://www.youtube.com/playlist?list=PLW3ep1uCIRfzQoZ0SlniYE8nz1ZRobjH7
Thanks,
--
Pranith
Paolo Bonzini writes:
> On 02/09/2016 16:33, Pranith Kumar wrote:
>>
>> Hi Paolo,
>>
>> This is in reference to the discussion we had yesterday on IRC. I am trying
>> to
>> understand the need for smp_read_barrier_depends() and how it prevents the
// do something
}
Why do you think smp_read_barrier_depends() is necessary here? If bh was a
shared variable I would understand, but here bh is local and a regular
barrier() would make sure that we are not optimizing the initial load into bh.
A patch fixing this follows.
Thanks,
--
Pranith
** Changed in: qemu
Status: New => Invalid
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/568228
Title:
/home/qemu-0.12.3/tcg/tcg.c:1367: tcg fatal error
Status in QEMU:
Invalid
Bug descr
cently posted a patch series cleaning up tests/tcg. While doing
that I fixed the build issues I came across.
Please see: https://www.mail-archive.com/qemu-devel@nongnu.org/msg393764.html
Thanks,
--
Pranith
On Thu, Sep 1, 2016 at 7:01 AM, Paolo Bonzini wrote:
>
>
> On 01/09/2016 00:29, Pranith Kumar wrote:
>> smp_read_barrier_depends() should be used only if you are reading
>> dependent pointers which are shared.
>
> bh is shared since it is equal to ctx->first_bh
the barrier and adds a comment why storing
'bh->next' is necessary.
Signed-off-by: Pranith Kumar
---
async.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/async.c b/async.c
index 3bca9b0..6b691aa 100644
--- a/async.c
+++ b/async.c
@@ -77,8 +77,7 @@ int aio_bh_
Signed-off-by: Pranith Kumar
---
tests/Makefile.include | 1 +
tests/tcg/Makefile.include | 20
2 files changed, 21 insertions(+)
create mode 100644 tests/tcg/Makefile.include
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 14be491..141281b 100644
Signed-off-by: Pranith Kumar
---
tests/tcg/{ => mips}/hello-mips.c | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename tests/tcg/{ => mips}/hello-mips.c (100%)
diff --git a/tests/tcg/hello-mips.c b/tests/tcg/mips/hello-mips.c
similarity index 100%
rename from tests/tcg/hello-
Signed-off-by: Pranith Kumar
---
tests/tcg/arm/Makefile| 45 +++
tests/tcg/{ => arm}/hello-arm.c | 0
tests/tcg/{ => arm}/test-arm-iwmmxt.s | 0
3 files changed, 45 insertions(+)
create mode 100644 tests/tcg/arm/Makefile
rename tes
Signed-off-by: Pranith Kumar
---
tests/tcg/misc/Makefile | 75 +++
tests/tcg/{ => misc}/linux-test.c | 3 ++
tests/tcg/{ => misc}/sha1.c | 0
tests/tcg/{ => misc}/test-mmap.c | 0
tests/tcg/{ => misc}/test_path.c | 0
tests/t
s or running the tests
in docker containers are suggested ideas to make running the tests
easier.
My makefile-fu is non-existent. So suggestions on how to hook up the
tests are welcome.
Pranith Kumar (4):
tests/tcg: Move arm tests to arch specific folder
tests/tcg: Move mips test to arch sp
Use the __atomic_*_n() primitives which take the value as argument. It
is not necessary to store the value locally before calling the
primitive, hence saving us a stack store and load.
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 24
1 file changed, 8
Paolo Bonzini writes:
> On 24/08/2016 22:44, Pranith Kumar wrote:
>> Use the __atomic_*_n() primitives which take the value as argument. It
>> is not necessary to store the value locally before calling the
>> primitive, hence saving us a stack store and load.
>
> I
Remove the redundant barrier() after the fence as agreed in previous
discussion here:
https://lists.gnu.org/archive/html/qemu-devel/2016-04/msg00489.html
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include
Use the __atomic_*_n() primitives which take the value as argument. It
is not necessary to store the value locally before calling the
primitive, hence saving us a stack store and load.
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 16 +---
1 file changed, 5 insertions
This patch tries to do the Right Thing™ to test for C11 features,
which is to test __STDC_VERSION__.
Signed-off-by: Pranith Kumar
---
include/qemu/atomic.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 43b0645
weaker fence with subsequent/previous stronger fence
load-acquire/store-release fence can be combined with a full fence
without relaxing the ordering constraint.
ex: a) ld; ldaq; mb => ld; mb
b) mb; strl; st => mb; st
Signed-off-by: Pranith Kumar
---
tcg/opt
On Mon, Aug 22, 2016 at 5:34 AM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
> You have transposed the tcg/tests in your subject for this particular commit.
I messed up the subject. I will fix this and resend.
--
Pranith
On Sat, Aug 20, 2016 at 11:19 PM, Richard Henderson wrote:
> On 08/19/2016 10:00 AM, Pranith Kumar wrote:
>>
>> This RFC patch series cleans up the tcg tests in tests/tcg folder.
>>
>> The tests have bit-rotten and were not compiling or running. I fixed
>> t
Enable running the litmus tests on travis.
Signed-off-by: Pranith Kumar
---
.travis.yml | 8
1 file changed, 8 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index f30b10e..f670c71 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -97,5 +97,13 @@ matrix:
before_install
This adds the x86 store-after-load re-ordering litmus test.
Signed-off-by: Pranith Kumar
---
tests/tcg/i386/litmus/Makefile | 42 ++
tests/tcg/i386/litmus/README.txt| 22 +
tests/tcg/i386/litmus/SAL.c | 491 +++
tests/tcg/i386/litmus/affinity.c| 159
sources can be found in this
repository: https://github.com/pranith/qemu-litmus
The litmus tests will fail if you do not have the barrier emitting
patch series applied and will pass otherwise. I tested these on both
an x86 and an Aarch64 machine. These tests are currently enabled on
the trusty
Signed-off-by: Pranith Kumar
---
tests/tcg/arm/Makefile| 45 +++
tests/tcg/{ => arm}/hello-arm.c | 0
tests/tcg/{ => arm}/test-arm-iwmmxt.s | 0
3 files changed, 45 insertions(+)
create mode 100644 tests/tcg/arm/Makefile
rename tes
is to add litmus tests to each arch and have them run
using the 'make check' target to test consistency on TCG.
There are no maintainers listed for this test folder. So I am cc'ing
people who I think might be interested.
Pranith Kumar (4):
tests/tcg: Move i386 tests to arch
Signed-off-by: Pranith Kumar
---
tests/tcg/Makefile | 156
tests/tcg/i386/Makefile | 88 ++
tests/tcg/{ => i386}/hello-i386.c | 0
tests/tcg/{ => i386}/pi_10.com | Bin
tests/tcg/{ =
Signed-off-by: Pranith Kumar
---
tests/tcg/misc/Makefile | 75 +++
tests/tcg/{ => misc}/linux-test.c | 3 ++
tests/tcg/{ => misc}/sha1.c | 0
tests/tcg/{ => misc}/test-mmap.c | 0
tests/tcg/{ => misc}/test_path.c | 0
tests/t
Signed-off-by: Pranith Kumar
---
tests/tcg/{ => mips}/hello-mips.c | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename tests/tcg/{ => mips}/hello-mips.c (100%)
diff --git a/tests/tcg/hello-mips.c b/tests/tcg/mips/hello-mips.c
similarity index 100%
rename from tests/tcg/hello-
Alex Bennée writes:
> Pranith Kumar writes:
>
>> This adds the x86 store-after-load re-ordering litmus test.
>>
>> Most of the supporting files are mostly unmodified and generated by
>> the litmus tool.
>>
>> Signed-off-by: Pranith Kumar
>>
Change the flag type to 'uint8_t' to fix the implicit conversion error.
Signed-off-by: Pranith Kumar
---
fpu/softfloat-specialize.h | 2 +-
include/fpu/softfloat.h| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-sp
Hi Richard,
On Wed, Aug 10, 2016 at 6:44 AM, Richard Henderson wrote:
> On 08/10/2016 04:42 AM, Pranith Kumar wrote:
>>
>> +/* Eliminate duplicate and unnecessary fence instructions */
>> +void tcg_optimize_mb(TCGContext *s)
>> +{
>> +int oi, oi_nex
weaker fence with subsequent/previous stronger fence
load-acquire/store-release fence can be combined with a full fence
without relaxing the ordering constraint.
ex: a) ld; ldaq; mb => ld; mb
b) mb; strl; st => mb; st
Signed-off-by: Pranith Kumar
---
v2:
- Properly remov
#x27;NEON_DO4'
NEON_FN(vdest.v1, vsrc1.v1, vsrc2.v1); \
^
/mnt/devops/code/qemu/target-arm/neon_helper.c:1054:23: note: expanded from
macro 'NEON_FN'
dest = (1 << (sizeof(src1) * 8 - 1)); \
~ ~~^~~~~~~
From: Paolo Bonzini
With the latest clang, we have the following warning:
/home/pranith/devops/code/qemu/include/qemu/seqlock.h:62:21: warning:
passing 'typeof (*&sl->sequence) *' (aka 'const unsigned int *') to parameter
of type 'unsigned int *'
Clang produces the following warning. The warning is detailed here:
https://reviews.llvm.org/D15866. Fix the warning.
/home/pranith/devops/code/qemu/hw/display/qxl.c:507:5: warning: macro expansion
producing 'defined' has undefined behavior [-Wexpansion-to-defined]
^
/home/pran
n the GCC 4.0 manual).
Disable these warnings by passing in -Wno-shift-negative-value.
Cc: Peter Maydell
Cc: Markus Armbruster
Cc: Laszlo Ersek
Signed-off-by: Paolo Bonzini
[pranith: forward-port part of patch to 2.7]
Signed-off-by: Pranith Kumar
---
HACKING | 4
configure | 2 +-
2
Change the flag type to 'int' to fix the implicit conversion error.
Suggested-by: Peter Maydell
Signed-off-by: Pranith Kumar
---
fpu/softfloat-specialize.h | 2 +-
include/fpu/softfloat.h| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/fpu/softfloat-spec
On Tue, Aug 9, 2016 at 4:17 AM, Peter Maydell wrote:
> #if !defined(SPICE_SERVER_VERSION) || (SPICE_SERVER_VERSION < 0xc06)
> #define SPICE_NEEDS_SET_MM_TIME 1
> #else
> #define SPICE_NEEDS_SET_MM_TIME 0
> #endif
>
This looks better. I will fix up a patch.
--
Pranith
On Tue, Aug 9, 2016 at 12:15 PM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> I am seeing an abort when I run qemu-aarch64 on a multi-threaded ARM64
>> executable. Is this a valid use case or is multi-threading still not
>> supported?
>
> QEMU comman
Clang produces the following warning. The warning is detailed here:
https://reviews.llvm.org/D15866. Disable the warning.
/home/pranith/devops/code/qemu/hw/display/qxl.c:507:5: warning: macro expansion
producing 'defined' has undefined behavior [-Wexpansion-to-de
#10 0x556a7490 in object_property_add (obj=0x57a17600,
name=0x57b530f0 "device[7]", type=0x57b53170 "child",
get=0x556a82e1 , set=0x0,
release=0x556a8375 ,
opaque=0x57b3eb00, errp=0x77f42eb0) at
/home/pranith/devops/code/qem
ping for review!
On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar wrote:
> Hello,
>
> The following series adds fence instruction generation support to
> TCG. Based on feedback to the last series, I added the four
> combinations of orderings modeled after Sparc membar.
>
>
Hi Paolo,
On Mon, Aug 8, 2016 at 5:11 AM, Paolo Bonzini wrote:
>
>
> On 07/08/2016 03:15, Pranith Kumar wrote:
>> With latest clang you get the following warning:
>>
>> warning: shifting a negative signed value is undefined
>> [-Wshift-negative-value]
>>
With the latest clang, we have the following warning. We are not using
the const qualifier consistently in other functions. So remove it from
the only one that uses it to fix the warning.
/home/pranith/devops/code/qemu/include/qemu/seqlock.h:62:21: warning: passing
'typeof (*&sl-
Clang produces the following warning. The warning is detailed here:
https://reviews.llvm.org/D15866
/home/pranith/devops/code/qemu/hw/display/qxl.c:507:5: warning: macro expansion
producing 'defined' has undefined behavior [-Wexpansion-to-defined]
#if SPICE_NEEDS_SET_MM_TIME
^
/ho
With latest clang you get the following warning:
warning: shifting a negative signed value is undefined [-Wshift-negative-value]
Fix the warning by changing negative shift to inverse 0 shift.
Signed-off-by: Pranith Kumar
---
target-mips/translate.c | 10 +-
1 file changed, 5
Signed-off-by: Pranith Kumar
---
.travis.yml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 881ba9d..f84f800 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -33,6 +33,7 @@ addons:
- libvte-2.90-dev
- sparse
- uuid-dev
+ - gcc
This adds the x86 store-after-load re-ordering litmus test.
Most of the supporting files are mostly unmodified and generated by
the litmus tool.
Signed-off-by: Pranith Kumar
---
tests/tcg/mttcg/x86/Makefile | 42 ++
tests/tcg/mttcg/x86/README.txt| 22 +
tests/tcg/mttcg/x86/SAL.c
have been verified to pass with the fence generation patch
series. The tests will fail otherwise.
Pranith Kumar (4):
tests/tcg: Add x86 mttcg litmus test
Enable x86 mttcg litmus tests in travis CI
tests/tcg: Add mttcg ARM64 litmus tests
Enable aarch64 mttcg litmus tests in travis CI
.
Enable the store-after-load litmus test to be run on travis-CI.
Signed-off-by: Pranith Kumar
---
.travis.yml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index f30b10e..881ba9d 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -99,3 +99,6 @@ matrix
Richard agreed to make odd fixes to PPC tcg parts[1]. This patch makes
the change.
[1] https://lists.gnu.org/archive/html/qemu-ppc/2016-03/msg00657.html
CC: Richard Henderson
Signed-off-by: Pranith Kumar
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
On Sat, Jul 23, 2016 at 1:34 PM, Paolo Bonzini wrote:
>> Ping for review!
>
> Hi,
>
> we're on hard freeze so it's normal that maintainers focus on bugfixes
> at this time.
>
OK. I will wait for 2 weeks and then ping to remind.
Thanks!
--
Pranith
Ping for review!
On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar wrote:
> Hello,
>
> The following series adds fence instruction generation support to
> TCG. Based on feedback to the last series, I added the four
> combinations of orderings modeled after Sparc membar.
>
> Thi
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1605443
Title:
QEMU epoll for i386-linux-user on arm host is broken in 2.6
Status in QEMU:
Confi
Closing since it seems to be fixed in latest release.
** Changed in: qemu
Status: Incomplete => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/498035
Title:
qemu hangs on shutdo
On Wed, Jul 20, 2016 at 6:07 PM, Peter Maydell wrote:
> On 20 July 2016 at 22:33, Pranith Kumar wrote:
>> Hmm, the original README did not have an explicit new line at end of
>> file.
>
> Yes it did:
> $ git show 70f87e0f0a:README | tail -c 1 | od -An -a
> nl
&g
On Wed, Jul 20, 2016 at 5:29 PM, Eric Blake wrote:
> On 07/20/2016 01:39 PM, Pranith Kumar wrote:
>> Signed-off-by: Pranith Kumar
>> ---
>> README | 44 +---
>> 1 file changed, 21 insertions(+), 23 deletions(-)
>>
>
be seen here:
https://github.com/pranith/qemu/tree/markdown
Pranith Kumar (3):
Revert e5dfc5e8e("Move README to markdown")
Update README to accomodate markdown format
Create README.md as a symlink to README
v2:
- Fix wrong commit hash in the subject of patch 1
- Update with com
201 - 300 of 460 matches
Mail list logo
