Re: [PATCH] RISC-V: Add support for Ztso

2022-10-13 Thread Andrea Parri
> > AFAICT, Ztso allows the forwarding in question too. Simulations with > > the axiomatic formalization confirm such expectation: > > OK that seems to be what it says in: > https://five-embeddev.com/riscv-isa-manual/latest/ztso.html > 'In both of these memory models, it is the that allows a

Re: [PATCH] RISC-V: Add support for Ztso

2022-10-13 Thread Andrea Parri
> > > Is x86's brand of memory ordering strong enough for Ztso? > > > I thought x86 had an optimisation where it was allowed to store forward > > > within the current CPU causing stores not to be quite strictly ordered. [...] > then a bit further down, '8.2.3.5 Intra-Processor Forwarding Is

Re: [PATCH] RISC-V: Add support for Ztso

2022-10-13 Thread Dr. David Alan Gilbert
* Andrea Parri (and...@rivosinc.com) wrote: > > > > Is x86's brand of memory ordering strong enough for Ztso? > > > > I thought x86 had an optimisation where it was allowed to store forward > > > > within the current CPU causing stores not to be quite strictly ordered. > > [...] > > > then a bit

Re: [PATCH] RISC-V: Add support for Ztso

2022-10-03 Thread Dr. David Alan Gilbert
* Palmer Dabbelt (pal...@rivosinc.com) wrote: > On Thu, 29 Sep 2022 12:16:48 PDT (-0700), dgilb...@redhat.com wrote: > > * Palmer Dabbelt (pal...@rivosinc.com) wrote: > > > Ztso, the RISC-V extension that provides the TSO memory model, was > > > recently frozen. This provides support for Ztso on

Re: [PATCH] RISC-V: Add support for Ztso

2022-10-02 Thread Palmer Dabbelt
On Thu, 29 Sep 2022 12:16:48 PDT (-0700), dgilb...@redhat.com wrote: * Palmer Dabbelt (pal...@rivosinc.com) wrote: Ztso, the RISC-V extension that provides the TSO memory model, was recently frozen. This provides support for Ztso on targets that are themselves TSO. Signed-off-by: Palmer

Re: [PATCH] RISC-V: Add support for Ztso

2022-09-29 Thread Dr. David Alan Gilbert
* Palmer Dabbelt (pal...@rivosinc.com) wrote: > Ztso, the RISC-V extension that provides the TSO memory model, was > recently frozen. This provides support for Ztso on targets that are > themselves TSO. > > Signed-off-by: Palmer Dabbelt > > --- > > diff --git a/tcg/i386/tcg-target.h

Re: [PATCH] RISC-V: Add support for Ztso

2022-09-17 Thread Palmer Dabbelt
On Sat, 17 Sep 2022 01:02:46 PDT (-0700), Richard Henderson wrote: On 9/16/22 14:52, Palmer Dabbelt wrote: Though, honestly, I've had patches to add the required barriers sitting around for the last few releases, to better support things like x86 on aarch64.  I should just finish that up. I

Re: [PATCH] RISC-V: Add support for Ztso

2022-09-17 Thread Richard Henderson
On 9/16/22 14:52, Palmer Dabbelt wrote: Though, honestly, I've had patches to add the required barriers sitting around for the last few releases, to better support things like x86 on aarch64.  I should just finish that up. I can just do that for the RISC-V TSO support?  Like the cover letter

Re: [PATCH] RISC-V: Add support for Ztso

2022-09-16 Thread Palmer Dabbelt
On Sat, 03 Sep 2022 17:47:54 PDT (-0700), richard.hender...@linaro.org wrote: On 9/2/22 04:44, Palmer Dabbelt wrote: -#define TCG_GUEST_DEFAULT_MO 0 +/* + * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and + * fetch), and WMO is approximately equivilant to Arm MCA. Rather

Re: [PATCH] RISC-V: Add support for Ztso

2022-09-03 Thread Richard Henderson
On 9/2/22 04:44, Palmer Dabbelt wrote: -#define TCG_GUEST_DEFAULT_MO 0 +/* + * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and + * fetch), and WMO is approximately equivilant to Arm MCA. Rather than + * enforcing orderings on most accesses, just default to the target

[PATCH] RISC-V: Add support for Ztso

2022-09-01 Thread Palmer Dabbelt
Ztso, the RISC-V extension that provides the TSO memory model, was recently frozen. This provides support for Ztso on targets that are themselves TSO. Signed-off-by: Palmer Dabbelt --- My first thought was to just add the TCG barries to load/store and AMOs that as defined by Ztso, but after