Hi Peter,
On Fri, May 31, 2024, 6:53 PM Peter Maydell
wrote:
> On Fri, 3 May 2024 at 17:53, Dorjoy Chowdhury
> wrote:
> >
> > On Fri, May 3, 2024 at 10:28 PM Peter Maydell
> wrote:
> > >
> > > On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury
> wrote:
> > > >
> > > > Some ARM CPUs advertise
On Fri, 3 May 2024 at 17:53, Dorjoy Chowdhury wrote:
>
> On Fri, May 3, 2024 at 10:28 PM Peter Maydell
> wrote:
> >
> > On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury
> > wrote:
> > >
> > > Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> > > to 1 in the MPIDR
On Sat, May 4, 2024 at 7:31 PM Peter Maydell wrote:
>
> On Fri, 3 May 2024 at 19:14, Dorjoy Chowdhury wrote:
> >
> > On Fri, May 3, 2024 at 10:28 PM Peter Maydell
> > wrote:
> > > In the meantime, there is one tiny bit of this that we can
> > > do now:
> > >
> > > > diff --git
On Fri, 3 May 2024 at 19:14, Dorjoy Chowdhury wrote:
>
> On Fri, May 3, 2024 at 10:28 PM Peter Maydell
> wrote:
> > In the meantime, there is one tiny bit of this that we can
> > do now:
> >
> > > diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> > > index cc68b5d8f1..9d5dcf1a3f 100644
> > >
On Fri, May 3, 2024 at 10:28 PM Peter Maydell wrote:
>
> On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury wrote:
> >
> > Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> > to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
> > bits, CPU id in Aff1[15:8]
On Fri, May 3, 2024 at 10:28 PM Peter Maydell wrote:
>
> On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury wrote:
> >
> > Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> > to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
> > bits, CPU id in Aff1[15:8]
On Fri, 19 Apr 2024 at 19:31, Dorjoy Chowdhury wrote:
>
> Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
> to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
> bits, CPU id in Aff1[15:8] bits and cluster id in Aff2[23:16] bits in
> MPIDR.
>
> On the
On Thu, 2 May 2024 at 14:50, Marcin Juszkiewicz
wrote:
> Both hw/arm/sbsa-ref.c and hw/arm/virt.c build cpu information in
> DeviceTree using "arm_build_mp_afinnity()" function. So if firmware
> parses it then it gets wrong values.
What wrong values? The values in the dtb should match the
Aff*
W dniu 2.05.2024 o 15:13, Peter Maydell pisze:
On Thu, 2 May 2024 at 14:11, Marcin Juszkiewicz
wrote:
W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
Should "return" also have "(1 << 24) |" to have MT=1 set?
Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
cluster0.
On Thu, 2 May 2024 at 14:11, Marcin Juszkiewicz
wrote:
>
> W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
> >> Should "return" also have "(1 << 24) |" to have MT=1 set?
> >>
> >> Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
> >> cluster0.
> >>
> >> Value 0x1000100
W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
Should "return" also have "(1 << 24) |" to have MT=1 set?
Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
cluster0.
Value 0x1000100 shows MT=1 so thread0 in core1 in cluster0.
I don't know all the details but from what
On Thu, May 2, 2024 at 6:14 PM Marcin Juszkiewicz
wrote:
>
> W dniu 19.04.2024 o 20:31, Dorjoy Chowdhury pisze:
> > -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
> > +uint64_t arm_build_mp_affinity(ARMCPU *cpu, int idx, uint8_t clustersz)
> > {
> > +if (cpu->has_smt) {
> > +
W dniu 19.04.2024 o 20:31, Dorjoy Chowdhury pisze:
-uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
+uint64_t arm_build_mp_affinity(ARMCPU *cpu, int idx, uint8_t clustersz)
{
+if (cpu->has_smt) {
+/*
+ * Right now, the ARM CPUs with SMT supported by QEMU only
On Thu, 2 May 2024 at 11:56, Marcin Juszkiewicz
wrote:
>
> W dniu 2.05.2024 o 12:37, Peter Maydell pisze:
> >> * what are the constraints on the Aff* fields (eg that kernel
> >> commit suggests Aff0 shouldn't be > 15)?
>
> > This one is apparently related to GICv3 -- if the GIC doesn't
> >
W dniu 2.05.2024 o 12:37, Peter Maydell pisze:
* what are the constraints on the Aff* fields (eg that kernel
commit suggests Aff0 shouldn't be > 15)?
This one is apparently related to GICv3 -- if the GIC doesn't
implement RangeSelector support in ICC_SGI0R_EL1 and other
places
On Thu, 2 May 2024 at 10:11, Peter Maydell wrote:
> On the QEMU side I guess we should strive to set up the MPIDR
> fields to something plausibly matching the topology as defined
> by the user on the command line. Unanswered questions:
>
> * I guess we need some kind of back-compat thing where
On Wed, 1 May 2024 at 19:08, Marcin Juszkiewicz
wrote:
>
> W dniu 22.04.2024 o 17:21, Richard Henderson pisze:
> >>> For Arm's CPUs they fall into two categories:
> >>> * older ones don't set MT in their MPIDR, and the Aff0
> >>> field is effectively the CPU number
> >>> * newer ones do
W dniu 22.04.2024 o 17:21, Richard Henderson pisze:
For Arm's CPUs they fall into two categories:
* older ones don't set MT in their MPIDR, and the Aff0
field is effectively the CPU number
* newer ones do set MT in their MPIDR, but don't have
SMT, so their Aff0 is always 0 and their
On Mon, Apr 22, 2024 at 5:26 PM Peter Maydell wrote:
>
> On Mon, 22 Apr 2024 at 11:46, Peter Maydell wrote:
> >
> > On Sun, 21 Apr 2024 at 06:40, Richard Henderson
> > wrote:
> > > > --- a/target/arm/cpu.c
> > > > +++ b/target/arm/cpu.c
> > > > @@ -1314,8 +1314,18 @@ static void
On 4/22/24 08:21, Richard Henderson wrote:
For Arm's CPUs they fall into two categories:
* older ones don't set MT in their MPIDR, and the Aff0
field is effectively the CPU number
* newer ones do set MT in their MPIDR, but don't have
SMT, so their Aff0 is always 0 and their Aff1
On 4/22/24 04:26, Peter Maydell wrote:
On Mon, 22 Apr 2024 at 11:46, Peter Maydell wrote:
On Sun, 21 Apr 2024 at 06:40, Richard Henderson
wrote:
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
}
On Mon, 22 Apr 2024 at 11:46, Peter Maydell wrote:
>
> On Sun, 21 Apr 2024 at 06:40, Richard Henderson
> wrote:
> > > --- a/target/arm/cpu.c
> > > +++ b/target/arm/cpu.c
> > > @@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE
> > > *f, int flags)
> > > }
> > > }
>
On Sun, 21 Apr 2024 at 06:40, Richard Henderson
wrote:
> > --- a/target/arm/cpu.c
> > +++ b/target/arm/cpu.c
> > @@ -1314,8 +1314,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE
> > *f, int flags)
> > }
> > }
> >
> > -uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
> >
On Sun, Apr 21, 2024 at 11:40 AM Richard Henderson
wrote:
>
> On 4/19/24 11:31, Dorjoy Chowdhury wrote:
> > +
> > +/*
> > + * Instantiate a temporary CPU object to build mp_affinity
> > + * of the possible CPUs.
> > + */
> > +cpuobj = object_new(ms->cpu_type);
> > +armcpu
On 4/19/24 11:31, Dorjoy Chowdhury wrote:
+
+/*
+ * Instantiate a temporary CPU object to build mp_affinity
+ * of the possible CPUs.
+ */
+cpuobj = object_new(ms->cpu_type);
+armcpu = ARM_CPU(cpuobj);
+
for (n = 0; n < ms->possible_cpus->len; n++) {
Some ARM CPUs advertise themselves as SMT by having the MT[24] bit set
to 1 in the MPIDR register. These CPUs have the thread id in Aff0[7:0]
bits, CPU id in Aff1[15:8] bits and cluster id in Aff2[23:16] bits in
MPIDR.
On the other hand, ARM CPUs without SMT have the MT[24] bit set to 0,
CPU id
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