On Tue, Oct 8, 2019 at 2:00 AM Bin Meng wrote:
> My gdb does not list "priv" register after applying this patch.
I didn't try the patch, I didn't have time for that. I would expect
priv to be in the "info registers" output if you are adding it to the
cpu register set. Shrug. Anyways, defining
Hi Jim,
On Tue, Oct 8, 2019 at 5:17 AM Jim Wilson wrote:
>
> On 10/4/19 8:16 AM, Jonathan Behrens wrote:
> > diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> > index 0d07aaec85..d6d76aafd8 100644
> > --- a/gdb-xml/riscv-32bit-cpu.xml
> > +++ b/gdb-xml/riscv-32bit-cpu.xml
On Mon, Oct 7, 2019 at 2:36 PM Alistair Francis wrote:
> On Fri, Oct 4, 2019 at 8:18 AM Jonathan Behrens wrote:
> > @@ -296,6 +302,14 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t
> > *mem_buf, int n)
> > } else if (n == 32) {
> > env->pc = ldtul_p(mem_buf);
> >
On Mon, Oct 7, 2019 at 5:17 PM Jim Wilson wrote:
> On 10/4/19 8:16 AM, Jonathan Behrens wrote:
> > diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> > index 0d07aaec85..d6d76aafd8 100644
> > --- a/gdb-xml/riscv-32bit-cpu.xml
> > +++ b/gdb-xml/riscv-32bit-cpu.xml
> > @@
On 10/4/19 8:16 AM, Jonathan Behrens wrote:
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
index 0d07aaec85..d6d76aafd8 100644
--- a/gdb-xml/riscv-32bit-cpu.xml
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -44,4 +44,5 @@
+
Adding this to the cpu register set
On Fri, Oct 4, 2019 at 8:18 AM Jonathan Behrens wrote:
>
> This patch enables a debugger to read and write the current privilege level
> via
> a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
> still visible but is hardwired to zero.
>
> Signed-off-by: Jonathan
On Fri, Oct 4, 2019 at 11:18 PM Jonathan Behrens wrote:
>
> This patch enables a debugger to read and write the current privilege level
> via
> a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
> still visible but is hardwired to zero.
>
> Signed-off-by: Jonathan
This patch enables a debugger to read and write the current privilege level via
a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
still visible but is hardwired to zero.
Signed-off-by: Jonathan Behrens
---
gdb-xml/riscv-32bit-cpu.xml | 1 +
