On Wed, May 19, 2021 at 06:00:18PM +0800, Chenyi Qiang wrote:
>
>
> On 5/18/2021 3:46 AM, Eduardo Habkost wrote:
> > +Stefan
> >
> > I have a question about ratelimit_set_speed() below:
> >
> > On Fri, Apr 30, 2021 at 06:33:05PM +0800, Chenyi Qiang wrote:
> > > A bus lock is acquired through
On 5/18/2021 3:46 AM, Eduardo Habkost wrote:
+Stefan
I have a question about ratelimit_set_speed() below:
On Fri, Apr 30, 2021 at 06:33:05PM +0800, Chenyi Qiang wrote:
A bus lock is acquired through either split locked access to writeback
(WB) memory or any locked access to non-WB memory.
On Mon, May 17, 2021 at 03:46:29PM -0400, Eduardo Habkost wrote:
> > +X86MachineState *x86ms = X86_MACHINE(ms);
> > +
> > +qemu_mutex_lock(_lock_ratelimit_lock);
> > +uint64_t delay_ns =
> > ratelimit_calculate_delay(>bus_lock_ratelimit_ctrl, 1);
> > +
+Stefan
I have a question about ratelimit_set_speed() below:
On Fri, Apr 30, 2021 at 06:33:05PM +0800, Chenyi Qiang wrote:
> A bus lock is acquired through either split locked access to writeback
> (WB) memory or any locked access to non-WB memory. It is typically >1000
> cycles slower than an
+Cc qemu-devel@nongnu.org
On 5/14/2021 9:07 AM, Chenyi Qiang wrote:
Hi Paolo, Eduardo
Any comments on this version?
On 4/30/2021 6:33 PM, Chenyi Qiang wrote:
A bus lock is acquired through either split locked access to writeback
(WB) memory or any locked access to non-WB memory. It is
Patchew URL:
https://patchew.org/QEMU/20210430103305.28849-1-chenyi.qi...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210430103305.28849-1-chenyi.qi...@intel.com
Subject: [PATCH v3] i386: Add ratelimit
A bus lock is acquired through either split locked access to writeback
(WB) memory or any locked access to non-WB memory. It is typically >1000
cycles slower than an atomic operation within a cache and can also
disrupts performance on other cores.
Virtual Machines can exploit bus locks to degrade
